Texas Instruments TUSB2077APTR, TUSB2077APT Datasheet
TUSB2077A
7-PORT HUB FOR THE UNIVERSAL SERIAL BUS
WITH OPTIONAL SERIAL EEPROM INTERFACE
SLLS414 – MARCH 2000
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Universal Serial Bus (USB) Version 1.1
Compliant
D
Integrated USB Transceivers
D
3.3-V Low Power ASIC Logic
D
Two Power Source Modes
– Self-powered Mode Supporting Seven
Downstream Ports
– Bus-powered Mode Supporting Four
Downstream Ports
D
All Downstream Ports Support Full-Speed
and Low-Speed Operations
D
Power Switching and Overcurrent
Reporting is Provided Per Port or Ganged
D
Supports Suspend and Resume Operations
D
Suspend Status Terminal Avaliable for
External Logic Power Down
D
Supports Custom Vendor ID and Product ID
With External Serial EEPROM
D
3-State EEPROM Interface to Allow
EEPROM Sharing
D
Push-Pull Outputs for PWRON Eliminate
the Need for External Pullup Resistors
D
Noise Filtering on OVRCUR Provides
Immunity to Voltage Spikes
D
Supports 6-MHz Operation Through Crystal
Input or 48-MHz Input Clock
D
New Functional Pins Introduced to Reduce
the Board Material Cost
– 3 LED Indicator Control Outputs
Enable Visualized Monitoring of 6
Different Hub/Port Status (HUBCFG,
PORTPWR, PORTDIS)
– Output Pin Available to Disable
External Pullup Resistor on DP0 for 15
ms After Reset or After Change on
BUSPWR
and Enable Easy
Implementation of On-Board Bus/Self
Power Dynamic Switching Circuitry
D
Available in 48-Pin LQFP† Package
EXTMEM
OVRCUR3
OVRCUR2
PWRON7
DP6
DM6
OVRCUR6
PWRON6
DP5
DM5
OVRCUR5
PWRON5
DP4
DM4
OVRCUR4
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
SUSPND
DP0PUR
DP0
DM0
GND
RESET
EECLK
EEDATA/GANGED
V
CC
BUSPWR
PWRON1
OVRCUR1
HUBCFG
DM7
MODEVXTAL1/CLK48
XTAL2
DP3
PWRON4
GND
DM2
DP2
PWRON3
DM3
OVRCUR7
GND
PORTPWR
DP1
DM1
PT PACKAGE
(TOP VIEW)
393837
46
4443424140
474845
202122
23
13141516172418
19
DP7
PORTDIS
PWRON2
CC
NC – No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1997, Texas Instruments Incorporated
JEDEC descriptor S–PQFP–G for low-profile quad flatpack (LQFP)
TUSB2077A
7-PORT HUB FOR THE UNIVERSAL SERIAL BUS
WITH OPTIONAL SERIAL EEPROM INTERFACE
SLLS414 – MARCH 2000
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description
The TUSB2077A hub is a 3.3-V CMOS device that provides up to seven down stream ports in compliance with
the USB version 1.1 specification. Because this device is implemented with a digital state machine instead of
a microcontroller, no software programming is required. Fully compliant USB transceivers are integrated into
the ASIC for all upstream and downstream ports. The downstream ports support both full-speed and low-speed
devices by automatically setting the slew rate according to the speed of the device attached to the ports. The
configuration of the BUSPWR
terminal selects either the bus-powered or the self-powered mode. The
introduction of the DP0 pull-up resistor disable pin, DP0PUR, makes it much easier to implement an on-board
bus/self-power dynamic-switching circuitry. The three LED indicator control output pins also enable the
implementation of visualized status monitoring of the hub and its downstream ports. With these new function
pins, the end equipment vendor can considerably reduce the total board cost while adding additional product
value.
The EXTMEM (Pin 47) enables or disables the optional EEPROM interface. When EXTMEM is high, the vendor
and product IDs (VID and PID) use defaults, such that the message displayed during enumeration is
General
Purpose USB Hub
. For this configuration, pin 8 functions as the GANGED input pin and the EECLK (Pin 7) is
unused. If custom VID and PID descriptors are desired, the EXTMEM
must be tied low (EXTMEM = 0) and a
SGS Thompson M93C46 or equivalent EEPROM must be used to store the programmable VID, PID and
GANGED value. For this configuration, pin 7 and pin 8 function as the EEPROM interface signals with pin 7 as
EECLK and pin 8 as EEDATA respectively.
The TUSB2077A supports both bus-powered and self-powered modes. External power management devices
such as the TPS2044 are required to control the 5 V-power source switching (on/of f) to the downstream ports
and detect over-current condition from the downstream ports individually or ganged. Outputs from external
power devices provide over-current inputs to the TUSB2077A OVRCUR pins in case of an over-current
condition, the corresponding PWRON
pins will be disabled by the TUSB2077A. In the ganged mode, all
PWRON signals transitions simultaneously , and any OVRCUR input can be used. In the nonganged mode, the
PWROR outputs and OVRCUR inputs operate on a per port basis.
The TUSB2077A provides the flexibility of using either a 6-MHz or a 48-MHz clock. The logic level of the MODE
terminal controls the selection of the clock source. When MODE is low, the output of the internal APLL circuitry
is selected to drive the internal core of the chip. When MODE is high, the XT AL1 input is selected as the input
clock source and the APLL circuitry is powered down and bypassed. The internal oscillator cell is also powered
down while MODE is high. For 6-MHz operation, TUSB2077A requires a 6-MHz clock signal on XT AL1 pin (with
XT AL2 for a crystal) from which its internal APLL circuitry generates a 48 MHz internal clock to sample the data
from the upstream port. For 48-MHz operation, the clock cannot be generated with a crystal, using the XT AL2
output, since the internal oscillator cell only supports fundamental frequency . If low power suspend and resume
are desired, a passive crystal or resonator must be used, although the hub supports the flexibility of using any
device that generates a 6-MHz clock. Because most oscillators cannot be stopped while power is on, their use
prohibits low-power suspend, which depends on disabling the clock. When the oscillator is used, by connecting
its output to XTAL1 terminal and leaving XTAL2 terminal open, its TTL output level can not exceed 3.6 V. If a
6 MHz oscillator is used, it must be stopped at logic low whenever SUSPND is high. For crystal or resonator
implementations, the XT AL1 terminal is the input and the XTAL2 terminal is used as the feedback path. A sample
crystal tuning circuit is shown in Figure 7.
TUSB2077A
7-PORT HUB FOR THE UNIVERSAL SERIAL BUS
WITH OPTIONAL SERIAL EEPROM INTERFACE
SLLS414 – MARCH 2000
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
45
6
47
8
7
Hub Repeater
Suspend/Resume
Logic and
Frame Timer
SIE
SIE Interface
Logic
Port 1
Logic
Hub/Device
Command
Decoder
Hub
Power
Logic
OVRCUR1 – OVRCUR7
PWRON1 – PWRON7
XTAL1/CLK 48
OSC/PLL
DP0 DM0
34
USB
Transceiver
DP7 DM7
DP1 DM1
14 13
12, 16, 20, 25, 29, 33, 37
11, 15, 19, 23,28, 32, 36
RESET
USB
Transceiver
Serial
EEPROM
Interface
EXTMEM
EEDATA/GANGED
EECLK
USB
Transceiver
39 38
Port 4
Logic
10
BUSPWR
1
SUSPND
41
PORTPWR
42
PORTDIS
40
HUBCFG
MODE
M
U
X
44
XTAL2
1
0
48
2
DP0PUR
TUSB2077A
7-PORT HUB FOR THE UNIVERSAL SERIAL BUS
WITH OPTIONAL SERIAL EEPROM INTERFACE
SLLS414 – MARCH 2000
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NAME NO.
I/O
DESCRIPTION
BUSPWR 10 I Power source indicator. BUSPWR is an active low input that indicates whether the downstream ports
source their power from the USB cable or a local power supply. For the bus-power mode, this pin should
be pulled low, and for the self–powered mode, this pin should be pulled to 3.3 V . Input must not change
dynamically during operation.
DM0 4 I/O Root port USB differential data minus. DM0 paired with DP0 constitutes the upstream USB port.
DM1 – DM7 13, 17, 21, 26,
30, 34, 38
I/O USB differential data minus. DM1 – DM7 paired with DP1 – DP7 support up to seven downstream USB
ports.
DP0 3 I/O Root port USB differential data plus. DP0 paired with DM0 constitutes the upstream USB port.
DP1 – DP7 14, 18, 22, 27,
31, 35, 39
I/O USB differential data plus. DP1 – DP7 paired with DM1 – DM7 support up to seven downstream USB
ports.
DP0PUR 2 O Pull-up resistor connection. When a system reset happens (RESET being driven to low, but not USB
reset) or any logic level change on BUSPWR terminal, DP0PUR output is inactive (floating) until the
internal counter reaches a 15 ms time period. After the counter expires, DP0PUR is driven to the V
CC
(3.3 V) level thereafter until the next system reset event occurs or there is a BUSPWR
logic level
change.
EECLK 7 O EEPROM serial clock. When EXTMEM is high, the EEPROM interface is disabled. The EECLK pin is
disabled and should be left floating (unconnected). When EXTMEM is low, EECLK acts as a 3-state
serial clock output to the EEPROM with a 100 µA internal pulldown.
EEDATA/
GANGED
8 I/O EEPROM serial data/power management mode indicator. When EXTMEM is low, EEDATA/
GANGED acts as a serial data I/O for the EEPROM and is internally pulled down with a 100 µA
pulldown. When EXTMEM
is high, EEDATA/GANGED selects between gang or per port power
over–current detection for the downstream ports. This standard TTL input must not change dynamically
during operation.
EXTMEM 47 I EEPROM read enable. When EXTMEM is high, the serial EEPROM interface of the device is disabled.
When EXTMEM
is low, terminals 7 and 8 are configured as the clock and data pins of the serial
EEPROM interface, respectively.
GND 5, 24, 43 Ground. GND terminals must be tied to ground for proper operation.
HUBCFG
†
40 O Hub configured. Used to control LED indicator. When the hub is configured, HUBCFG is high, which
can be used to turn on a green LED. When the hub is not configured, HUBCFG is low, which can be
used to turn on a red LED.
MODE 48 I Mode select. When MODE is low, the APLL output clock is selected as the clock source to drive the
internal core of the chip and 6-MHz crystal or oscillator can used. When MODE is high, the clock on
XTAL1/CLK48 is selected as the clock source and 48-MHz oscillator or other on-board clock source
can be used.
OVRCUR1 –
OVRCUR7
12, 16, 20, 25,
29, 33, 37
I Over-current input. OVRCUR1 – OVRCUR7 are active low. For per-port over current detection, one
over-current input is available for each of the seven downstream ports. In the ganged mode, any
OVRCUR
input may be used and all OVRCUR pins should be tied together. OVRCUR pins have noise
filtering logic.
PORTPWR
†
41 O Any port powered. Used to control LED indicator. When any port is powered on, PORTPWR is high,
which can be used to turn on a green LED. When all ports are off, PORTPWR is low , which can be used
to turn on a red LED.
PORTDIS
†
42 O No ports disabled. PORTDIS is used for LED indicator control. When no port is disabled, PORTDIS is
high, which can be used to turn on a green LED. When any port is disabled, PORTDIS is low, which
can be used to turn on a red LED.
PWRON1 –
PWRON7
11, 15, 19, 23,
28, 32, 36
O Power-on/-off control signals. PWRON1 – PWRON7 are active low, push-pull outputs that enables the
external power switch device. Push-pull outputs eliminate the pull-up resistors which are required by
for open-drain outputs. However, the external power switches that connect to these pins must be able
to operate with 3.3-V inputs because these outputs cannot drive 5-V signals.
RESET 6 I Reset. RESET is an active low TTL input with hysteresis and must be asserted at power up. When
RESET is asserted, all logic is initialized. Generally, a reset with a pulse width between 100 µs and 1
ms is recommended after 3.3-V VCC reaching its 90%. The clock signal must be active during the last
60 µs of the reset window.
TUSB2077A
7-PORT HUB FOR THE UNIVERSAL SERIAL BUS
WITH OPTIONAL SERIAL EEPROM INTERFACE
SLLS414 – MARCH 2000
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions (Continued)
TERMINAL
NAME NO.
I/O
DESCRIPTION
SUSPND 1 O Suspend status. SUSPND is an active high output available for external logic power down operations.
During the SUSPEND mode, SUSPND is high. SUSPND is low for normal operation.
V
CC
9, 46 3.3-V supply voltage.
XTAL1/CLK48 45 I Crystal 1/48-MHz Clock Input. When MODE is low, XTAL1/CLK48 is a 6-MHz crystal input with 50%
duty cycle. An internal APLL generates the 48-MHz and 12-MHz clocks used internally by the ASIC
logic. When MODE is high, XTAL1/CLK48 acts as the input of the 48 MHz clock and the internal APLL
logic is bypassed.
XTAL2 44 O Crystal 2. XTAL2 is a 6-MHz crystal output. This terminal should be left open when using an oscillator.
†
All LED control are 3-stated during low-power suspend.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, VCC (see Note 1) –0.5 V to 3.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltgage range, VI –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
, (VI < 0 V or VI > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK, (VO < 0 V or V
O
> VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage levels are with respect to GND.
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, V
CC
3 3.3 3.6 V
Input voltage, TTL/LVCMOS‡, V
I
0 V
CC
V
Output voltage, TTL/LVCMOS§, V
O
0 V
CC
V
High-level input voltage, signal-ended receiver, V
IH(REC)
2 V
CC
V
Low-level input voltage, signal-ended receiver, V
IL(REC)
0.8 V
High-level input voltage, TTL/LVCMOS‡, V
IH(TTL)
2 V
CC
V
Low-level input voltage, TTL/LVCMOS‡, V
IL(TTL)
0 0.8 V
Operating free-air temperature, T
A
0 70 °C
External series, differential driver resistor, R
(DRV)
22 Ω
Operating (DC differential driver) high speed mode, f
(OPRH)
12 Mb/s
Operating (DC differential driver) low speed mode, f
(OPRL)
1.5 Mb/s
Common mode, input range, differential receiver , V
(ICR)
0.8 2.5 V
Input transition times (tr and tf), TTL/LVCMOS‡ 0 25 ns
Junction temperature range, T
J
¶
0 115 °C
‡
Applies for input and bidirectional buffers
§
Applies for output and bidirectional buffers
¶
These junction temperatures reflect simulated conditions. Absolute maximum junction temperature is 150°C. The customer is responsible for
verifying junction temperature.
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