TUSB2046B
4-PORT HUB FOR THE UNIVERSAL SERIAL BUS
WITH OPTIONAL SERIAL EEPROM INTERFACE
SLLS413 – FEBRUARY 2000
D
Universal Serial Bus (USB) Version 1.1
Compliant
D
32-Pin LQFP† Package With a 0.8 mm Pin
Pitch
D
3.3-V Low Power ASIC Logic
D
Integrated USB Transceivers
D
State Machine Implementation Requires No
Firmware Programming
D
One Upstream Port and Four Downstream
Ports
D
All Downstream Ports Support Full-Speed
and Low-Speed Operations
D
Two Power Source Modes
– Self-Powered Mode
– Bus-Powered Mode
D
Power Switching and Over-current
Reporting is Provided Ganged or Per Port
D
Supports Suspend and Resume Operations
D
Supports Programmable Vendor ID and
Product ID With External Serial EEPROM
D
3-State EEPROM Interface Allows EEPROM
Sharing
D
Push-Pull Outputs for PWRON Eliminate
the Need for External Pullup Resistors
D
Noise Filtering on OVRCUR Provides
Immunity to Voltage Spikes
D
Package Pinout Allows 2-Layer PCB
D
Low EMI Emission Achieved by a 6-MHz
Crystal Input
D
Migrated From Proven TUSB2040 Hub
D
Lower Cost Than the TUSB2040 Hub
D
Enhanced System ESD Performance
D
Supports 6 MHz Operation Through a
Crystal Input or a 48 MHz Input Clock
description
DP0
DM0
V
CC
RESET
EECLK
EEDATA/GANGED
GND
BUSPWR
VF PACKAGE
(TOP VIEW)
SUSPND
TSTMODE
XTAL1
XTAL2
32 26
31 30 29 28 27
1
2
3
4
5
6
7
8
11 12 13 14 15
910
DP1
DM1
PWRON1
OVRCUR1
GND
PWRON2
CC
TSTPLL/48MCLK
EXTMEM
V
25
24
23
22
21
20
19
18
17
16
DP2
DM2
OVRCUR2
DP4
DM4
OVRCUR4
PWRON4
DP3
DM3
OVRCUR3
PWRON3
The TUSB2046B is a 3.3-V CMOS hub device that provides one upstream port and four downstream ports in
compliance with the 1.1 Universal Serial Bus (USB) specification. Because this device is implemented with a
digital state machine instead of a microcontroller, no firmware programming is required. Fully compliant USB
transceivers are integrated into the ASIC for all upstream and downstream ports. The downstream ports support
both full-speed and low-speed devices by automatically setting the slew rate according to the speed of the
device attached to the ports. The configuration of the BUSPWR pin selects either the bus-powered or the
self-powered mode.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†
JEDEC descriptor S-PQFP-G for low profile quad flat pack (LQFP).
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 2000, Texas Instruments Incorporated
1
TUSB2046B
4-PORT HUB FOR THE UNIVERSAL SERIAL BUS
WITH OPTIONAL SERIAL EEPROM INTERFACE
SLLS413 – FEBRUARY 2000
description (continued)
Configuring the GANGED input determines the power switching and over-current detection modes for the
downstream ports. External power management devices such as the TPS2044 are required to control the 5-V
source to the downstream ports according to the corresponding values of the PWRON pin. Upon detecting any
over-current conditions, the power management device sets the corresponding OVRCUR
TUSB2046B to a logic low. If GANGED is high, all PWRON outputs switch together and if any OVRCUR is
activated, all ports transition to power off state. If GANGED is low, the PWRON outputs and OVRCUR inputs
operate on a per port basis.
The TUSB2046B provides the flexibility of using a 6-MHz or a 48-MHz clock. The logic level of the TSTMODE
terminal controls the selection of the clock source. When TSTMODE is low, the output of the internal APLL
circuitry is selected to drive the internal core of the chip. When TSTMODE is high, the TSTPLL/48MCLK input
is selected as the input clock source and the APLL circuitry is powered down and bypassed. The internal
oscillator cell is also powered down while TSTMODE is high.
Low EMI emission is achieved because the TUSB2046B is able to utilize a 6 MHz crystal input. Connect the
crystal as shown in Figure 6. An internal PLL then generates the 48 MHz clock used to sample data from the
upstream port and to synchronize the 12 MHz used for the USB clock. If low power suspend and resume are
desired, a passive crystal or resonator must be used. However, a 6-MHz oscillator may be used by connecting
the output to the XTAL1 terminal and leaving the XTAL2 terminal open. The oscillator TTL output must not
exceed 3.6 V.
pin of the
For 48-MHz operation, the clock can not be generated with a crystal, using the XT AL2 output, since the internal
oscillator cell only supports fundamental frequency.
Refer to Figure 7 and Figure 8 in the
input clock configuration.
The EXTMEM pin enables or disables the optional EEPROM interface. When the EXTMEM pin is high, the
product ID (PID) displayed during enumeration is the general-purpose USB hub. For this default, pin 5 is
disabled and pin 6 functions as the GANGED input pin. If custom PID and Vendor ID (VID) descriptors are
desired, the EXTMEM
EEPROM interface with pin 5 and pin 6 functioning as the EECLK and EEDATA, respectively. See Table 1 for
a description of the EEPROM memory map.
Other useful features of the TUSB2046B include a package with a 0.8 mm pin pitch for easy PCB routing and
assembly , push-pull outputs for the PWRON pins eliminate the need for pullup resistors required by traditional
open collector I/Os, and OVRCUR pins have noise filtering for increased immunity to voltage spikes.
pin must be low (EXTMEM = 0). For this configuration, pin 5 and pin 6 function as the
input clock configuration
section for more detailed information regarding
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
Hub Repeater
DP0 DM0
12
USB
Transceiver
Suspend/Resume
Logic and
Frame Timer
TUSB2046B
4-PORT HUB FOR THE UNIVERSAL SERIAL BUS
WITH OPTIONAL SERIAL EEPROM INTERFACE
SLLS413 – FEBRUARY 2000
32
SUSPND
27
TSTPLL/48MCLK
30
XTAL1
29
XTAL2
4
RESET
26
EXTMEM
6
EEDATA/GANGED
5
EECLK
SIE Interface
Logic
OSC/PLL
SIE
Serial
EEPROM
Interface
Port 4
Logic
USB
Transceiver
24 23
DP4 DM4
Port 3
Logic
USB
Transceiver
20 19
Port 2
Logic
USB
Transceiver
16 15
DP2 DM2DP3 DM3
Port 1
Logic
Transceiver
12 11
USB
DP1 DM1
Hub/Device
Command
Decoder
Hub
Power
Logic
10, 14, 18, 22
9, 13, 17, 21
8
BUSPWR
OVRCUR1 – OVRCUR4
PWRON1 – PWRON4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
TUSB2046B
I/O
DESCRIPTION
4-PORT HUB FOR THE UNIVERSAL SERIAL BUS
WITH OPTIONAL SERIAL EEPROM INTERFACE
SLLS413 – FEBRUARY 2000
Terminal Functions
TERMINAL
NAME NO.
BUSPWR 8 I Power source indicator. BUSPWR is an active high input that indicates whether the downstream ports
DM0 2 I/O Root port USB differential data minus. DM0 paired with DP0 constitutes the upstream USB port.
DM1 – DM4 11, 15,
DP0 1 I/O Root port USB differential data plus. DP0 paired with DM0 constitutes the upstream USB port.
DP1 – DP4 12, 16,
EECLK 5 O EEPROM serial clock. When EXTMEM is high, the EEPROM interace is disabled. The EECLK pin is
EEDATA/
GANGED
EXTMEM 26 I EEPROM read enable. When EXTMEM is high, the serial EEPROM interface of the device is disabled.
GND 7, 28 Ground. GND terminals must be tied to ground for proper operation.
OVRCUR1 –
OVRCUR4
PWRON1 –
PWRON4
RESET 4 I Reset. RESET is an active low TTL input with hysteresis and must be asserted at power up. When RESET
SUSPND 32 O Suspend status. SUSPND is an active high output available for external logic power down operations.
TSTMODE 31 I T est/Mode pin. TSTMODE is used as a test pin during production testing. This pin must be tied to ground
TSTPLL/48MCLK 27 I/O Test/48MHz clock input. TSTPLL/48MCLK is used as a test pin during production testing. This pin must
V
CC
XTAL1 30 I Crystal 1. XT AL1 is a 6-MHz crystal input with 50% duty cycle. An internal PLL generates the 48-MHz and
XTAL2 29 O Crystal 2. XTAL2 is a 6-MHz crystal output. This terminal should be left open when using an oscillator.
19, 23
20, 24
6 I/O EEPROM serial data/power management mode indicator. When EXTMEM is high, EEDATA/GANGED
10, 14,
18, 22
9, 13,
17, 21
3, 25 3.3-V supply voltage
source their power from the USB cable or a local power supply. For the bus-power mode, this pin should
be pulled to 3.3 V, and for the self-powered mode, this pin should be pulled low. Input must not change
dynamically during operation.
I/O USB differential data minus. DM1 – DM4 paired with DP1 – DP4 support up to four downstream USB ports.
I/O USB differential data plus. DP1 – DP4 paired with DM1 – DM4 support up to four downstream USB ports.
disabled and should be left floating (unconnected). When EXTMEM
clock output to the EEPROM with a 100 µA internal pulldown.
selects between gang or per-port power over-current detection for the downstream ports. When EXTMEM
is low, EEDAT A/GANGED acts as a serial data I/O for the EEPROM and is internally pulled down with a
100 µA pulldown. This standard TTL input must not change dynamically during operation.
When EXTMEM
interface, respectively .
I Over-current input. OVRCUR1 – OVRCUR4 are active low. For per-port over current detection, one
over-current input is available for each of the four downstream ports. In the ganged mode, any OVRCUR
input may be used and all OVRCUR pins should be tied together. OVRCUR pins are active low inputs with
noise filtering logic.
O Power-on/-off control signals. PWRON1 – PWRON4 are active low, push-pull outputs. Push-pull outputs
eliminate the pullup resistors which open-drain outputs require. However, the external power switches that
connect to these pins must be able to operate with 3.3-V inputs because these outputs cannot drive 5-V
signals.
is asserted, all logic is initialized. Generally, a reset with a pulse width between 100 µs and 1 ms is
recommended after 3.3 V VCC reaching its 90%. Clock signal has to be active during the last 60 µs of the
reset window.
During the suspend mode, SUSPND is high. SUSPND is low for normal operation.
or 3.3 V VCC for normal 6 MHz or 48 MHz operation, respectively.
be tied to ground for normal 6 MHz operation. If 48 MHz input clock is desired, a 48 MHz clock source (no
crystal) can be connected to this input pin.
12-MHz clocks used internally by the ASIC logic.
is low, terminals 5 and 6 are configured as the clock and data pins of the serial EEPROM
is low, EECLK acts as a 3-state serial
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TUSB2046B
4-PORT HUB FOR THE UNIVERSAL SERIAL BUS
WITH OPTIONAL SERIAL EEPROM INTERFACE
SLLS413 – FEBRUARY 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC (see Note 1) –0.5 V to 3.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
–0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
Input clamp current, IIK, (VI < 0 V or VI > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK, (VO < 0 V or V
Storage temperature range, T
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
> VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
Operating free-air temperature range, TA 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage levels are with respect to GND.
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, V
Input voltage, TTL/LVCMOS, V
Output voltage, TTL/LVCMOS, V
High-level input voltage, signal-ended receiver, V
Low-level input voltage, signal-ended receiver, V
High-level input voltage, TTL/LVCMOS, V
Low-level input voltage, TTL/LVCMOS, V
Operating free-air temperature, T
External series, differential driver resistor, R
Operating (dc differential driver) high speed mode, f
Operating (dc differential driver) low speed mode, f
Common mode, input range, differential receiver , V
Input transition times, tt, TTL/LVCMOS 0 25 ns
Junction temperature range, T
CC
I
O
IH(REC)
IL(REC)
IH(TTL)
IL(TTL)
A
(DRV)
(OPRH)
(OPRL)
(ICR)
J
3 3.3 3.6 V
0 V
0 V
2 V
2 V
0 0.8 V
0 70 °C
22 (–5%) 22 (5%) Ω
0.8 2.5 V
0 115 °C
CC
CC
CC
0.8 V
CC
12 Mb/s
1.5 Mb/s
V
V
V
V
†
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
TUSB2046B
USB data lines
USB data lines
V
Positi
V
N
V
I
(V
VT–)
IOZHigh-impedance output current
ICCInput supply current
4-PORT HUB FOR THE UNIVERSAL SERIAL BUS
WITH OPTIONAL SERIAL EEPROM INTERFACE
SLLS413 – FEBRUARY 2000
electrical characteristics over recommended ranges of operating free-air temperature and supply
voltage (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
V
OH
V
OL
IT+
IT–
hys
I
IL
I
IH
z
o(DRV)
V
ID
†
Applies for input buffers with hysteresis
‡
Applies for open drain buffers
High-level output voltage
Low-level output voltage
ve input threshold voltage
egative-input threshold voltage
nput hysteresis†
p
Low-level input current TTL/LVCMOS VI = GND –1 µA
High-level input current TTL/L VCMOS VI = V
Driver output impedance USB data lines Static VOH or V
Differential input voltage USB data lines 0.8 V ≤ V
p
pp
T+
p
–
TTL/LVCMOS IOH = –4 mA VCC –
R
= 15 kΩ, to GND 2.8
(DRV)
IOH = –12 mA (without R
TTL/LVCMOS IOL = 4 mA 0.5
R
= 1.5 kΩ to 3.6 V 0.3
(DRV)
IOL = 12 mA (without R
TTL/LVCMOS 1.8 V
Single-ended
TTL/LVCMOS 0.8 V
Single-ended
TTL/LVCMOS 0.3 0.7 V
Single-ended 0.8 V ≤ V
TTL/LVCMOS V = VCC or GND
USB data lines 0 V ≤ VO ≤ V
0.8 V ≤ V
0.8 V ≤ V
Normal operation 40 mA
Suspend mode 1 µA
≤ 2.5 V 1.8 V
ICR
≤ 2.5 V 1 V
ICR
≤ 2.5 V 300 500 mV
ICR
‡
CC
CC
OL
≤ 2.5 V 0.2 V
ICR
) VCC –
(DRV)
) 0.5
(DRV)
0.5
V
0.5
V
±10 µA
±10 µA
1 µA
7.1 19.9 Ω
differential driver switching characteristics over recommended ranges of operating free-air
temperature and supply voltage, C
full speed mode
PARAMETER TEST CONDITIONS MIN MAX UNIT
t
r
t
f
t
(RFM
V
O(CRS)
§
Characterized only. Limits are approved by design and are not production tested.
low speed mode
t
r
t
f
t
(RFM)
V
O(CRS)
§
Characterized only. Limits are approved by design and are not production tested.
Transition rise time for DPor DM See Figure 1 and Figure 2 4 20 ns
Transition fall time for DPor DM See Figure 1 and Figure 2 4 20 ns
Rise/fall time matching
Signal crossover output voltage
PARAMETER TEST CONDITIONS MIN MAX UNIT
Transition rise time for DPor DM
Transition fall time for DPor DM
Rise/fall time matching
Signal crossover output voltage
§
§
= 50 pF (unless otherwise noted)
L
(tr/tf) × 100 90% 110%
§
§
CL = 200 pF to 600 pF, See Figure 1 and Figure 2 75 300 ns
§
§
CL = 200 pF to 600 pF, See Figure 1 and Figure 2 75 300 ns
(tr/tf) × 100 80% 120%
CL = 200 pF to 600 pF 1.3 2.0 V
1.3 2.0 V
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TUSB2046B
4-PORT HUB FOR THE UNIVERSAL SERIAL BUS
WITH OPTIONAL SERIAL EEPROM INTERFACE
SLLS413 – FEBRUARY 2000
DP
22 Ω
DM
22 Ω
Figure 1. Differential Driver Switching Load
t
f
DM
DP
NOTE: The tr/tf ratio is measured as t
90%
10%
90%
10%
t
r
Figure 2. Differential Driver Timing Waveforms
1.5
Characterization
measurement point
15 kΩ
15 kΩ
r(DP)/tf(DM)
and t
C
L
C
L
90%
10%
r(DM)/tf(DP)
V(
= V
TERM)
Full
Low
90%
10%
at each crossover point.
t
f
t
r
CC
1.5 kΩ
V
OH
V
OL
1.3
1
0.5
0.2
– Differential Receiver Input Sensitivity – V
ID
V
0
012
0.8
V
– Common Mode Input Range – V
ICR
34
2.5
3.6
Figure 3. Differential Receiver Input Sensitivity vs Common Mode Input Range
V
V
V
0 V
CC
IH
IL
IT–
V
hys
Logic high
V
IT+
V
Logic low
Figure 4. Single-Ended Receiver Input Signal Parameter Definitions
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
TUSB2046B
4-PORT HUB FOR THE UNIVERSAL SERIAL BUS
WITH OPTIONAL SERIAL EEPROM INTERFACE
SLLS413 – FEBRUARY 2000
APPLICATION INFORMATION
A major advantage of USB is the ability to connect 127 functions configured in up to six logical layers (tiers) to
a single personal computer (see Figure 5).
PC
With Root Hub
Monitor
Modem Telephone
With 4-Port Hub
(Self-Powered)
Scanner
Printer
Digital
Scanner
Left
Speaker
Keyboard
With 4-Port Hub
(Bus-Powered)
Mouse
With 4-Port Hub (Self-Powered)
Right
Speaker
Figure 5. USB Tiered Configuration Example
Another advantage of USB is that all peripherals are connected using a standardized four-wire cable that
provides both communication and power distribution. The power configurations are bus-powered and
self-powered modes. The maximum current that may be drawn from the USB 5-V line during power up is
100 mA. For the bus-powered mode, a hub can draw a maximum of 500 mA from the 5-V line of the USB cable.
A bus-powered hub must always be connected downstream to a self-powered hub unless it is the only hub
connected to the PC and there are no high-powered functions connected downstream. In the self-powered
mode, the hub is connected to an external power supply and can supply up to 500 mA to each downstream port.
High-powered functions may draw a maximum of 500 mA from each downstream port and may only be
connected downstream to self-powered hubs. Per the USB specification, in the bus-powered mode, each
downstream port can provide a maximum of 100 mA of current, and in the self-powered mode, each
downstream port can provide a maximum of 500 mA of current.
Both bus-powered and self-powered hubs require over-current protection for all downstream ports. The two
types of protection are individual port management (individual port basis) or ganged port management (multiple
port basis). Individual port management requires power management devices for each individual downstream
port, but adds robustness to the USB system because, in the event of an over-current condition, the USB host
only powers down the port that has the condition. The ganged configuration uses fewer power management
devices and thus has lower system costs, but in the event of an over-current condition on any of the downstream
ports, all the ganged ports are disabled by the USB host.
Using a combination of the BUSPWR and EEDA T A/GANGED inputs, the TUSB2046B supports four modes of
power management: bus-powered hub with either individual port power management or ganged port power
management, and the self-powered hub with either individual port power management or ganged port power
management. Texas Instruments supplies the complete hub solution because we offer this TUSB2046B, the
TUSB2077 (7–port) and the TUSB2140B (4-port with I
2
C) hubs along with the power management chips
needed to implement a fully USB Specification 1.1 compliant system.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TUSB2046B
4-PORT HUB FOR THE UNIVERSAL SERIAL BUS
WITH OPTIONAL SERIAL EEPROM INTERFACE
SLLS413 – FEBRUARY 2000
APPLICATION INFORMATION
USB design notes
The following sections provide block diagram examples of how to implement the TUSB2046B device. Note,
even though no resistors are shown, pullup, pulldown and series resistors mustl be used to properly implement
this device.
Figure 6 is an example of how to generate the 6 MHz clock signal.
C
L
XTAL1 XTAL2
R
d
C2C1
NOTE A: Figure 6 assumes a 6 MHz fundamental crystal that is parallel loaded. The component values of C1, C2 and Rd are determined using
a crystal from Fox Electronics – part number HC49U–6.00MHz30\50\0 ±70\20 which means ±30 ppm at 25°C and 50 ppm from 0°C
to 70°C. The characteristics for the crystal include a load capacitance (CL) of 20 pF , maximum shunt capacitance (Co) of 7 pF, and
the maximum ESR of 50 Ω. In order to insure enough negative resistance, use C1 = C2 = 27 pF. The resistor Rd is used to trim the
gain, and Rd = 1.5 kΩ
is recommended.
Figure 6. Crystal Tuning Circuit
input clock configuration
The input clock configuration logic of TUSB2046B is enhanced to accept a 6 MHz crystal or 48 MHz on the board
clock source with a simple tie-off change on TSTMODE (pin 31).
D
A 6-MHz input clock configuration is shown in Figure 7.
In this mode, both TSTMODE and TSTPLL/48MCLK terminals must be tied to ground. The hub is configured
to use the 6 MHz clock on pin 30 and 29, which are XT AL1 and XTAL2 respectively on TUSB2046B. This
is identical as the TUSB2046.
TUSB2046B USB HUB
6 MHz
Clock Signal
30
XTAL1
29
XTAL2
31
TSTMODE
27
TSTPLL/48 MCLK
Figure 7. 6-MHz Input Clock Configuration
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
TUSB2046B
4-PORT HUB FOR THE UNIVERSAL SERIAL BUS
WITH OPTIONAL SERIAL EEPROM INTERFACE
SLLS413 – FEBRUARY 2000
APPLICATION INFORMATION
input clock configuration (continued)
D
A 48-MHz input clock configuration is shown in Figure 8.
In this mode, both TSTMODE and XT AL1 terminals must be tied to 3.3 V VCC. The hub accepts the 48 MHz
clock input on TSTPLL/48MCLK (pin 27). XTAL2 must be left floating (open) for this configuration. Only
oscillator or on board clock source is accepted for this mode. A crystal can not be used for this mode, since
the chips internal oscillator cell only supports fundamental frequency.
3.3 V
Open
48 MHz Oscillator
or on Board Clock Source
Figure 8. 48-MHz Input Clock Configuration
TUSB2046B USB HUB
30
XTAL1
29
XTAL2
31
TSTMODE
27
TSTPLL/48MCLK
Figure 9 is a block diagram example of how to connect the external EEPROM if a custom product ID and vendor
ID are desired.
Figure 10 shows the EEPROM read operation timing diagram. Figures 1 1, 12, and 13 illustrate how to connect
the TUSB2046B device for different power source and port power management combinations.
3.3 V
Power-On Reset
EEPROM
6
ORG
8
V
CC
5
V
SS
S
System
D
Q
C
1
6-MHz Clock
Signal
3
1 kΩ
4
2
TUSB2046B USB Hub
30
XTAL1
29
XTAL2
4
RESET
26
EXTMEM
1
DP0
2
DM0
6
EEDATA
5
EECLK
V
GND
DP1 – DP4
DM1 – DM4
OVRCUR1
OVRCUR4
PWRON1 –
PWRON4
CC
–
3, 25
7, 28
12, 16, 20, 24
11, 15, 19, 23
10, 14, 18, 22
9, 13, 17, 21
Regulator
5 V GND
Power
Switching
Bus or Local Power
4
4
4
GND
4
V
bus
USB Data lines
and Power to
Downstream
Ports
10
Figure 9. Typical Application of the TUSB2046B USB Hub
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TUSB2046B
4-PORT HUB FOR THE UNIVERSAL SERIAL BUS
WITH OPTIONAL SERIAL EEPROM INTERFACE
SLLS413 – FEBRUARY 2000
APPLICATION INFORMATION
programming the EEPROM
An SGS Thompson M93C46 EEPROM or equivalent is used for storing the programmable VID and PID. When
the EEPROM interface is enabled (EXTMEM
inside the TUSB2046B. The internal pulldowns are disabled when the EEPROM interface is disabled (EXTMEM
= 1).
The EEPROM is programmed with the three 16-bit locations as shown in Table 1. Connecting pin 6 of the
EEPROM high (ORG = 1) organizes the EEPROM memory into 64×16 bit words.
Table 1. EEPROM Memory Map
ADDRESS D15 D14 D13 D12–D8 D7–D0
00000 0
00001 VID High-byte VID Low-byte
00010 PID High-byte PID Low-byte
The D and Q signals of the EEPROM must be tied together using a 1-kΩ resistor with the common I/O operations
forming a single-wire bus. After system power-on reset, the TUSB2046B performs a one-time access read
operation from the EEPROM if the EXTMEM
connected to the system power-on reset. Initially , the EEDATA pin will be driven by the TUSB2046B to send a
start bit (1) which is followed by the read instruction (10) and the starting-word address (00000). Once the read
instruction is received, the instruction and address are decoded by the EEPROM, which then sends the data
to the output shift register. At this point, the hub stops driving the EEDATA pin and the EEPROM starts driving.
A dummy (0) bit is then output and the first three 16-bit words in the EEPROM are output with the most significant
bit (MSB) first.
= 0), the EECLK and EEDA TA are internally pulled down (100 µA)
GANGED 00000 00000 00000000
XXXXXXXX
pin is pulled low and the chip select(s) of the EEPROM is
The output data changes are triggered by the rising edge of the clock provided by the TUSB2046B on the EECLK
pin. The
SGS-Thompson M936C46
EEPROM is recommended because it advances to the next memory
location by automatically incrementing the address internally. Any EEPROM used must have the automatic
internal address advance function. After reading the three words of data from the EEPROM, the TUSB2046B
puts the EEPROM interface into a high-impedance condition (pulled down internally) to allow other logic to share
the EEPROM. The EEPROM read operation is summarized in Figure 10. For more details on EEPROM
operation, refer to
SGS-Thompson Microelectronics M93C46 Serial Microwire Bus EEPROM
data sheet.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
11
TUSB2046B
4-PORT HUB FOR THE UNIVERSAL SERIAL BUS
WITH OPTIONAL SERIAL EEPROM INTERFACE
SLLS413 – FEBRUARY 2000
APPLICATION INFORMATION
3-Stated
Pulldown
With Internal
MSB of
Fourth Word
LSB of
Third Word
Other
Data Bits
EEPROM Driving Data LineHub Driving Data Line
D15 D14 D0 XX
6 Bit Address (000000)Start Read OP Code(10) 48 Data Bits Don’t Care
First Word
MSB of The
Bit
A0 Dummy
Bits
Other
Address
A5 A1
Figure 10. EEPROM Read Operation Timing Diagram
Figure 10.
12
S
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
C
D
TUSB2046B
4-PORT HUB FOR THE UNIVERSAL SERIAL BUS
WITH OPTIONAL SERIAL EEPROM INTERFACE
SLLS413 – FEBRUARY 2000
APPLICATION INFORMATION
bus-powered hub, ganged port power management
When used in bus-powered mode, the TUSB2046B supports up to four downstream ports by controlling a
TPS2041 device which is capable of supplying 100 mA of current to each downstream port. Bus-powered hubs
must implement power switching to ensure current demand is held below 100 mA when the hub is hot-plugged
into the system. Utliizing the TPS2041 for ganged power management provides over-current protection for the
downstream ports. The SN75240 transient suppressors reduce inrush current and voltage spikes on the data
lines. The OVRCUR
signals should be tied together for a ganged operation.
Upstream
Port
D +
D –
5 V
GND
SN75240
A
C
B
D
4.7 µF
0.1 µF
6-MHz Clock
Signal
System
Power-On Reset
1.5 kΩ
†
3.3 V LDO
5 V
3.3 V
GND
3.3 V
3.3 V
§
4.7 µF
DP0
DM0
V
CC
XTAL1
XTAL2
EXTMEM
RESET
GND
TUSB2046B
BUSPWR
EEDATA/GANGED
PWRON1
PWRON2
PWRON3
PWRON4
OVRCUR1
OVRCUR2
OVRCUR3
OVRCUR4
DP1
DM1
DP2
DM2
DP3
DM3
DP4
DM4
3.3 V
15 kΩ
15 kΩ
15 kΩ
15 kΩ
SN75240
SN75240
TPS2041
EN IN
OUT
OUT
OUT
OC
ABC
ABC
†
IN
Downstream
Ports
D +
Ferrite Beads
D
†
15 kΩ
15 kΩ
D
†
15 kΩ
15 kΩ
1 µF
100 µF
Ferrite Beads
100 µF
Ferrite Beads
100 µF
Ferrite Beads
D –
GND
5 V
‡
D +
D –
GND
5 V
‡
D +
D –
GND
5 V
‡
D +
D –
GND
5 V
‡
†
TPS2041 and SN75240 are Texas Instruments devices.
‡
120 µF per hub is the minimum required per the USB specification, version 1.1. However, TI recommends a 100 µF low ESR tantulum capacitor
per port for immunity to voltage droop.
§
LDO is a 5 V to 3.3 V voltage regulator
100 µF
Figure 11. TUSB2046B Bus-Powered Hub, Ganged Port Power Management Application
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
13
TUSB2046B
4-PORT HUB FOR THE UNIVERSAL SERIAL BUS
WITH OPTIONAL SERIAL EEPROM INTERFACE
SLLS413 – FEBRUARY 2000
APPLICATION INFORMATION
self-powered hub, ganged port power management
The TUSB2046B can also be implemented for ganged port power management in a self-powered configuration.
The implementation is very similar to the bus-powered example with the exception that a self-powered port
supplies 500 mA of current to each downstream port. The over-current protection can be provided by a TPS2044
quad device or a TPS2024 single power switch.
Upstream
Port
D +
D –
5 V
GND
4.7 µF
0.1 µF
SN75240
A
C
B
D
†
3.3 V LDO
5 V
3.3 V
GND
1.5 kΩ
§
3.3 V
4.7 µF
DP0
DM0
V
CC
TUSB2046B
EEDATA/GANGED
BUSPWR
DP1
DM1
DP2
DM2
3.3 V
15 kΩ
15 kΩ
ABC
D
SN75240
15 kΩ
†
15 kΩ
Ferrite Beads
100 µF
Downstream
Ports
D +
D –
GND
5 V
‡
6-MHz Clock
Signal
System
Power-On Reset
3.3 V
XTAL1
XTAL2
EXTMEM
RESET
GND
DP3
DM3
DP4
DM4
PWRON1
PWRON2
PWRON3
PWRON4
OVRCUR1
OVRCUR2
OVRCUR3
OVRCUR4
15 kΩ
15 kΩ
15 kΩ
15 kΩ
TPS2044
EN2
EN3
EN4
OC1
OC2
OC3
OC4
IN1EN1
IN2
OUT1
OUT2
OUT3
OUT4
ABC
SN75240
†
D
0.1 µF
D +
D –
Ferrite Beads
GND
†
Ferrite Beads
Ferrite Beads
100 µF
100 µF
100 µF
5 V
‡
D +
D –
GND
5 V
‡
D +
D –
GND
5 V
‡
†
TPS2044, TPS2042, and SN75240 are Texas Instruments devices.
5 V Board Power
Supply
The TPS2024 can be substituted for the TPS2044.
‡
120 µF per hub is the minimum required per the USB specification, version 1.1. However, TI recommends a 100 µF low ESR tantulum capacitor
per port for immunity to voltage droop.
§
LDO is a 5 V to 3.3 V voltage regulator
Figure 12. TUSB2046B Self-Powered Hub, Ganged Port Power Management Application
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TUSB2046B
4-PORT HUB FOR THE UNIVERSAL SERIAL BUS
WITH OPTIONAL SERIAL EEPROM INTERFACE
SLLS413 – FEBRUARY 2000
APPLICATION INFORMATION
self-powered hub, individual port power management
In a self-powered configuration, the TUSB2046B can be implemented for individual port-power management
when used with the TPS2044 because it is capable of supplying 500 mA of current to each downstream port
and can provide current limiting on a per port basis. When the hub detects a fault on a downstream port, power
is removed from only the port with the fault and the remaining ports continue to operate normally . Self-powered
hubs are required to implement over-current protection and report overcurrent conditions. The SN75240
transient suppressors reduce inrush current and voltage spikes on the data lines.
DP0
DM0
V
CC
XTAL1
XTAL2
EXTMEM
RESET
GND
TUSB2046B
DP1
DM1
BUSPWR
EEDATA/GANGED
DP2
DM2
DP3
DM3
DP4
DM4
PWRON1
PWRON2
PWRON3
PWRON4
OVRCUR1
OVRCUR2
OVRCUR3
OVRCUR4
15 kΩ
15 kΩ
15 kΩ
15 kΩ
15 kΩ
15 kΩ
TPS2044
EN1
EN2
EN3
EN4
OUT1
OUT2
OUT3
OUT4
OC1
OC2
OC3
OC4
ABC
SN75240
SN75240
†
IN1
IN2
D
ABC
†
15 kΩ
15 kΩ
D
†
0.1 µF
Upstream
Port
D +
D –
5 V
GND
SN75240
A
C
B
D
4.7 µF
0.1 µF
6-MHz Clock
Signal
System
Power-On Reset
1.5 kΩ
†
3.3 V LDO
5 V
3.3 V
GND
3.3 V
3.3 V
§
4.7 µF
Downstream
Ports
D +
D –
GND
5 V
‡
100 µF
D +
D –
GND
5 V
‡
100 µF
D +
D –
GND
5 V
‡
100 µF
D +
D –
GND
5 V
‡
100 µF
†
TPS2042 and SN75240 are Texas Instruments devices. Two TPS2042 devices can be substituted for
5-V Board Power
Supply
the TPS2044.
‡
120 µF per hub is the minimum required per the USB specification, version 1.1. However, TI recommends a 100 µF low ESR tantulum capacitor
per port for immunity to voltage droop.
§
LDO is a 5 V to 3.3 V voltage regulator
Figure 13. TUSB2046B Self-Powered Hub, Individual Port-Power Management Application
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
15
TUSB2046B
4-PORT HUB FOR THE UNIVERSAL SERIAL BUS
WITH OPTIONAL SERIAL EEPROM INTERFACE
SLLS413 – FEBRUARY 2000
MECHANICAL DATA
VF (S-PQFP-G32) PLASTIC QUAD FLATPACK
25
32
0,80
1,45
1,35
24
0,45
0,30
17
16
9
1
5,60 TYP
7,20
SQ
6,80
9,20
SQ
8,80
8
0,22
M
0,05 MIN
0,13 NOM
Gage Plane
0,25
0°–7°
1,60 MAX
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
Seating Plane
0,10
0,75
0,45
4040172/C 10/96
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 2000, Texas Instruments Incorporated
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