Texas instruments TUSB1310 Data Manual

TUSB1310

USB 3.0 Transceiver

Data Manual

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Literature Number: SLLSE16C

December 2009–Revised August 2010

TUSB1310

SLLSE16C–DECEMBER 2009–REVISED AUGUST 2010

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Contents

1 PRODUCT OVERVIEW ......................................................................................................... 7

1.1 Features ...................................................................................................................... 7

1.2 Target Applications ......................................................................................................... 7

1.3 Introduction .................................................................................................................. 8

1.4 Functional Block Diagram .................................................................................................. 8

2 PIN DESCRIPTIONS ........................................................................................................... 10

2.1 Configuration Pins ......................................................................................................... 10

2.2 PIPE ......................................................................................................................... 10

2.3 ULPI ......................................................................................................................... 13

2.3.1 ULPI Modes ..................................................................................................... 13

2.4 Clocking ..................................................................................................................... 14

2.5 JTAG Interface ............................................................................................................. 14

2.6 Reset and Output Control Interface ..................................................................................... 14

2.7 Strap Options .............................................................................................................. 14

2.8 USB Interfaces ............................................................................................................. 15

2.9 Special Connect ........................................................................................................... 15

2.10 Power and Ground ........................................................................................................ 15

3 FUNCTIONAL DESCRIPTION ............................................................................................... 17

3.1 Power On and Reset ...................................................................................................... 17

3.1.1 RESETN and PHY_RESETN – Hardware Reset .......................................................... 17

3.1.2 ULPI Reset – Software Reset ................................................................................. 17

3.1.3 OUT_ENABLE - Output Enable .............................................................................. 17

3.1.4 Power Up Sequence ........................................................................................... 17

3.2 Clocks ....................................................................................................................... 18

3.2.1 Clock Distribution ............................................................................................... 18

3.2.2 Output Clock .................................................................................................... 18

3.3 Power Management ....................................................................................................... 18

3.3.1 USB Power Management ...................................................................................... 19

3.4 Receiver Status ............................................................................................................ 19

3.4.1 Clock Tolerance Compensation .............................................................................. 20

3.4.2 Receiver Detection ............................................................................................. 20

3.4.3 8b/10b Decode Errors .......................................................................................... 20

3.4.4 Elastic Buffer Errors ............................................................................................ 21

3.4.5 Disparity Errors ................................................................................................. 21

3.5 Loopback ................................................................................................................... 21

4 REGISTERS ...................................................................................................................... 22

4.1 Register Definitions ........................................................................................................ 22

4.2 Register Map ............................................................................................................... 22

4.2.1 Vendor ID and Product ID (00h-03h) ........................................................................ 22

4.2.2 Function Control (04h-06h) .................................................................................... 23

4.2.3 Interface Control (07h-09h) .................................................................................... 24

4.2.4 Debug (15h) ..................................................................................................... 24

4.2.5 Scratch Register (16-18h) ..................................................................................... 24

5 DESIGN GUIDELINES ......................................................................................................... 25

5.1 Chip Connection on PCB ................................................................................................. 25

5.1.1 USB Connector Pins Connection ............................................................................. 25

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5.1.2 Clock Connections .............................................................................................. 26

5.2 Clock Source Requirements ............................................................................................. 27

5.2.1 Clock Source Selection Guide ................................................................................ 27

5.2.2 Oscillator ......................................................................................................... 28

5.2.3 Crystal ............................................................................................................ 28

SLLSE16C–DECEMBER 2009–REVISED AUGUST 2010

6 ELECTRICAL SPECIFICATIONS .......................................................................................... 29

6.1 ABSOLUTE MAXIMUM RATINGS ...................................................................................... 29

6.2 RECOMMENDED OPERATING CONDITIONS ....................................................................... 29

6.3 DC CHARACTERISTICS FOR 1.8-V DIGITAL IO .................................................................... 29

6.4 DEVICE POWER CONSUMPTION ..................................................................................... 30

6.5 AC Characteristics ......................................................................................................... 30

6.5.1 Power Up and Reset Timing .................................................................................. 30

6.5.2 PIPE Transmit ................................................................................................... 31

6.5.3 PIPE Receive ................................................................................................... 31

6.5.4 ULPI Parameters ............................................................................................... 32

6.5.5 ULPI Clock ....................................................................................................... 32

6.5.6 ULPI Transmit ................................................................................................... 32

6.5.7 ULPI Receive Timing ........................................................................................... 33

6.5.8 Power State Transition Time .................................................................................. 33

TUSB1310

SLLSE16C–DECEMBER 2009–REVISED AUGUST 2010

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List of Figures

1-1 Typical Application................................................................................................................. 8

1-2 Functional Block Diagram ........................................................................................................ 9

3-1 Power Up Sequence............................................................................................................. 18

5-1 Analog Pin Connections......................................................................................................... 25

5-2 USB Standard-A Connector Pin Connection ................................................................................. 26

5-3 USB Standard-B Connector Pin Connection ................................................................................. 26

5-4 Typical Crystal Connections .................................................................................................... 27

6-1 Power Up and Reset Timing.................................................................................................... 30

6-2 PIPE Transmit Timing ........................................................................................................... 31

6-3 PIPE Receive Timing ............................................................................................................ 31

6-4 ULPI Transmit Timing............................................................................................................ 33

6-5 ULPI Receive Timing ............................................................................................................ 33

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SLLSE16C–DECEMBER 2009–REVISED AUGUST 2010

List of Tables

2-1 Configuration Pins................................................................................................................ 10

2-2 PIPE Signal Description ......................................................................................................... 10

2-3 ULPI Signal Description ......................................................................................................... 13

2-4 ULPI Synchronous and Low Power Mode Functions........................................................................ 13

2-5 Clock Signal Name Description ................................................................................................ 14

2-6 JTAG Signal Name Description ................................................................................................ 14

2-7 Reset and Output Control Signal Description ................................................................................ 14

2-8 Strapping Options ................................................................................................................ 14

2-9 USB Interface Signal Name Descriptions..................................................................................... 15

2-10 Special Connect Signal Descriptions .......................................................................................... 15

2-11 Power/Ground Signal Descriptions ............................................................................................ 15

3-1 Pin States in Chip Reset ........................................................................................................ 17

3-2 Power States...................................................................................................................... 19

3-3 PIPE Control Pin Matrix ......................................................................................................... 19

3-4 RX_STATUS - SKP .............................................................................................................. 20

3-5 RX_STATUS - Receiver Detection............................................................................................. 20

3-6 8b/10b Decode Errors ........................................................................................................... 21

3-7 Elastic Buffer Errors.............................................................................................................. 21

3-8 Disparity Errors ................................................................................................................... 21

4-1 Register Definitions .............................................................................................................. 22

4-2 Register Map...................................................................................................................... 22

4-3 Vendor ID and Product ID....................................................................................................... 22

4-4 Function Control .................................................................................................................. 23

4-5 Interface Control.................................................................................................................. 24

4-6 Debug.............................................................................................................................. 24

4-7 Scratch Register.................................................................................................................. 24

5-1 Oscillator Specification .......................................................................................................... 28

5-2 Oscillator Specification .......................................................................................................... 28

6-1 Power Up and Reset Timing.................................................................................................... 31

6-2 PIPE Transmit Timing ........................................................................................................... 31

6-3 PIPE Receive Timing ............................................................................................................ 31

6-4 ULPI Parameters ................................................................................................................. 32

6-5 ULPI Clock Parameters ......................................................................................................... 32

6-6 ULPI Transmit Timing............................................................................................................ 33

6-7 ULPI Transmit Timing............................................................................................................ 33

TUSB1310

SLLSE16C–DECEMBER 2009–REVISED AUGUST 2010

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TUSB1310

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SLLSE16C–DECEMBER 2009–REVISED AUGUST 2010

USB 3.0 Transceiver

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1 PRODUCT OVERVIEW

1.1 Features

• Universal Serial Bus (USB) – Single Port 5.0-Gbps USB 3.0 Physical Layer Transceiver

• One 5.0-Gbps SuperSpeed Conneciton

• One 480-Mbps HS/FS/LS Connection – Fully Compliant with USB 3.0 Specification – Supports 3+ Meters USB 3.0 Cable Length – Fully Adaptive Equalizer to Optimize Receiver Sensitivity – PIPE to Link Layer Controller

• Supports 16-Bit SDR Mode at 250 MHz

• Compliant With PHY Interface for the USB Architectures (PIPE), Version 3.0 – ULPI to Link Layer Controller

• Supports 8-Bit SDR Mode at 60 MHz

• Supports Synchronous Mode and Low Power Mode

• Compliant with UTMI+ Low Pin Interface (ULPI) Specification, Revision 1.1

• General Features – IEEE 1149.1 JTAG Support – IEEE 1149.6 JTAG support for the SuperSpeed Port – Operates on a Single Reference Clock Selectable from 20, 25, 30 or 40 MHz – 3.3-, 1.8-, and 1.1-V Supply Voltages – 1.8-V PIPE and ULPI I/O

– Available in Lead-Free 175-Ball 12- x 12-nF BGA Package (175ZAY)

1.2 Target Applications

• Surveillance Cameras

• Multimedia Handset

• Smartphone

• Digital Still Camera

• Portable Media Player

• Personal Navigation Device

• Audio Dock

• Video IP Phone

• Wireless IP Phone

• Software Defined Radio

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TUSB1310

SLLSE16C–DECEMBER 2009–REVISED AUGUST 2010

1.3 Introduction

The TUSB1310 is a single port, 5.0-Gbps USB 3.0 physical layer transceiver operating off of a single crystal or an external reference clock. The reference clock frequencies are selectable from 20, 25, 30, and 40 MHz. The TUSB1310 provides a clock to USB link layer controllers. The single reference clock allows the TUSB1310 to provide a cost effective USB 3.0 solution with few external components and a minimum implementation cost.

Link controller interfaces to the TUSB1310 are via a PIPE (SuperSpeed) and a ULPI (USB2.0) interface. The 16-bit PIPE operates with a 250-MHz interface clock. The ULPI supports 8-bit operations with a 60-MHz interface clock.

USB 3.0 reduces active power and idle power by improving power management. The PIPE interface controls the TUSB1310 low power states which minimizes power consumption.

SuperSpeed USB leverages existing USB software infrastructure by keeping the existing software interfaces and software drivers. In addition the SuperSpeed USB retains backward compatibility at the Type-A connector with USB2.0 based PCs and with USB2.0 cables.

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Figure 1-1. Typical Application

1.4 Functional Block Diagram

The USB physical layer handles the low level USB protocol and signaling. This includes data serialization and deserialization, 8b/10b encoding, analog buffers, elastic buffers and receiver detection. It shifts the clock domain of the data from the USB rate to one that is compatible with the link layer controller.

The SuperSpeed USB contains SSTXP/SSTXN and SSRXP/SSRXP differential pairs and uses the PIPE to communicate with the link layer controller. The Non-SuperSpeed USB has a DP/DM differential pair and communicates with the link layer controller via the ULPI. The TUSB1310 reference clock is connected to an internal crystal oscillator, spread spectrum clock and PLL which provides clocks to all blocks and to the CLKOUT pin for the link layer controller.

A JTAG interface is used for IEEE1149.1 and IEEE1149.6 boundary scan.

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Figure 1-2. Functional Block Diagram

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2 PIN DESCRIPTIONS

TYPE DESCRIPTION

I Input

O Output

I/O Input/output

PD, PU Internal pull-down / pull-up

S Strapping pin P Power Supply G Ground

2.1 Configuration Pins

The configuration pins are not latched by RESETN.

Table 2-1. Configuration Pins

SIGNAL NAME TYPE PIN NO. MODE NAME DESCRIPTION

PHY_MODE1 I, PD H12 USB Must be set to 0. Operates as USB 3.0 transceiver. PHY_MODE0 I, PU J12 USB Must be set to 1. Operates as USB 3.0 transceiver.

2.2 PIPE

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The TUSB1310 supports 16-bit SDR mode with a 250-MHz clock.

Table 2-2. PIPE Signal Description

SIGNAL NAME TYPE BALL NO. DESCRIPTION

TX_CLK I K1 TX_DATA15 G2

TX_DATA14 H2 TX_DATA13 H1 TX_DATA12 J2 TX_DATA11 L3 TX_DATA10 L2 TX_DATA9 M2 TX_DATA8 M1 TX_DATA7 N1 TX_DATA6 P1 TX_DATA5 N2 TX_DATA4 P2 TX_DATA3 N3 TX_DATA2 P3 TX_DATA1 N4 TX_DATA0 P5 TX_DATAK1 G1 TX_DATAK0 J1

PCLK O A6 to this clock. This clock operates at 250 MHz. The rising edge of the clock is the reference

I The 16 bits represent 2 symbols of transmit data where TX_DATA7-0 is the first symbol to

TX_DATA and TX_DATAK clock for source synchronous PIPE. This clock frequency is the same as PCLK frequency. The rising edge of the clock is the reference for all signals.

Parallel USB SuperSpeed data input bus. be transmitted, and TX_DATA15-8 is the second symbol.

Data/Control for the symbols of transmit data. TX_DATAK0 corresponds to the low-byte of TX_DATA, TX_DATAK1 to the upper byte.

Parallel interface data clock. All data movement across the parallel PIPE is synchronous for all signals.

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Table 2-2. PIPE Signal Description (continued)

SIGNAL NAME TYPE BALL NO. DESCRIPTION

RX_DATA15 B9 RX_DATA14 A9 RX_DATA13 A8 RX_DATA12 B8 RX_DATA11 B5 RX_DATA10 B4 RX_DATA9 A4 RX_DATA8 B3 RX_DATA7 A3 RX_DATA6 A2 RX_DATA5 B1 RX_DATA4 C2 RX_DATA3 C1 RX_DATA2 D1 RX_DATA1 D2 RX_DATA0 E2 RX_DATAK1 B7 Data/Control for the symbols of receive data. RX_DATAK0 corresponds to the low-byte of

RX_DATAK0 A7 RX_VALID O F1 Active High. Indicates symbol lock and valid data on RX_DATA and RX_DATAK.

CONTROL AND STATUS SIGNALS

PHY_RESETN I, PU J3 Active Low. Resets the transmitter and receiver. This signal is asynchronous. TX_DETRX_LPBK I, PD M6 TX_ELECIDLE I K3 Active High. Forces TX output to electrical idle depending on the power state. RX_ELECIDLE F3

RX_STATUS2 C7 RX_STATUS1 C6 BIT 2 BIT 1 BIT 0 DESCRIPTION

RX_STATUS0 C5 0 0 0 Received data OK

POWER_DOWN1 G3 Power up and down the transceiver power states. POWER_DOWN0 H3 BIT 1 BIT 0 DESCRIPTION

O The 16 bits represent 2 symbols of receive data where RX_DATA7-0 is the first symbol

O RX_DATA, RX_DATAK1 to the upper byte. A value of zero indicates a data byte; a value

S, I/O, Active High. While de-asserted with the PHY in P0, P1, P2, or P3, indicates detection of

PD LFPS.

Parallel USB SuperSpeed data output bus. received, and RX_DATA15-8 is the second.

of 1 indicates a control byte.

Active High. Used to tell the PHY to begin a receiver detection operation or to begin loopback.

Encodes receiver status and error codes for the received data stream when receiving data.

0 0 1 1 SKP ordered set added 0 1 0 1 SKP ordered set removed 0 1 1 Receiver detected 1 0 0 8B/10B decode error 1 0 1 Elastic buffer overflow

Elastic buffer underflow.

1 1 0 This error code is not used if the elasticity buffer is

operating in the nominal buffer empty mode.

1 1 1 Receive disparity error

0 0 P0, normal operation 0 1 P1, low recovery time latency, power saving state 1 0 P2, longer recovery time latency, low power state 1 1 P3, lowest power state

When transitioning from P3 to P0, the signaling is asynchronous.

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