PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
• USB2.0 PHY Transceiver Chip, Designed to• Complete HS-USB Physical Front-End:
Interface With a USB Controller via a ULPI
Interface, Fully Compliant With:
– Universal Serial Bus Specification Rev. 2.0
– On-The-Go Supplement to the USB 2.0Supporting 2 Clock Frequencies 19.2 MHz/26
• DP/DM Line External Component
Compensation (TI Patent Pending)
• Interfaces to Host, Peripheral and OTG Device
Cores; Optimized for Portable Devices or
System ASICs with Built-in USB OTG Device
Core
• Complete USB OTG Physical Front-End that
Supports Host Negotiation Protocol (HNP) and
Session Request Protocol (SRP)– Non-Return-to-Zero Inverted (NRZI)
• V
Overvoltage Protection Circuitry Protects
BUS
V
Pin in Range –2 V to 20 V– Supports Bus Reset, Suspend, Resume and
BUS
• Internal 5 V Short-Circuit Protection of DP, DM,
and ID Pins for Cable Shorting to V
Pin– HS USB DP/DM Impedance Programmability
BUS
• ULPI Interface:
– I/O Interface (1.8V) Optimized for
Non-Terminated 50 Ω Line Impedance– Control of External V
– ULPI CLOCK Pin (60 MHz) Supports Both
Input and Output Clock Configurations– V
– Fully Programmable ULPI-Compliant– Both Session Request Protocol (SRP)
Register SetMethods Supported: Data Pulsing and V
• Full Industrial Grade Operating Temperature
Range from –40°C to 85°C– Integrated V
• Available in a 32-Pin Quad Flat No Lead [QFN
(RHB)] Package• Internal Power-On Reset (POR) Circuit
• Can Be Interfaced to Peripheral, Host or OTG• Flexible System Integration and Very Low
Controller Devices via ULPI. Suited to PortableCurrent Consumption, Optimized for Portable
Devices or System ASICs with Built-InDevices
Controller Core.
The TUSB1210 is a USB2.0 transceiver chip, designed to interface with a USB controller via a ULPI
interface. It supports all USB2.0 data rates (High-Speed 480Mbps, Full-Speed 12 Mbps and Low-Speed
1.5Mbps) in both Host and Peripheral modes. It additionally supports a UART mode and legacy ULPI
serial modes.
TUSB1210 also supports the OTG (Ver1.3) optional addendum to the USB 2.0 Specification, including
Host Negotiation Protocol (HNP) and Session Request Protocol (SRP).
TUSB1210 is optimized to be interfaced through a 12-pin SDR UTMI Low Pin Interface (ULPI), supporting
both input clock and output clock modes, with 1.8 V interface supply voltage.
TUSB1210 integrates a 3.3 V LDO, which makes it flexible to work with either battery operated systems or
pure 3.3 V supplied systems. Both the main supply and the 3.3 V power domain can be supplied through
an external switched-mode converter for optimized power efficiency.
TUSB1210 includes a POR circuit to detect supply presence on V
disabled or configured in low power mode for energy saving.
TUSB1210 is protected against accidental shorts to 5 V or ground on its exposed interface (DP/DM/ID). It
is also protected against up to 20 V surges on V
TUSB1210 integrates a high-performance low-jitter 480 MHz PLL and supports two clock configurations.
Depending on the required link configuration, TUSB1210 supports both ULPI input and output clock mode
: input clock mode, in which case a square-wave 60 MHz clock is provided to TUSB1210 at the ULPI
interface CLOCK pin; and output clock mode in which case TUSB1210 can accept a square-wave
reference clock at REFCLK of either 19.2 MHz, 26 MHz. Frequency is indicated to TUSB1210 via the
configuration pin CFG. This can be useful if a reference clock is already available in the system.
BUS
SLLSE09D–NOVEMBER 2009–REVISED JANUARY 2011
BAT
and V
pins. TUSB1210 can be
DDIO
.
1
2.1Terminal Description
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TUSB1210
www.ti.com
SLLSE09D–NOVEMBER 2009–REVISED JANUARY 2011
Table 2-1. Terminal Functions
TERMINAL
NO.NAME
1REFCLKAI3.3 Vclock of amplitude in the range of 3 V to 3.6 V when Pin 26 (CLOCK) is
Reference clock input (square-wave only). Tie to GND when pin 26
DD33
(CLOCK) is required to be Input mode. Connect to square-wave reference
required to be Output mode. See pin 14 (CFG) description for REFCLK
input frequency settings.
ULPI NXT output signal
ULPI DATA input/output signal 0 synchronized to CLOCK
ULPI DATA input/output signal 1 synchronized to CLOCK
ULPI DATA input/output signal 2 synchronized to CLOCK
ULPI DATA input/output signal 3 synchronized to CLOCK
ULPI DATA input/output signal 4 synchronized to CLOCK
No connect
ULPI DATA input/output signal 5 synchronized to CLOCK
ULPI DATA input/output signal 6 synchronized to CLOCK
Active-high chip select pin. When low the IC is in power down and ULPI
bus is tri-stated. When high normal operation. Tie to V
ULPI DATA input/output signal 7 synchronized to CLOCK
REFCLK clock frequency configuration pin. Two frequencies are
supported: 19.2 MHz when 0, or 26 MHz when 1.
CMOS active-high digital output control of external 5V VBUS supply
DP pin of the USB connector
DM pin of the USB connector
3.3-V internal LDO output. Connect to external filtering capacitor.
Input supply voltage or battery source
BAT
V
BUS
pin of the USB connector
BUS
Identification (ID) pin of the USB connector
ApowerV
ApowerV
ApowerV
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
DD33
DD33
DD33
DD33
DD33
ULPI 60 MHz clock on which ULPI data is synchronized.
Two modes are possible:
DDIO
Input Mode: CLOCK defaults as an input.
Output Mode: When an input clock is detected on REFCLK pin (after 4
rising edges) then CLOCK will change to an output.
When low, all digital logic (except 32 kHz logic required for power up
sequencing) including registers are reset to their default values, and ULPI
bus is tri-stated. When high, normal USB operation.
External 1.8-V supply input. Connect to external filtering capacitor.
ULPI STP input signal
External 1.8-V supply input. Connect to external filtering capacitor.
ULPI DIR output signal
External 1.8V supply input for digital I/Os. Connect to external filtering
over operating free-air temperature range (unless otherwise noted)
PARAMETERCONDITIONSMINMAXUNIT
V
CC
Main battery supply voltage
Voltage on any input
V
input–220V
BUS
ID, DP, DM inputsStress condition guaranteed 24h–0.35.25V
V
T
T
T
DDIO
stg
A
J
IO supply voltageContinuous1.98V
Storage temperature range–55125°C
Ambient temperature range–4085°C
Ambient temperature range°C
Ambient temperature for parametricWith max 125°C as junction temperature
compliance
DP, DM, ID high voltage short circuitsupply, in any mode of TUSB1210 operation,5.25V
DP, DM, ID low voltage short circuitany mode of TUSB1210 operation,0V
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The product will have negligible reliability impact if voltage spikes of 5.5 V occur for a total (cumulative over lifetime) duration of 5
milliseconds.
(3) Except V
BAT
input, V
, ID, DP, and DM pads
BUS
(2)
(3)
Where supply represents the voltage applied
to the power supply pin associated with the–0.3 1 × VCC+0.3V
input
Absolute maximum rating–40150
For parametric compliance–40125
DP, DM or ID pins short circuited to V
continuously for 24 hours
DP, DM or ID pins short circuited to GND in
continuously for 24 hours
(1)
05V
–4085°C
BUS
3.2Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETERTEST CONDITIONSMINNOMMAX UNIT
V
BAT
V
BAT
CERT
V
DDIO
T
A
Battery supply voltage2.73.64.8V
Battery supply voltage for USB 2.0 compliancy
(USB 2.0 certification)
When V
When V
is supplied internally3.15V
DD33
is shorted to V
DD33
externally3.05
BAT
Digital IO pin supply1.711.98V
Ambient temperature range–4085°C
3.3ESD Electrical Parameters
over operating free-air temperature range (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
CDMCharged-Device Model stress voltageAll pads500V
HBMHuman-Body Model stress voltageAll pads2000V
The USB PLL block generates the clocks used to synchronize :
•the ULPI interface (60 MHz clock)
•the USB interface (depending on the USB data rate, 480 Mbps, 12 Mbps or 1.5 Mbps)
TUSB1210 requires an external reference clock which is used as an input to the 480 MHz USB PLL block.
Depending on the clock configuration, this reference clock can be provided either at REFCLK pin or at
CLOCK pin. By default CLK pin is configured as an input.
Two clock configurations are possible:
•Input clock configuration (see Section 4.2)
•Output clock configuration (see Section 4.3)
4.2ULPI Input Clock Configuration
In this mode REFCLK must be externally tied to GND. CLOCK remains configured as an input.
When the ULPI interface is used in “input clock configuration”, i.e., the 60 MHz ULPI clock is provided to
TUSB1210 on Clock pin, then this is used as the reference clock for the 480 MHz USB PLL block.
In this mode a reference clock must be externally provided on REFCLK pin When an input clock is
detected on REFCLK pin then CLK will automatically change to an output, i.e., 60 MHz ULPI clock is
output by TUSB1210 on CLK pin.
Two reference clock input frequencies are supported. REFCLK input frequency is communicated to
TUSB1210 via a configuration pin, CFG, see f
TUSB1210 supports square-wave reference clock input only. Reference clock input must be square-wave
of amplitude in the range 3.0 V to 3.6 V.
Table 4-2. Electrical Characteristics: REFCLK
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
REFCLK input duty cycle4060%
f
REFCLK
REFCLK nominal frequencyMHz
REFCLK input rise/fall time20%
REFCLK input frequency accuracy250ppm
REFCLK input integrated jitter600ps rms
When CFG pin is tied to GND19.2
When CFG pin is tied to V
In % of clock period t
All logic is reset if CS = 0 or V
All logic (except 32 kHz logic) is reset if V
PHY logic is reset when any supplies are not present (V
TUSB1210 may be reset manually by toggling the RESETB pin to GND for at lease 200 ns.
If manual reset via RESETB is not required then RESETB pin may be tied to V
This chapter describes the electrical characteristics of the voltage regulators and timing characteristics of
the supplies digitally controlled within the TUSB1210.
5.1Power Providers
Table 5-1. Summary of TUSB1210 Power Providers
NAMEUSAGETYPE
5.1.1V
The V
subchip inside TUSB1210. Table 5-2 describes the regulator characteristics.
(1) V
Regulator
DD33
DD33
V
DD15
V
DD18
V
DD33
may be supplied externally, or by shorting the V
DD33
range [3.2 V : 3.6 V]. Note that the V
irrespective of whether V
externally in the application, the electrical specs for this LDO are provided below.
internal LDO regulator powers the USB PHY, charger detection, and OTG functions of the USB
InternalLDO1.550
ExternalLDO1.830
InternalLDO3.115
DD33
TYPICALMAXIMUM
VOLTAGE (V)CURRENT (mA)
pin to V
LDO will always power-on when the chip is enabled,
DD33
is supplied externally or not. In the case the V
DD33
pin provided V
BAT
(1)
BAT
pin is not supplied
DD33
www.ti.com
min is in
V
Since the USB2.0 standard requires data lines to be biased with pullups biased from a supply greater than
3 V, and since V
TUSB1210 will not meet USB 2.0 Standard if operated from a battery whose voltage is lower than 3.3 V.
V
INVDD33
V
VDD33
I
VDD33
5.1.2V
The V
regulator takes its power from V
DD33
regulator has an inherent voltage drop from its input, V
The timing parameter symbols used in the timing requirement and switching characteristic tables are
created in accordance with JEDEC Standard 100. To shorten the symbols, some pin names and other
related terminologies have been abbreviated as shown in Table 6-1.
Table 6-1. Timing Parameter Definitions
SYMBOLPARAMETER
CCycle time (period)
DDelay time
DisDisable time
EnEnable time
HHold time
SuSetup time
STARTStart bit
TTransition time
VValid time
WPulse duration (width)
XUnknown, changing, or don't care level
HHigh
LLow
VValid
IVInvalid
AEActive edge
FEFirst edge
LELast edge
ZHigh impedance
www.ti.com
LOWERCASE SUBSCRIPTS
6.2Interface Target Frequencies
Table Table 6-2 assumes testing over the recommended operating conditions.
Table 6-2. TUSB1210 Interface Target Frequencies
IOINTERFACE DESIGNATIONTARGET
INTERFACEFREQUENCY
USBUniversalHigh speed480 Mbits/s
serial bus
Full speed12 Mbits/s
Low speed1.5 Mbits/s
1.5 V
6.3USB Transceiver
The TUSB1210 device includes a universal serial bus (USB) on-the-go (OTG) transceiver that supports
USB 480 Mb/s high-speed (HS), 12 Mb/s full-speed (FS), and USB 1.5 Mb/s low-speed (LS) through a
12-pin UTMI+ low pin interface (ULPI).
Table 6-3, Table 6-4, and Table 6-5 show the status of each of the 12 ULPI pins including input/output
direction and whether output pins are driven to ‘0’ or to ‘1’, or pulled up/pulled down via internal
pullup/pulldown resistors.
Note that pullup/pulldown resistors are automatically replaced by driven ‘1’/’0’ levels respectively once
internal IORST is released, with the exception of the pullup on STP which is maintained in all modes.
Pin assignment changes in ULPI 3-pin serial mode, ULPI 6-pin serial mode, and UART mode. Unused
pins are tied low in these modes as shown below.
Set-up time (control in, 8-bit data in)36ns
Hold time (control in, 8-bit data in)1.50ns
Output delay (control out, 8-bit data out)69ns
6.3.3PHY Electrical Characteristics
The PHY is the physical signaling layer of the USB 2.0. It essentially contains all the drivers and receivers
required for physical data and protocol signaling on the DP and DM lines.
The PHY interfaces to the USB controller through a standard 12-pin digital interface called UTMI+ low pin
interface (ULPI).
The transmitters and receivers inside the PHY are classified into two main classes.
•The full-speed (FS) and low-speed (LS) transceivers. These are the legacy USB1.x transceivers.
•The HS (HS) transceivers
In order to bias the transistors and run the logic, the PHY also contains reference generation circuitry
which consists of:
•A DPLL which does a frequency multiplication to achieve the 480-MHz low-jitter lock necessary for
USB and also the clock required for the switched capacitor resistance block.
•A switched capacitor resistance block which is used to replicate an external resistor on chip.
Built-in pullup and pulldown resistors are used as part of the protocol signaling.
Apart from this, the PHY also contains circuitry which protects it from accidental 5-V short on the DP and
DM lines.
6.3.3.1LS/FS Single-Ended Receivers
In addition to the differential receiver, there is a single-ended receiver (SE–, SE+) for each of the two data
lines D+/–. The main purpose of the single-ended receivers is to qualify the D+ and D– signals in the
full-speed/low-speed modes of operation.
Skew between VP and VMDriver outputs unloaded–202ns
Single-ended hysteresis50mV
High (driven)2V
Low0.8V
Switching threshold0.82V
6.3.3.2LS/FS Differential Receiver
A differential input receiver (Rx) retrieves the LS/FS differential data signaling. The differential voltage on
the line is converted into digital data by a differential comparator on DP/DM. This data is then sent to a
clock and data recovery circuit which recovers the clock from the data. An additional serial mode exists in
which the differential data is directly output on the RXRCV pin.
Table 6-8. LS/FS Differential Receiver
PARAMETERCOMMENTSMINTYPMAXUNIT
VDIDifferential input sensitivityRef. USB2.0200mV
VCMDifferential Common mode rangeRef. USB2.00.82.5V
6.3.3.3LS/FS Transmitter
The USB transceiver (Tx) uses a differential output driver to drive the USB data signal D+/– onto the USB
cable. The driver's outputs support 3-state operation to achieve bidirectional half-duplex transactions.
PARAMETERCOMMENTSMINTYPMAXUNIT
V
OL
V
OH
V
CRS
T
FR
T
FF
T
FRFM
T
FDRATE
T
DJ1
T
DJ2
T
FEOPT
V
CM
LowRef. USB2.00300mV
High (driven)Ref. USB2.02.83.6V
Output signal crossover voltageRef. USB2.0, covered by1.32V
Rise timeRef. USB2.0, covered by75300ns
Fall time75300ns
Differential rise and fall time matching80125%
Low-speed data rateRef. USB2.0, covered by1.47751.5225Mb/s
Source jitter total (includingTo next transitionRef. USB2.0, covered by-2525ns
frequency tolerance)eye diagram
Source SE0 interval of EOPRef. USB2.0, covered by1.251.5us
TFDRATE Full-speed data rateRef. USB2.0, covered by eye11.9712.03 Mb/s
T
DJ1
T
DJ2
TFEOPTSource SE0 interval of EOPRef. USB2.0, covered by eye160175ns
LowRef. USB2.00300mV
High (driven)Ref. USB2.02.83.6V
Ref. USB2.0, covered by eye1.32V
diagram
Rise timeRef. USB2.0420ns
Fall timeRef. USB2.0420ns
Differential rise and fall time matchingRef. USB2.0, covered by eye90111.1%
Driver output resistanceRef. USB2.02844Ω
Source jitter total (including
frequency tolerance)
Downstream eye diagramRef. USB2.0, covered by eye
Upstream eye diagram
To next transitionRef. USB2.0, covered by eye-22ns
For paired transitions-11
diagram1
diagram
diagram
diagram
diagram
6.3.3.4HS Differential Receiver
The HS receiver consists of the following blocks:
A differential input comparator to receive the serial data
•A squelch detector to qualify the received data
•An oversampler-based clock data recovery scheme followed by a NRZI decoder, bit unstuffing, and
serial-to-parallel converter to generate the ULPI DATAOUT
VHSCMHigh-speed data signaling common modeRef. USB2.0-50500mV
(differential signal amplitude)
(differential signal amplitude)
High-speed differential input signaling levelsRef. USB2.0, specified by eye patternmV
templates
voltage range (guidelines for receiver)
Receiver jitter toleranceRef. USB2.0, specified by eye pattern150ps
templates
6.3.3.5HS Differential Transmitter
The HS transmitter is always operated via the ULPI parallel interface. The parallel data on the interface is
serialized, bit stuffed, NRZI encoded, and transmitted as a dc output current on DP or DM depending on
the data. Each line has an effective 22.5-Ω load to ground, which generates the voltage levels for
signaling.
A disconnect detector is also part of the HS transmitter. A disconnect on the far end of the cable causes
the impedance seen by the transmitter to double thereby doubling the differential amplitude seen on the
DP/DM lines.
High-speed idle levelRef. USB2.0-1010mV
High-speed data signaling highRef. USB2.0360440mV
High-speed data signaling lowRef. USB2.0-1010mV
VCHIRPJChirp J level (differential voltage)Ref. USB2.07001100mV
VCHIRPK Chirp K level (differential voltage)Ref. USB2.0-900-500mV
THSRRise Time (10% - 90%)Ref. USB2.0, covered by eye diagram500ps
THSRFall time (10% - 90%)Ref. USB2.0, covered by eye diagram500ps
ZHSDRVDriver output resistance (which also serves asRef. USB2.040.549.5Ω
high-speed termination)
THSDRAT High-speed data rangeRef. USB2.0, covered by eye diagram479.76480. Mb/s
24
Data source jitterRef. USB2.0, covered by eye diagram
Downstream eye diagramRef. USB2.0, covered by eye diagram
Upstream eye diagramRef. USB2.0, covered by eye diagram
6.3.3.6UART Transceiver
In this mode, the ULPI data bus is redefined as a 2-pin UART interface, which exchanges data through a
direct access to the FS/LS analog transmitter and receiver.
ID Comparators — ID External Resistors Specifications
R
ID_GND
R
ID_FLOAT
R
PH_ID_UP
VP
H_ID_UP
ID ground comparatorID_GND interrupt122028kΩ
ID Float comparatorID_FLOAT interrupt200500kΩ
ID Line
Phone ID pullup to VPH_ID_UPID unloaded (V
Phone ID pullup voltageConnected to V
ID line maximum voltage5.25V
ADDRESS OFFSET0x00
PHYSICAL ADDRESS0x00INSTANCEUSB_SCUSB
DESCRIPTIONLower byte of vendor ID supplied by USB-IF (TI Vendor ID = 0x0451)
TYPER
WRITE LATENCY
BITSFIELD NAMEDESCRIPTIONTYPERESET
7:00VENDOR_IDR0x51
9.1.2VENDOR_ID_HI
ADDRESS OFFSET0x01
PHYSICAL ADDRESS0x01INSTANCEUSB_SCUSB
DESCRIPTIONUpper byte of vendor ID supplied by USB-IF (TI Vendor ID = 0x0451)
TYPER
WRITE LATENCY
SLLSE09D–NOVEMBER 2009–REVISED JANUARY 2011
76543210
VENDOR_ID
BITSFIELD NAMEDESCRIPTIONTYPERESET
7:00VEN DOR_IDR0x04
9.1.3PRODUCT_ID_LO
ADDRESS OFFSET0x02
PHYSICAL ADDRESS0x02INSTANCEUSB_SCUSB
DESCRIPTIONLower byte of Product ID supplied by Vendor (TUSB1210 Product ID is
DESCRIPTIONControls UTMI function settings of the PHY.
TYPERW
WRITE LATENCY
www.ti.com
76543210
PRODUCT_ID
CE
76543210
Reserved
BITSFIELD NAMEDESCRIPTIONTYPERESET
7ReservedR0
6SUSPENDMActive low PHY suspend. Put PHY into Low Power Mode. In Low PowerRW1
Mode the PHY power down all blocks except the full speed receiver, OTG
comparators, and the ULPI interface pins. The PHY automatically set this bit
to '1' when Low Power Mode is exited.
5RESETActive high transceiver reset. Does not reset the ULPI interface or ULPIRW0
register set.
Once set, the PHY asserts the DIR signal and reset the UTMI core. When the
reset is completed, the PHY de-asserts DIR and clears this bit. After
de-asserting DIR, the PHY re-assert DIR and send an RX command update.
Note: This bit is auto-cleared, this explain why it can't be read at '1'.
4:03OPMODESelect the required bit encoding style during transmitRW0x0
0x0: Normal operation
0x1: Non-driving
0x2: Disable bit-stuff and NRZI encoding
0x3: Reserved (No SYNC and EOP generation feature not supported)
2TERMSELECTControls the internal 1.5Kohms pull-up resistor and 45ohms HS terminations.RW0
Control over bus resistors changes depending on XcvrSelect, OpMode,
DpPulldown and DmPulldown.
ADDRESS OFFSET0x07
PHYSICAL ADDRESS0x07INSTANCEUSB_SCUSB
DESCRIPTIONEnables alternative interfaces and PHY features.
TYPERW
WRITE LATENCY
www.ti.com
7654321 0
AUTORESUME
INDICATORPASSTHRU
INDICATORCOMPLEMENT
INTERFACE_PROTECT_DISABLE
BITSFIELD NAMEDESCRIPTIONTYPERESET
7INTERFACE_PROTECT Controls circuitry built into the PHY for protecting the ULPI interface when theRW0
6INDICATORPASSTHRU Controls whether the complement output is qualified with the internalRW0
5INDICATORCOMPLEMTells the PHY to invert EXTERNALVBUSINDICATOR input signal, generatingRW0
4AUTORESUMEEnables the PHY to automatically transmit resume signaling.RW1
3CLOCKSUSPENDMActive low clock suspend. Valid only in Serial Modes. Powers down theRW0
_DISABLElink tri-states stp and data.
0b: Enables the interface protect circuit
1b: Disables the interface protect circuit
vbusvalid comparator before being used in the VBUS State in the RXCMD.
0b: Complement output signal is qualified with the internal VBUSVALID
comparator.
1b: Complement output signal is not qualified with the internal VBUSVALID
comparator.
ENTthe complement output.
0b: PHY will not invert signal EXTERNALVBUSINDICATOR (default)
1b: PHY will invert signal EXTERNALVBUSINDICATOR
Refer to USB specification 7.1.7.7 and 7.9 for more details.
0 = AutoResume disabled
1 = AutoResume enabled (default)
internal clock circuitry only. Valid only when SuspendM = 1b. The PHY must
ignore ClockSuspend when SuspendM = 0b. By default, the clock will not be
powered in Serial and Carkit Modes.
0b : Clock will not be powered in Serial and UART Modes.
1b : Clock will be powered in Serial and UART Modes.
2CARKITMODEChanges the ULPI interface to UART interface. The PHY automatically clearRW0
this field when UART mode is exited.
0b: UART disabled.
1b: Enable serial UART mode.
1FSLSSERIALMODE_3PI Changes the ULPI interface to 3-pin Serial.RW0
N
The PHY must automatically clear this field when serial mode is exited.
0b: FS/LS packets are sent using parallel interface
1b: FS/LS packets are sent using 4-pin serial interface
0FSLSSERIALMODE_6PI Changes the ULPI interface to 6-pin Serial.RW0
N
The PHY must automatically clear this field when serial mode is exited.
0b: FS/LS packets are sent using parallel interface
1b: FS/LS packets are sent using 6-pin serial interface
7USEEXTERNALVBUSINDICA Tells the PHY to use an external VBUS over-current indicator.RW0
TOR
0b: Use the internal OTG comparator (VA_VBUS_VLD) or internal
VBUS valid indicator (default)
1b: Use external VBUS valid indicator signal.
6DRVVBUSEXTERNALSelects between the internal and the external 5 V VBUS supply.RW0
0b: Pin17 (CPEN) is disabled (output GND level). TUSB1210 does
not support internal VBUS supply.
1b: Pin17 (CPEN) is set to ‘1’ (output VDD33 voltage level) if
DRVVBUS bit is ‘1’, else Pin17 (CPEN) is disabled (output GND
level) if DRVVBUS bit is ‘0’
5DRVVBUSVBUS output control bitRW0
0b : do not drive VBUS
1b : drive 5V on VBUS
Note: Both DRVVBUS and DRVVBUSEXTERNAL bits must be set
to 1 in order to to set Pin17 (CPEN). CPEN pin can be used to
enable an external VBUS supply
4CHRGVBUSCharge VBUS through a resistor. Used for VBUS pulsing SRP. TheRW0
3DISCHRGVBUSDischarge VBUS through a resistor. If the Link sets this bit to 1, itRW0
2DMPULLDOWNEnables the 15k Ohm pull-down resistor on D-.RW1
1DPPULLDOWNEnables the 15k Ohm pull-down resistor on D+.RW1
0IDPULLUPConnects a pull-up to the ID line and enables sampling of the signalRW0
Link must first check that VBUS has been discharged (see
DischrgVbus register bit), and that both D+ and D- data lines have
been low (SE0) for 2ms.
0b : do not charge VBUS
1b : charge VBUS
waits for an RX CMD indicating SessEnd has transitioned from 0 to
1, and then resets this bit to 0 to stop the discharge.
0b : do not discharge VBUS
1b : discharge VBUS
0b : Pull-down resistor not connected to D-.
1b : Pull-down resistor connected to D-.
0b : Pull-down resistor not connected to D+.
1b : Pull-down resistor connected to D+.
level.
0b : Disable sampling of ID line.
1b : Enable sampling of ID line.
7ReservedR0
6ReservedR0
5ReservedR0
4IDGNDCurrent value of UTMI+ IdGnd output.R0
This bit is not updated if IdPullup bit is reset to 0 and for 50 ms after IdPullup is set to
1.
3SESSENDCurrent value of UTMI+ SessEnd output.R0
2SESSVALIDCurrent value of UTMI+ SessValid output. SessValid is the same as UTMI+ AValid.R0
1VBUSVALIDCurrent value of UTMI+ VbusValid output.R0
0HOSTDISCONNECT Current value of UTMI+ Hostdisconnect output.R0
Applicable only in host mode.
Automatically reset to 0 when Low Power Mode is entered.
NOTE: Reset value is '0' when host is connected.
Reset value is '1' when host is disconnected.
DESCRIPTIONThese bits are set by the PHY when an unmasked change occurs on the
corresponding internal signal. The PHY will automatically clear all bits when
the Link reads this register, or when Low Power Mode is entered. The PHY
also clears this register when Serial Mode or Carkit Mode is entered regardless
of the value of ClockSuspendM.
The PHY follows the rules defined in Table 26 of the ULPI spec for setting any
latch register bit. It is important to note that if register read data is returned to
the Link in the same cycle that a USB Interrupt Latch bit is to be set, the
interrupt condition is given immediately in the register read data and the Latch
bit is not set.
Note that it is optional for the Link to read the USB Interrupt Latch register in
Synchronous Mode because the RX CMD byte already indicates the interrupt
source directly
TYPER
WRITE LATENCY
E
76543210
Reserved
Reserved
Reserved
IDGND_LATCH
SESSEND_LATCH
SESSVALID_LATCH
VBUSVALID_LATCH
HOSTDISCONNECT_LATCH
BITSFIELD NAMEDESCRIPTIONTYPERESET
7ReservedR0
6ReservedR0
5ReservedR0
4IDGND_LATCHSet to 1 by the PHY when an unmasked event occurs on IdGnd. ClearedR0
3SESSEND_LATCHSet to 1 by the PHY when an unmasked event occurs on SessEnd.R0
Cleared when this register is read.
2SESSVALID_LATCHSet to 1 by the PHY when an unmasked event occurs on SessValid.R0
Cleared when this register is read. SessValid is the same as UTMI+
AValid.
1VBUSVALID_LATCHSet to 1 by the PHY when an unmasked event occurs on VbusValid.R0
Cleared when this register is read.
0HOSTDISCONNECT_LATSet to 1 by the PHY when an unmasked event occurs onR0
CHHostdisconnect. Cleared when this register is read. Applicable only in
host mode.
NOTE: As this IT is enabled by default, the reset value depends on the
host status
Reset value is '0' when host is connected.
Reset value is '1' when host is disconnected.
SLLSE09D–NOVEMBER 2009–REVISED JANUARY 2011
9.1.22 DEBUG
ADDRESS OFFSET0x15
PHYSICAL ADDRESS0x15INSTANCE USB_SCUSB
DESCRIPTIONIndicates the current value of various signals useful for debugging.
TYPER
WRITE LATENCY
7SPAREReserved. The link must never write a 1b to this bit.RW0
6MNTR_VUSBIN_OK_EN When set to 1, it enables RX CMDs for high to low or low to highRW0
transitions on MNTR_VUSBIN_OK. This bit is provided for debugging
purposes.
5ID_FLOAT_ENWhen set to 1, it enables RX CMDs for high to low or low to highRW0
transitions on ID_FLOAT. This bit is provided for debugging purposes.
4ID_RES_ENWhen set to 1, it enables RX CMDs for high to low or low to highRW0
transitions on ID_RESA, ID_RESB and ID_RESC. This bit is provided for
debugging purposes.
3BVALID_FALLEnables RX CMDs for high to low transitions on BVALID. When BVALIDRW0
changes from high to low, the USB TRANS will send an RX CMD to the
link with the alt_int bit set to 1b.
This bit is optional and is not necessary for OTG devices. This bit is
provided for debugging purposes. Disabled by default.
2BVALID_RISEEnables RX CMDs for low to high transitions on BVALID. When BVALIDRW0
changes from low to high, the USB Trans will send an RX CMD to the link
with the alt_int bit set to 1b.
This bit is optional and is not necessary for OTG devices. This bit is
provided for debugging purposes. Disabled by default.
1SPAREReserved. The link must never write a 1b to this bit.RW0
0ABNORMALSTRESS_EWhen set to 1, it enables RX CMDs for low to high and high to lowRW0
Ntransitions on ABNORMALSTRESS. This bit is provided for debugging
0000 17.928 mA
0001 18.117 mA
0010 18.306 mA
0011 18.495 mA
0100 18.683 mA
0101 18.872 mA
0110 19.061 mA
0111 19.249 mA
1000 19.438 mA
1001 19.627 mA
1010 19.816 mA
1011 20.004 mA
1100 20.193 mA
1101 20.382 mA
1110 20.570 mA
1111 20.759 mA
IHSTX[0] is also the AC BOOST enable
IHSTX[0] = 0 à AC BOOST is disabled
IHSTX[0] = 1 à AC BOOST is enabled
ADDRESS OFFSET0x83
PHYSICAL ADDRESS0x83INSTANCEUSB_SCUSB
DESCRIPTIONIndicates the current value of the interrupt source signal.
TYPER
WRITE LATEN CY
76543210
Reserved
ID_RESB_STS
ID_RESC_STS
ID_FLOAT_STS
MNTR_VUSBIN_OK_STS
ABNORMALSTRESS_STS
BITSFIELD NAMEDESCRIPTIONTYPERESET
7ReservedR0
6MNTR_VUSBIN_OK_STSCurrent value of MNTR_VUSBIN_OK outputR0
5ABNORMALSTRESS_STSCurrent value of ABNORMALSTRESS outputR0
4ID_FLOAT_STSCurrent value of ID_FLOAT outputR0
3ID_RESC_STSCurrent value of ID_RESC outputR0
2ID_RESB_STSCurrent value of ID_RESB outputR0
1ID_RESA_STSCurrent value of ID_RESA outputR0
0BVALID_STSCurrent value of VB_SESS_VLD outputR0
BVALID_STS
ID_RESA_STS
9.1.33 VENDOR_SPECIFIC1_LATCH
ADDRESS OFFSET0x84
PHYSICAL ADDRESS0x84INSTANCEUSB_SCUSB
DESCRIPTIONThese bits are set by the PHY when an unmasked change occurs on the
corresponding internal signal. The PHY will automatically clear all bits when
the Link reads this register, or when Low Power Mode is entered. The PHY
also clears this register when Serial mode is entered regardless of the value of
ClockSuspendM.
The PHY follows the rules defined in Table 26 of the ULPI spec for setting any
latch register bit.
10.1 Host or OTG, ULPI Input Clock Mode Application
Figure 10-1 shows a suggested application diagram for TUSB1210 in the case of ULPI input-clock mode
(60 MHz ULPI clock is provided by link processor), in Host or OTG application. Note this is just one
example, it is of course possible to operate as HOST or OTG while also in ULPI output-clock mode.
A.Pin 11 (CS) : can be tied high to VIOif CS_OUT pin unavailable; Pin 14 (CFG) : tie-high is Don’t Care since ULPI
clock is used in input mode
B.Pin 1 (REFCLK) : must be tied low
C. Ext 3 V supply supported
D. Pin 27 (RESETB) can be tied to V
E.Pins labeled N/C (no-connect) are truly no-connect, and can be tied or left floating.
Figure 10-2 shows a suggested application diagram for TUSB1210 in the case of ULPI output clock mode
(60 MHz ULPI clock is provided by TUSB1210, while link processor or another external circuit provides
REFCLK), in Device mode application. Note this is just one example, it is of course possible to operate as
Device while also in ULPI input-clock mode. Refer also to Figure 10-1.
A.Pin 11 (CS) : can be tied high to VIOif CS_OUT pin unavailable; Pin 14 (CFG) : Tied to V
mode here, tie to GND for 19.2MHz mode.
B.Pin 1 (REFCLK) : connect to external 3.3V square-wave reference clock
C. Ext 3 V supply supported
D. Pin 27 (RESETB) can be tied to V
E.Pins labeled N/C (no-connect) are truly no-connect, and can be tied or left floating.
PMarking used to note prototype (X), preproduction (P), or
qualified/production device (Blank)(1)
AMask set version descriptor (initial silicon = BLANK, first
silicon revision = A, second silicon revision = B,...)(2)
YMYear month
LLLLSLot code
$Fab Planning Code
SLLSE09D–NOVEMBER 2009–REVISED JANUARY 2011
12.2 Package Thermal Resistance Characteristics
Table 12-2 provides the thermal resistance characteristics for the recommended package type RHB
(S-PQFP-N32) used for the TUSB1210 device. Refer to the application report IC Package ThermalMetrics, TI literature number SPRA953, further details concerning parameter definitions and usage.
(1) Top is surface of the package facing away from the PCB.
(2) Refer to measurement method in Chapter 2 of IC Package Thermal Metrics, TI literature number SPRA953.
(3) Bottom surface is the surface of the package facing towards the PCB.
Junction-to-top of package (not a true thermal0.5°C/WEIA/JESD 51-2
resistance)
Junction-to-board (not a true thermal resistance)10.5°C/WEIA/JESD 51-6
(1)
(3)
Submit Documentation Feedback
Product Folder Link(s): TUSB1210
37.3°C/WNo current JEDEC specification
3.6°C/WNo current JEDEC specification
(2)
(2)
PACKAGE OPTION ADDENDUM
www.ti.com
12-Jan-2011
PACKAGING INFORMATION
Orderable Device
TUSB1210BRHBPREVIEWQFNRHB321TBDCall TICall TISamples Not Available
TUSB1210BRHBRPREVIEWQFNRHB321TBDCall TICall TISamples Not Available
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Status
(1)
Package Type Package
Drawing
PinsPackage Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional
restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not
responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in
such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
ProductsApplications
Audiowww.ti.com/audioCommunications and Telecom www.ti.com/communications
Amplifiersamplifier.ti.comComputers and Peripheralswww.ti.com/computers
Data Convertersdataconverter.ti.comConsumer Electronicswww.ti.com/consumer-apps
DLP® Productswww.dlp.comEnergy and Lightingwww.ti.com/energy
DSPdsp.ti.comIndustrialwww.ti.com/industrial
Clocks and Timerswww.ti.com/clocksMedicalwww.ti.com/medical
Interfaceinterface.ti.comSecuritywww.ti.com/security
Logiclogic.ti.comSpace, Avionics and Defense www.ti.com/space-avionics-defense
Power Mgmtpower.ti.comTransportation andwww.ti.com/automotive
Microcontrollersmicrocontroller.ti.comVideo and Imagingwww.ti.com/video
RFIDwww.ti-rfid.comWirelesswww.ti.com/wireless-apps
RF/IF and ZigBee® Solutionswww.ti.com/lprf