Texas instruments TUSB1210 Data Manual

TUSB1210

Standalone USB Transceiver Chip Silicon

Data Manual

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Literature Number: SLLSE09D

November 2009–Revised January 2011

TUSB1210

SLLSE09D–NOVEMBER 2009–REVISED JANUARY 2011

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Contents

1 Features ............................................................................................................................. 7

2 Description ......................................................................................................................... 8

2.1 Terminal Description ........................................................................................................ 8

2.2 TUSB1210 Block Diagram ............................................................................................... 10

3 Electrical Characteristics .................................................................................................... 11

3.1 Absolute Maximum Ratings .............................................................................................. 11

3.2 Recommended Operating Conditions .................................................................................. 11

3.3 ESD Electrical Parameters ............................................................................................... 11

4 Clock System .................................................................................................................... 12

4.1 USB PLL Reference Clock ............................................................................................... 12

4.2 ULPI Input Clock Configuration .......................................................................................... 12

4.3 ULPI Output Clock Configuration ........................................................................................ 12

4.4 Clock 32 kHz ............................................................................................................... 13

4.5 Reset ........................................................................................................................ 13

5 Power Module ................................................................................................................... 14

5.1 Power Providers ........................................................................................................... 14

5.1.1 V

5.1.2 V

5.1.3 V

5.2 Power Consumption ....................................................................................................... 15

5.3 Power Management ....................................................................................................... 16

5.3.1 Power On Sequence ........................................................................................... 16

5.3.2 Timers and Debounce ......................................................................................... 17

6 USB Connectivity .............................................................................................................. 18

6.1 Timing Parameter Definitions ............................................................................................ 18

6.2 Interface Target Frequencies ............................................................................................ 18

6.3 USB Transceiver ........................................................................................................... 18

6.3.1 TUSB1210 Modes vs ULPI Pin Status ...................................................................... 19

6.3.2 ULPI Interface Timing .......................................................................................... 20

6.3.3 PHY Electrical Characteristics ................................................................................ 20

6.3.4 OTG Electrical Characteristics ................................................................................ 24

7 I/O Electrical Characteristics ............................................................................................... 26

7.1 Analog I/O Electrical Characteristics .................................................................................... 26

7.2 Digital I/O Electrical Characteristics ..................................................................................... 26

7.3 Electrical Characteristics: Digital IO Pins (Non-ULPI) ................................................................ 26

8 External Components ........................................................................................................ 27

9 Register Map ..................................................................................................................... 28

9.1 TUSB1210 Product ........................................................................................................ 28

9.1.1 VENDOR_ID_LO ............................................................................................... 29

Regulator ................................................................................................. 14

DD33

Supply ..................................................................................................... 14

DD18

Regulator ................................................................................................. 14

DD15

5.3.1.1 Timing Diagram .................................................................................... 16

6.3.3.1 LS/FS Single-Ended Receivers .................................................................. 20

6.3.3.2 LS/FS Differential Receiver ....................................................................... 21

6.3.3.3 LS/FS Transmitter .................................................................................. 21

6.3.3.4 HS Differential Receiver ........................................................................... 22

6.3.3.5 HS Differential Transmitter ........................................................................ 22

6.3.3.6 UART Transceiver ................................................................................. 23

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9.1.2 VENDOR_ID_HI ................................................................................................ 29

9.1.3 PRODUCT_ID_LO ............................................................................................. 29

9.1.4 PRODUCT_ID_HI .............................................................................................. 30

9.1.5 FUNC_CTRL .................................................................................................... 30

9.1.6 FUNC_CTRL_SET ............................................................................................. 31

9.1.7 FUNC_CTRL_CLR ............................................................................................. 31

9.1.8 IFC_CTRL ....................................................................................................... 32

9.1.9 IFC_CTRL_SET ................................................................................................ 33

9.1.10 IFC_CTRL_CLR ................................................................................................ 34

9.1.11 OTG_CTRL ...................................................................................................... 34

9.1.12 OTG_CTRL_SET ............................................................................................... 36

9.1.13 OTG_CTRL_CLR ............................................................................................... 36

9.1.14 USB_INT_EN_RISE ............................................................................................ 37

9.1.15 USB_INT_EN_RISE_SET ..................................................................................... 38

9.1.16 USB_INT_EN_RISE_CLR ..................................................................................... 38

9.1.17 USB_INT_EN_FALL ........................................................................................... 39

9.1.18 USB_INT_EN_FALL_SET ..................................................................................... 40

9.1.19 USB_INT_EN_FALL_CLR ..................................................................................... 40

9.1.20 USB_INT_STS .................................................................................................. 41

9.1.21 USB_INT_LATCH .............................................................................................. 42

9.1.22 DEBUG .......................................................................................................... 43

9.1.23 SCRATCH_REG ................................................................................................ 43

9.1.24 SCRATCH_REG_SET ......................................................................................... 44

9.1.25 SCRATCH_REG_CLR ......................................................................................... 44

9.1.26 VENDOR_SPECIFIC1 ......................................................................................... 45

9.1.27 VENDOR_SPECIFIC1_SET .................................................................................. 45

9.1.28 VENDOR_SPECIFIC1_CLR .................................................................................. 46

9.1.29 VENDOR_SPECIFIC2 ......................................................................................... 47

9.1.30 VENDOR_SPECIFIC2_SET .................................................................................. 48

9.1.31 VENDOR_SPECIFIC2_CLR .................................................................................. 48

9.1.32 VENDOR_SPECIFIC1_STS .................................................................................. 49

9.1.33 VENDOR_SPECIFIC1_LATCH ............................................................................... 49

9.1.34 VENDOR_SPECIFIC3 ......................................................................................... 50

9.1.35 VENDOR_SPECIFIC3_SET .................................................................................. 51

9.1.36 VENDOR_SPECIFIC3_CLR .................................................................................. 51

SLLSE09D–NOVEMBER 2009–REVISED JANUARY 2011

10 Application Information ...................................................................................................... 53

10.1 Host or OTG, ULPI Input Clock Mode Application .................................................................... 53

10.2 Device, ULPI Output Clock Mode Application ......................................................................... 53

11 Glossary ........................................................................................................................... 55

12 TUSB1210 Package ............................................................................................................ 57

12.1 TUSB1210 Standard Package Symbolization ......................................................................... 57

12.2 Package Thermal Resistance Characteristics ......................................................................... 57

TUSB1210

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List of Figures

5-1 TUSB1210 Power-Up Timing (ULPI Clock Input Mode) .................................................................... 16

6-1 USB UART Data Flow ........................................................................................................... 23

10-1 Host or OTG, ULPI Input Clock Mode Application Diagram................................................................ 53

10-2 Device, ULPI Output Clock Mode Application Diagram..................................................................... 54

12-1 Printed Device Reference....................................................................................................... 57

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List of Tables

2-1 Terminal Functions ................................................................................................................ 9

4-1 Electrical Characteristics: Clock Input ........................................................................................ 12

4-2 Electrical Characteristics: REFCLK ........................................................................................... 12

4-3 Performances..................................................................................................................... 13

5-1 Summary of TUSB1210 Power Providers..................................................................................... 14

5-2 V 5-3 V

5-4 Power Consumption ............................................................................................................. 15

6-1 Timing Parameter Definitions................................................................................................... 18

6-2 TUSB1210 Interface Target Frequencies..................................................................................... 18

6-3 TUSB1210 Modes vs ULPI Pin Status:ULPI Synchronous Mode Power-Up

6-4 TUSB1210 Modes vs ULPI Pin Status: USB Suspend Mode ............................................................. 19

6-5 TUSB1210 Modes vs ULPI Pin Status: ULPI 6-Pin Serial Mode and UART Mode ..................................... 20

6-6 ULPI Interface Timing............................................................................................................ 20

6-7 LS/FS Single-Ended Receivers ................................................................................................ 21

6-8 LS/FS Differential Receiver ..................................................................................................... 21

6-9 LS Transmitter .................................................................................................................... 21

6-10 FS Transmitter.................................................................................................................... 22

6-11 HS Differential Receiver......................................................................................................... 22

6-12 HS Transmitter.................................................................................................................... 23

6-13 USB UART Interface Timing Parameters ..................................................................................... 23

6-14 CEA-2011/UART Transceiver .................................................................................................. 23

6-15 Pullup/Pulldown Resistors....................................................................................................... 24

6-16 OTG V

6-17 OTG ID Electrical................................................................................................................. 25

7-1 Electrical Characteristics: Analog Output Pins .............................................................................. 26

8-1 TUSB1210 External Components.............................................................................................. 27

8-2 TUSB1210 V

9-1 USB Register Summary ......................................................................................................... 28

12-1 TUSB1210 Nomenclature Description......................................................................................... 57

12-2 TUSB1210 Thermal Resistance Characteristics............................................................................. 57

Internal LDO Regulator Characteristics ................................................................................ 14

DD33

Internal LDO Regulator Characteristics ................................................................................ 15

DD15

...................................................................................................................................... 19

Electrical.............................................................................................................. 24

BUS

Capacitors..................................................................................................... 27

BUS

TUSB1210

SLLSE09D–NOVEMBER 2009–REVISED JANUARY 2011

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TUSB1210

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SLLSE09D–NOVEMBER 2009–REVISED JANUARY 2011

Standalone USB Transceiver Chip Silicon

Check for Samples: TUSB1210

1 Features

• USB2.0 PHY Transceiver Chip, Designed to • Complete HS-USB Physical Front-End: Interface With a USB Controller via a ULPI Interface, Fully Compliant With:

– Universal Serial Bus Specification Rev. 2.0 – On-The-Go Supplement to the USB 2.0 Supporting 2 Clock Frequencies 19.2 MHz/26

Specification Rev. 1.3 MHz

– UTMI+ Low Pin Interface (ULPI) Specification – Integrated 45 Ω ±10% High-Speed

Rev. 1.1 Termination Resistors, 1.5 kΩ Full-Speed

– ULPI 12-pin SDR Interface

• DP/DM Line External Component Compensation (TI Patent Pending)

• Interfaces to Host, Peripheral and OTG Device Cores; Optimized for Portable Devices or System ASICs with Built-in USB OTG Device Core

• Complete USB OTG Physical Front-End that Supports Host Negotiation Protocol (HNP) and Session Request Protocol (SRP) – Non-Return-to-Zero Inverted (NRZI)

• V

Overvoltage Protection Circuitry Protects

BUS

Pin in Range –2 V to 20 V – Supports Bus Reset, Suspend, Resume and

BUS

• Internal 5 V Short-Circuit Protection of DP, DM, and ID Pins for Cable Shorting to V

Pin – HS USB DP/DM Impedance Programmability

BUS

• ULPI Interface: – I/O Interface (1.8V) Optimized for

Non-Terminated 50 Ω Line Impedance – Control of External V

– ULPI CLOCK Pin (60 MHz) Supports Both

Input and Output Clock Configurations – V

– Fully Programmable ULPI-Compliant – Both Session Request Protocol (SRP)

• Full Industrial Grade Operating Temperature Range from –40°C to 85°C – Integrated V

• Available in a 32-Pin Quad Flat No Lead [QFN (RHB)] Package • Internal Power-On Reset (POR) Circuit

• Can Be Interfaced to Peripheral, Host or OTG • Flexible System Integration and Very Low Controller Devices via ULPI. Suited to Portable Current Consumption, Optimized for Portable Devices or System ASICs with Built-In Devices Controller Core.

– Supports High Speed (480 Mbit/s), Full

Speed (12 Mbit/s) and Low Speed (1.5 Mbit/s)

– Integrated Phase-Locked Loop (PLL)

Device Pull-up Resistor, 15 kΩ Host Termination Resistors

– Integrated Transmit and Receive Paths for

Parallel-to-Serial and Serial-to-Parallel Data Conversion

– USB Data Recovery to Allow Recovery of

USB Data up to ±500 ppm Frequency Drift

– Bit-Stuffing Insertion During Transmit and

Removal During Receive

Encoding and Decoding

High-Speed Detection Handshake (Chirp)

for External Component Compensation

• OTG Ver1.3 : Switch or Charge

BUS

Pump

Fault Detection

BUS

Pulsing

Detectors and Cable

BUS

Detection (ID)

BUS

DDIO

DIR

DD18

STP

DD18

RESETB

CLOCK

N/C

REFCLK 1

N/C

NXT 2

DATA0 3 TUSB1210

RHB PACKAGE

(TOP VIEW)

BUS

DATA1 4 32-pin QFN

BAT

DATA2 5

DD33

DATA3 6

DATA4 7

GND

N/C 8

CPEN

DATA5

DATA6

DD15

DATA7

CFG

N/C

TUSB1210

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2 Description

The TUSB1210 is a USB2.0 transceiver chip, designed to interface with a USB controller via a ULPI interface. It supports all USB2.0 data rates (High-Speed 480Mbps, Full-Speed 12 Mbps and Low-Speed

1.5Mbps) in both Host and Peripheral modes. It additionally supports a UART mode and legacy ULPI serial modes.

TUSB1210 also supports the OTG (Ver1.3) optional addendum to the USB 2.0 Specification, including Host Negotiation Protocol (HNP) and Session Request Protocol (SRP).

TUSB1210 is optimized to be interfaced through a 12-pin SDR UTMI Low Pin Interface (ULPI), supporting both input clock and output clock modes, with 1.8 V interface supply voltage.

TUSB1210 integrates a 3.3 V LDO, which makes it flexible to work with either battery operated systems or pure 3.3 V supplied systems. Both the main supply and the 3.3 V power domain can be supplied through an external switched-mode converter for optimized power efficiency.

TUSB1210 includes a POR circuit to detect supply presence on V disabled or configured in low power mode for energy saving.

TUSB1210 is protected against accidental shorts to 5 V or ground on its exposed interface (DP/DM/ID). It is also protected against up to 20 V surges on V

TUSB1210 integrates a high-performance low-jitter 480 MHz PLL and supports two clock configurations. Depending on the required link configuration, TUSB1210 supports both ULPI input and output clock mode : input clock mode, in which case a square-wave 60 MHz clock is provided to TUSB1210 at the ULPI interface CLOCK pin; and output clock mode in which case TUSB1210 can accept a square-wave reference clock at REFCLK of either 19.2 MHz, 26 MHz. Frequency is indicated to TUSB1210 via the configuration pin CFG. This can be useful if a reference clock is already available in the system.

BUS

SLLSE09D–NOVEMBER 2009–REVISED JANUARY 2011

BAT

and V

pins. TUSB1210 can be

DDIO

2.1 Terminal Description

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TUSB1210

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Table 2-1. Terminal Functions

TERMINAL

NO. NAME

1 REFCLK A I 3.3 V clock of amplitude in the range of 3 V to 3.6 V when Pin 26 (CLOCK) is

2 NXT D O V 3 DATA0 D I/O V 4 DATA1 D I/O V 5 DATA2 D I/O V 6 DATA3 D I/O V 7 DATA4 D I/O V 8 N/C – – V 9 DATA5 D I/O V

10 DATA6 D I/O V 11 CS D I V 12 VDD15 A power 1.5-V internal LDO output. Connect to external filtering capacitor.

13 DATA7 D I/O V 14 CFG D I V 15 N/C – – – No connect

16 N/C – – – No connect 17 CPEN D O V 18 DP A I/O V 19 DM A I/O V 20 V 21 V 22 V

DD33

BAT

BUS

23 ID A I/O V 24 N/C – – – No connect 25 N/C – – – No connect

26 CLOCK D O V

27 RESETB D I V

28 V

DD18

29 STP D I V 30 V

DD18

31 DIR D O V 32 V

DDIO

A/D TYPE LEVEL DESCRIPTION

Reference clock input (square-wave only). Tie to GND when pin 26

DD33

(CLOCK) is required to be Input mode. Connect to square-wave reference required to be Output mode. See pin 14 (CFG) description for REFCLK

input frequency settings. ULPI NXT output signal ULPI DATA input/output signal 0 synchronized to CLOCK ULPI DATA input/output signal 1 synchronized to CLOCK ULPI DATA input/output signal 2 synchronized to CLOCK ULPI DATA input/output signal 3 synchronized to CLOCK ULPI DATA input/output signal 4 synchronized to CLOCK No connect ULPI DATA input/output signal 5 synchronized to CLOCK ULPI DATA input/output signal 6 synchronized to CLOCK Active-high chip select pin. When low the IC is in power down and ULPI

bus is tri-stated. When high normal operation. Tie to V

ULPI DATA input/output signal 7 synchronized to CLOCK REFCLK clock frequency configuration pin. Two frequencies are

supported: 19.2 MHz when 0, or 26 MHz when 1.

CMOS active-high digital output control of external 5V VBUS supply DP pin of the USB connector DM pin of the USB connector

3.3-V internal LDO output. Connect to external filtering capacitor. Input supply voltage or battery source

BAT

BUS

pin of the USB connector

BUS

Identification (ID) pin of the USB connector

A power V A power V A power V

DDIO DDIO DDIO DDIO DDIO DDIO DDIO DDIO DDIO

DDIO

DD33 DD33 DD33 DD33

DD33

ULPI 60 MHz clock on which ULPI data is synchronized. Two modes are possible:

DDIO

Input Mode: CLOCK defaults as an input. Output Mode: When an input clock is detected on REFCLK pin (after 4

rising edges) then CLOCK will change to an output. When low, all digital logic (except 32 kHz logic required for power up

sequencing) including registers are reset to their default values, and ULPI bus is tri-stated. When high, normal USB operation.

External 1.8-V supply input. Connect to external filtering capacitor. ULPI STP input signal External 1.8-V supply input. Connect to external filtering capacitor. ULPI DIR output signal External 1.8V supply input for digital I/Os. Connect to external filtering

capacitor.

A power V

A I V

DDIO

DD18 DDIO DD18 DDIO

DDIO

if unused.

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USB-IP

OTG

1V5

3V3

1V8

POR

VBAT

PLL

PHY ANA

PHY

DIG

ULPI

REGS

32K

BGAP

& REF

POR

DIG

TEST

OTG

PWR_ FSM

POR

VIO

CTRL

RST_DIG

VDDIO (32)

VBAT (21)

(24)

VDD15 (12)

VDD18 (28) VDD33 (20)

DP (18)

DM (19)

ID (23)

(22)

VBUS

( 1) REFCLK

(25)

(17) CPEN

(3:7,9:10,13)

DATA (7:0)

(2 ) NXT

(31) DIR

(29) STP

(26) CL OCK

(16)

(15)

VDD18 (30)

PKG Substrate

(Ground )

(14) CFG

(11) CS

(8)

(27) RESETB

TUSB1210

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2.2 TUSB1210 Block Diagram

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3 Electrical Characteristics

3.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

PARAMETER CONDITIONS MIN MAX UNIT

Main battery supply voltage

Voltage on any input

input –2 20 V

BUS

ID, DP, DM inputs Stress condition guaranteed 24h –0.3 5.25 V V T T

DDIO stg A

IO supply voltage Continuous 1.98 V

Storage temperature range –55 125 °C

Ambient temperature range –40 85 °C

Ambient temperature range °C

Ambient temperature for parametric With max 125°C as junction temperature

compliance

DP, DM, ID high voltage short circuit supply, in any mode of TUSB1210 operation, 5.25 V

DP, DM, ID low voltage short circuit any mode of TUSB1210 operation, 0 V

(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The product will have negligible reliability impact if voltage spikes of 5.5 V occur for a total (cumulative over lifetime) duration of 5

milliseconds.

(3) Except V

BAT

input, V

, ID, DP, and DM pads

BUS

(2)

(3)

Where supply represents the voltage applied to the power supply pin associated with the –0.3 1 × VCC+0.3 V input

Absolute maximum rating –40 150 For parametric compliance –40 125

DP, DM or ID pins short circuited to V continuously for 24 hours

DP, DM or ID pins short circuited to GND in continuously for 24 hours

(1)

0 5 V

–40 85 °C

BUS

3.2 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT

BAT

CERT

DDIO

Battery supply voltage 2.7 3.6 4.8 V

Battery supply voltage for USB 2.0 compliancy

(USB 2.0 certification)

When V When V

is supplied internally 3.15 V

DD33

is shorted to V

DD33

externally 3.05

BAT

Digital IO pin supply 1.71 1.98 V

Ambient temperature range –40 85 °C

3.3 ESD Electrical Parameters

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

CDM Charged-Device Model stress voltage All pads 500 V HBM Human-Body Model stress voltage All pads 2000 V

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4 Clock System

4.1 USB PLL Reference Clock

The USB PLL block generates the clocks used to synchronize :

• the ULPI interface (60 MHz clock)

• the USB interface (depending on the USB data rate, 480 Mbps, 12 Mbps or 1.5 Mbps) TUSB1210 requires an external reference clock which is used as an input to the 480 MHz USB PLL block.

Depending on the clock configuration, this reference clock can be provided either at REFCLK pin or at CLOCK pin. By default CLK pin is configured as an input.

Two clock configurations are possible:

• Input clock configuration (see Section 4.2)

• Output clock configuration (see Section 4.3)

4.2 ULPI Input Clock Configuration

In this mode REFCLK must be externally tied to GND. CLOCK remains configured as an input. When the ULPI interface is used in “input clock configuration”, i.e., the 60 MHz ULPI clock is provided to

TUSB1210 on Clock pin, then this is used as the reference clock for the 480 MHz USB PLL block.

Table 4-1. Electrical Characteristics: Clock Input

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PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Clock input duty cycle 40 60 % f

CLK

Clock nominal frequency 60 MHz

Clock input rise/fall time In % of clock period t

Clock input frequency accuracy 250 ppm

Clock input integrated jitter 600 ps rms

4.3 ULPI Output Clock Configuration

In this mode a reference clock must be externally provided on REFCLK pin When an input clock is detected on REFCLK pin then CLK will automatically change to an output, i.e., 60 MHz ULPI clock is output by TUSB1210 on CLK pin.

Two reference clock input frequencies are supported. REFCLK input frequency is communicated to TUSB1210 via a configuration pin, CFG, see f TUSB1210 supports square-wave reference clock input only. Reference clock input must be square-wave of amplitude in the range 3.0 V to 3.6 V.

Table 4-2. Electrical Characteristics: REFCLK

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

REFCLK input duty cycle 40 60 %

REFCLK

REFCLK nominal frequency MHz

REFCLK input rise/fall time 20 %

REFCLK input frequency accuracy 250 ppm

REFCLK input integrated jitter 600 ps rms

When CFG pin is tied to GND 19.2 When CFG pin is tied to V In % of clock period t

1/f

REFCLK

( = 1/f

CLK

REFCLK

DDIO

)

REFCLK

) 10 %

CLK

in Table 8-1 for frequency correspondence.

( =

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4.4 Clock 32 kHz

An internal clock generator running at 32 kHz has been implemented to provide a low-speed, low-power clock to the system

Table 4-3. Performances

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Output duty cycle Input duty cycle 40–60% 48 50 52 % Output frequency 23 32 38 kHz

4.5 Reset

All logic is reset if CS = 0 or V All logic (except 32 kHz logic) is reset if V PHY logic is reset when any supplies are not present (V TUSB1210 may be reset manually by toggling the RESETB pin to GND for at lease 200 ns. If manual reset via RESETB is not required then RESETB pin may be tied to V

are not present.

BAT

is not present.

DDIO

, V

DD15

, V

DD18

, V

) or if RESETB pin is low.

DD33

permanently.

DDIO

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5 Power Module

This chapter describes the electrical characteristics of the voltage regulators and timing characteristics of the supplies digitally controlled within the TUSB1210.

5.1 Power Providers

Table 5-1. Summary of TUSB1210 Power Providers

NAME USAGE TYPE

5.1.1 V

The V subchip inside TUSB1210. Table 5-2 describes the regulator characteristics.

(1) V

Regulator

DD33

DD15

DD18

DD33

may be supplied externally, or by shorting the V

DD33

range [3.2 V : 3.6 V]. Note that the V irrespective of whether V externally in the application, the electrical specs for this LDO are provided below.

internal LDO regulator powers the USB PHY, charger detection, and OTG functions of the USB

Internal LDO 1.5 50

External LDO 1.8 30

Internal LDO 3.1 15

DD33

TYPICAL MAXIMUM

VOLTAGE (V) CURRENT (mA)

pin to V

LDO will always power-on when the chip is enabled,

DD33

is supplied externally or not. In the case the V

DD33

pin provided V

BAT

(1)

BAT

pin is not supplied

DD33

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min is in

V Since the USB2.0 standard requires data lines to be biased with pullups biased from a supply greater than

3 V, and since V TUSB1210 will not meet USB 2.0 Standard if operated from a battery whose voltage is lower than 3.3 V.

INVDD33

VDD33

5.1.2 V

The V

regulator takes its power from V

DD33

regulator has an inherent voltage drop from its input, V

DD33

Table 5-2. V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Input voltage V

Output voltage ON mode, V

Rated output current V

Supply

DD18

supply is powered externally at the V

DD18

DD33

USB V

BAT

USB mA

BAT

, to its regulated output,

BAT

Internal LDO Regulator Characteristics

typ + 0.2 3.6 4.5 V

VDD33

VUSB3V3_VSEL = ‘000 2.4 2.5 2.6 VUSB3V3_VSEL = ‘001 2.65 2.75 2.85 VUSB3V3_VSEL = ‘010 2.9 3.0 3.1 VUSB3V3_VSEL = ‘011 (default) 3.0 3.1 3.2 VUSB3V3_VSEL = ‘100 3.1 3.2 3.3 VUSB3V3_VSEL = ‘101 3.2 3.3 3.4 VUSB3V3_VSEL = ‘110 3.3 3.4 3.5 VUSB3V3_VSEL = ‘111 3.4 3.5 3.6 Active mode 15 Suspend/reset mode 1

pin. See Table 8-1 for external components.

DD18

5.1.3 V

The V

Regulator

DD15

internal LDO regulator powers the USB subchip inside TUSB1210. Table 5-3 describes the

regulator characteristics.

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Table 5-3. V

Internal LDO Regulator Characteristics

DD15

SLLSE09D–NOVEMBER 2009–REVISED JANUARY 2011

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

IN VDD15

VDD15

Input voltage On mode, V Output voltage V

INVDD15 min

IN VDD15

– V

INVDD15 max

= V

BAT

2.7 3.6 4.5 V

1.45 1.56 1.65 V

Rated output current On mode 30 mA

5.2 Power Consumption

Table 5-4 describes the power consumption depending on the use cases.

NOTE

The typical power consumption is obtained in the nominal operating conditions and with the TUSB1210 standalone.

Table 5-4. Power Consumption

MODE CONDITIONS SUPPLY UNIT

VBAT

= 3.6 V, V

OFF Mode µA

Suspend Mode µA

HS USB Operation V

(Synchronous Mode) = 1.8 V, active USB transfer

FS USB Operation V

(Synchronous Mode) USB transfer

Reset Mode µA

BAT

= 1.8 V, CS = 0 V

= 5 V, V

BUS

1.8 V, No clock

= 3.6 V, V

BAT

= 3.6 V, V

BAT

RESETB = 0 V, V

= 3.6 V, V

DDIO

= 1.8 V, V

DDIO

= 3.6 V, V

BAT

= 1.8 V, V

DDIO

= 1.8 V, active

DDIO

= 5 V, V

BUS

= 1.8 V, No clock

DDIO

DD18

BAT

VDDIO

VDD18

TOTAL

VBAT

VDDIO

VDD18

TOTAL

VBAT

VDDIO

VDD18

TOTAL

VBAT

VDDIO

VDD18

TOTAL

VBAT

VDDIO

VDD18

TOTAL

TYPICAL

CONSUMPTION

8 3 5

204

3 3

210

24.6

1.89

21.5 48

25.8

1.81

4.06

31.7

237

3 3

243

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VBAT , VDD33

VDDIO, VDD18

IORST

ICACT

VDD15

DIGPOR

CK32K

BGOK

CK32KOK

MNTR_(VDD18,VIO)_OK

MNTR_VDD33_OK

RESETN_PWR

TDELRSTPWR (61us)

TDELMNTRVIOEN (91.5us)

TDELVDD33EN (91.5us)

TMNTR (183.1us)

(input 60M) CLOCK

PLL 480M LOCKED

TPLL (300us)

DIR

TBGAP (2ms)

TPWONVDD15 (100us)

RESETB

TDELRESETB (244.1us)

TVBBDET (10us)

TCK32K_PWON (125us)

TMNTR (183.1us)

TDEL_CS_SUPPLYOK (2.84ms)

TDEL_RST_DIR (0.54ms)

NOPWR

OFF

HWRST

COLDRST

ACTIVE

TUSB1210

SLLSE09D–NOVEMBER 2009–REVISED JANUARY 2011

5.3 Power Management

5.3.1 Power On Sequence

5.3.1.1 Timing Diagram

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Figure 5-1. TUSB1210 Power-Up Timing (ULPI Clock Input Mode)

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5.3.2 Timers and Debounce

PARAMETER COMMENTS MIN TYP MAX UNIT

DEL_CS_SUPPLYOK

DEL_RST_DIR

VBBDET

BGAP

PWONVDD15

PWONCK32K

DELRSTPWR

DELMNTRVIOEN

MNTR

DELVDD33EN

DELRESETB

PLL

Chip-select-to-supplies OK delay 2.84 4.10 ms RESETB to PHY PLL locked and DIR 0.54 0.647 ms

falling-edge delay V

detection delay 10 us

BAT

Bandgap power-on delay 2 ms V

power-on delay 100 us

DD15

32-KHz RC-OSC power-on delay 125 us Power control reset delay 61 us Monitor enable delay 91.5 us Supply monitoring debounce 183.1 us V

LDO enable delay 93.75 us

DD33

RESETB internal delay 244.1 us PLL lock time 300 us

SLLSE09D–NOVEMBER 2009–REVISED JANUARY 2011

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TUSB1210

SLLSE09D–NOVEMBER 2009–REVISED JANUARY 2011

6 USB Connectivity

6.1 Timing Parameter Definitions

The timing parameter symbols used in the timing requirement and switching characteristic tables are created in accordance with JEDEC Standard 100. To shorten the symbols, some pin names and other related terminologies have been abbreviated as shown in Table 6-1.

Table 6-1. Timing Parameter Definitions

SYMBOL PARAMETER

C Cycle time (period) D Delay time

Dis Disable time

En Enable time

H Hold time

Su Setup time

START Start bit

T Transition time V Valid time

W Pulse duration (width)

X Unknown, changing, or don't care level H High L Low V Valid

IV Invalid AE Active edge FE First edge

LE Last edge

Z High impedance

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LOWERCASE SUBSCRIPTS

6.2 Interface Target Frequencies

Table Table 6-2 assumes testing over the recommended operating conditions.

Table 6-2. TUSB1210 Interface Target Frequencies

IO INTERFACE DESIGNATION TARGET

INTERFACE FREQUENCY

USB Universal High speed 480 Mbits/s

serial bus

Full speed 12 Mbits/s Low speed 1.5 Mbits/s

1.5 V

6.3 USB Transceiver

The TUSB1210 device includes a universal serial bus (USB) on-the-go (OTG) transceiver that supports USB 480 Mb/s high-speed (HS), 12 Mb/s full-speed (FS), and USB 1.5 Mb/s low-speed (LS) through a 12-pin UTMI+ low pin interface (ULPI).

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