PC
USB
CLK
AC-to-DC
5V PS
AC-to-DC
19V PS
TSW4806
(Clock Gen)
TSW2110
ADS4249
(Dual ADC)
TSW1400
(Data Capt)
TSW2200
(Pwr dist)
User's Guide
SLAU438–March 2012
TSW2110EVM Evaluation Module (EVM)
This user’s guide describes the operation of the TSW2110 input signal generator evaluation module
(EVM). The 10-MHz EVM is used to verify the functionality of various TI analog-to-digital converters
(ADCs). The guide includes setup instructions for the hardware, expected results captured from a
TSW1400EVM and an ADS4249EVM. The TSW2110EVM product folder on the TI web site contains the
EVM schematic, bill of materials, and layout files.
1 Introduction
The TI TSW2110EVM (EVM) helps designers evaluate the functionality of their ADC devices. This product
eliminates the expense of using a signal generator to create an input signal.
The board is powered off a bench power supply or the 5-V output which is found on the TSW2200EVM. A
red and black banana jack to easy hook patch cable delivers the required voltage to the EVM. An external
clock generator is required to provide a sampling clock for the ADC board to capture correctly. For the
captures conducted in this document, a 245.76-MHz clocking signal from the TSW4806EVM was used.
The EVM has a default setup expecting an input voltage of 5 V. With this voltage applied, a temperaturecontrolled crystal oscillator (TCXO) generates a HCMOS waveform at 10 MHz. Using amplification,
attenuation and filtering, a 10-MHz signal is generated with low harmonic distortion output. The output
waveform is set to +10 dBm (2 Vpp), which is used as the input to an ADC board.
The TCXO is powered from the 3.3-V output of the low-dropout (LDO) regulator in its default mode. This
applied voltage generates a 10-MHz, HCMOS signal with an amplitude of 10.6 dBm.
The output waveform of the TCXO is attenuated by a 15dB pad prior to going into the input of the
amplifier. This amplifier requires an input signal with an amplitude of approximately –5 dBm. At this input
level, a gain of 20 dB is achieved without creating additional harmonic distortion. The amplifier output
waveform is +15 dBm and has significant harmonics. A crystal filter (part number, FTR-80307) is
necessary to eliminate these harmonics. A 1db pad is installed after the amplifier to maintain 50-Ω
termination and reduce the impact of impedance mismatches.
Figure 1. Block Diagram for Testing
SLAU438–March 2012 TSW2110EVM Evaluation Module (EVM)
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Evaluation with the TSW2110
On the 8-pole crystal filter, FTR-80307, matching is tuned for optimal performance. This matching is
crucial for proper filter behavior and does not result in low output power. This filter attenuates the
harmonics lower than –80 dBc resulting in a clean sine wave that is used as an input to the ADC board.
Depending on which ADC is evaluated, the resulting carrier amplitude should be approximately –1 dBFS.
For information on the filter, contact PDI at www.pdixtal.com.
2 Evaluation with the TSW2110
This chapter details the evaluation process and features of the EVM. An external supply voltage must be
connected to the voltage in and ground test points (TP1 and TP2, respectively). A blue LED turns on if the
proper voltage is supplied. An SMA to SMA cable must be connected from the output SMA connector to
the input channel of the unit under test.
The board accepts a supply voltage of 5 V (default) or 3.3 V. Different jumper configurations are
necessary for these two options. If the board is supplied with 5 V, the charge pump is bypassed and the
LDO 3.3-V regulator is implemented. If 3.3 V is supplied, the regulator is bypassed and the charge pump
is used. The necessary configurations for each method are seen in Table 1. The board is clearly marked
with these points so that the proper jumper configuration can be implemented. Improper jumpers will not
damage the parts on the board; however, the system will not create the desired waveform for accurate
testing.
Option JP1 JP2, JP3 JP4, JP5
5 V (default) Short 1-2 Opened Shorted
3.3 V Short 2-3 Shorted Opened
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Table 1. Jumper Configurations
3 Measurements
When the board is functioning properly, the output waveform measured on the SMA connector should
have 10 dBm of amplitude. The best way to get an accurate reading is when measured on a signal
analyzer with a 50-Ω load termination. The testing for this user’s guide was done on a spectrum analyzer.
On many signal analyzers, the EVM output signal overdrives the machine in their default settings. RF
attenuation must be set to account for this. The data taken in Figure 2 had the RF attenuation set to 25 dB
and set to 5 dB in Figure 3.
2
TSW2110EVM Evaluation Module (EVM) SLAU438–March 2012
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Measurements
Figure 2. Output Waveform At 10 MHz, Signal At 10.1 dBm
The output is filtered with a 10-MHz rejection filter to keep from distorting the analyzer. Figure 3 shows the
performance of the EVM at the second through fifth harmonics. The highest is the second harmonic at
74.2 dBm.
Figure 3. Waveform Harmonics At 91.4, 74.2, 99.82, and 103.59 dBm
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Measurements
3.1 Expected Values
Table 2 and Table 3 outline the expected values for certain test points on the board to monitor the
functionality of the TSW2110. Depending on the input voltage configuration on the board, some of the
expected values are different. The charge pump draws more current in the 3.3-V input configuration than
the LDO regulator does with the 5-V input.
3.2 Output Waveform
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Table 2. Expected Values With a 5-V Input
System Current 115 mA
Input Voltage 5 V
Amplifier Voltage 4.98 V
Table 3. Expected Values With a 3.3-V Input
System Current 190 mA
Input Voltage 3.3 V
Amplifier Voltage 5.01 V
Figure 4. Capture on TSW1400 of the ADS4249EVM, Input Signal Source Is TSW2110
The data captured meets datasheet-type performance for the ADS4249EVM.
4
TSW2110EVM Evaluation Module (EVM) SLAU438–March 2012
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Measurements
Figure 5. TSW2110EVM Board
SLAU438–March 2012 TSW2110EVM Evaluation Module (EVM)
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Copyright © 2012, Texas Instruments Incorporated
5
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