TEXAS INSTRUMENTS TSW1400 Technical data

User's Guide

SLWU079– February 2012

TSW140x High Speed Data Capture/Pattern Generator

Card

The Texas Instruments TSW1400 Evaluation Module (EVM) is a next generation of pattern generator and data capture card used to evaluate performances of a wide range of Texas Instruments (TI) high-speed analog-to-digital converters (ADC) and digital-to-analog converters (DAC). For an ADC, capturing the sampled data over an LVDS interface when using a high-quality, low-jitter clock, and a high-quality input frequency, the TSW1400 can be used to demonstrate data sheet performance specifications. Together with the accompanying Labview based Graphic User Interface (GUI), it is a complete system that captures and evaluates data samples from ADC EVM’s and generates and sends desired test patterns to DAC EVM’s

The TSW1405 is a low cost data capture card with limited capabilities as compared with the TSW1400. The TSW1405 supports pattern capture for most LVDS format TI ADC EVMs, but with a capture buffer limitation of 64K samples. The TSW1405 draws its power from the USB connection to the PC for easy setup and operation. The same TSW1400 Graphical User Interface supports the TSW1405 as well, making for a consistent feel across the different platforms.

The TSW1406 is a low cost pattern generator card with limited capabilities as compared with the TSW1400. The TSW1406 supports pattern generation for most LVDS format TI DAC EVMs, but with a pattern limitation of 64K samples. The TSW1406 draws its power from the USB connection to the PC for easy setup and operation. The same TSW1400 GUI supports the TSW1406 as well.

Table 1. TSW140x EVM Features

I/O Interface

LVDS CMOS JESD 16 Bit Memory Depth Data Capture Data Source

TSW1400 Yes Firmware Firmware 512M Yes Yes

TSW1405 Yes No No 64K Yes No TSW1406 Yes No No 64K No Yes

1 Functionality ................................................................................................................. 3

1.1 ADC EVM Data Capture .......................................................................................... 4

1.2 DAC EVM Pattern Generator ..................................................................................... 4

2 Hardware Configuration .................................................................................................... 4

2.1 Power Connections ................................................................................................ 5

2.2 Switches, Jumpers and Fuses ................................................................................... 5

2.3 LED's ................................................................................................................ 6

2.4 Connectors .......................................................................................................... 6

3 Software Start up ........................................................................................................... 7

3.1 Installation Instructions ............................................................................................ 7

3.2 USB Interface and Drivers ........................................................................................ 8

3.3 Device ini Files .................................................................................................... 10

4 User Interface .............................................................................................................. 10

4.1 Toolbar ............................................................................................................. 11

4.2 Status Windows ................................................................................................... 14

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Contents

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4.3 Mode Selection ................................................................................................... 15

4.4 Device Selection .................................................................................................. 15

4.5 Capture Button (ADC Mode only) .............................................................................. 16

4.6 Test Selection (ADC Mode only) ............................................................................... 16

4.7 DAC Display Panel (DAC Mode only) ......................................................................... 21

4.8 I/Q Multi-tone Generator ......................................................................................... 23

5 ADC Data Capture Software Operation ................................................................................ 23

5.1 Testing with an ADS5281 EVM ................................................................................. 23

6 TSW1400 Pattern Generator Operation ................................................................................ 27

6.1 Testing with DAC3152 EVM .................................................................................... 27

6.2 Loading DAC Firmware .......................................................................................... 27

6.3 Configuring TSW1400 for Pattern Generation ................................................................ 29

List of Figures

1 TSW1400EVM Block Diagram ............................................................................................ 3

2 TSW1400EVM Serial Number............................................................................................. 8

3 Firmware Does Not Match the Device Selected........................................................................ 8

4 TSW1400EVM GUI Top Level ............................................................................................ 9

5 Connecting GUI to EVM ................................................................................................... 9

6 Hardware Device Manager............................................................................................... 10

7 File Tab Options........................................................................................................... 11

8 Instrument Options ........................................................................................................ 11

9 Capture Option............................................................................................................. 12

10 Test Options................................................................................................................ 12

11 Notch Frequency Bin removal .......................................................................................... 13

12 Two Channel Display ..................................................................................................... 14

13 Status Window............................................................................................................. 15

14 Center Status Window.................................................................................................... 15

15 TSW1400 Modes.......................................................................................................... 15

16 ADC Device Selection Window.......................................................................................... 16

17 Single Tone FFT Display................................................................................................. 17

18 Data Display Options ..................................................................................................... 18

19 Channel Selection Window............................................................................................... 18

20 Data Windowing Options ................................................................................................. 18

21 ADC 2nd Input Frequency Box .......................................................................................... 20

22 DAC Display Mode........................................................................................................ 21

23 DAC Test Pattern Display................................................................................................ 22

24 TSW1400EVM interfacing to an ADS5281 EVM...................................................................... 24

25 ADC5281 Single Tone FFT Capture Results.......................................................................... 25

26 Devices Supported with Current Firmware Load...................................................................... 26

27 TSW1400 EVM Interfacing to a DAC EVM ............................................................................ 27

28 TSW1400EVM GUI DAC Mode Top Level............................................................................. 28

29 DAC Selection ............................................................................................................. 28

30 TSW1400 Output Data to DAC EVM ................................................................................... 29

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ADC EVM

DAC LVDS INTERFACE

1GB DDR RAM

ALTERA

STRATIX IV

(FIRMWARE)

USB

SERIAL

SPI

Interface

USB

PORT

Data and Clock

Signals

TSW1400 EVM

DAC EVM

Pattern and

Data Clock

ADC / DAC CMOS

INTERFACE

ADC LVDS INTERFACE

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1 Functionality

The TSW1400 has two direct interfaces to TI ADC EVM’s. One option captures data through a LVDS interface and the other uses a CMOS interface (currently not supported). Sampled data from the ADC is de-serialized and formatted by an Altera Stratix IV FPGA, then stored into an external onboard 1GB DDR memory card. The onboard memory enables the TSW1400 to store up to 512M 16 bit data samples. To acquire data on a host PC, the FPGA reads the data from memory and transmits it on Serial Peripheral Interface (SPI). An onboard high speed USB to SPI converter bridges the FPGA SPI interface to the host PC and GUI.

The TSW1400 has two direct interfaces to TI DAC EVM’s. In Pattern Generator Mode, the TSW1400 generates desired test patterns for DAC EVM’s under test. These patterns are sent from the host PC over the USB interface to the TSW1400. The FPGA stores the data received into the board DDR memory module. The data from the memory is then read by the FPGA and transmitted to a DAC EVM either across a DAC LVDS interface connector or a CMOS interface connector (currently not supported).

A block diagram of the TSW1400 EVM is shown in Figure 1.

Functionality

Figure 1. TSW1400EVM Block Diagram

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Hardware Configuration

1.1 ADC EVM Data Capture

Many TI high-speed ADCs have LVDS outputs for the digitized data. These ADCs are generally available on an EVM that connects directly to the TSW1400EVM. The common connector between the ADC EVM and the TSW1400EVM is a Samtec high-speed connector with differential pairs routed to adjacent pins and the pairs separated by a ground pin. A common pinout for the connector across a family of EVMs has been established. At present, the interface between the ADC EVM and the TSW1400EVM has defined connections for 35 pairs of LVDS data lines, two clock pairs, and eight general purpose CMOS I/O pins. The TSW1400 has a CMOS interface that is currently unsupported in this release.

The data format for the LVDS data bus can be in one of many formats, all supported by the TSW1400. For single-channel, high-speed ADCs, the data format is commonly a parallel dual-data rate with one output clock . Dual-data rate means that both the rising and falling edges of the clock register data into the TSW1400. For multichannel ADCs, the data is commonly presented in a serialized format, where individual bits of the output data are presented on an LVDS pair one bit at a time, at a higher data rate than the sample rate of the ADC.

Several firmware files are used by the FPGA on the TSW1400 to accommodate both parallel DDR formats an serial LVDS formats, although not at the same time. The GUI will load the FPGA with the appropriate firmware based on the ADC EVM under test selected by the user.

The parallel DDR FPGA program supports several types of data formats. One common format presents odd-numbered data bits on the bus on one clock edge and even-numbered data bits on the bus on the other clock edge. This format is commonly used for ADCs with sampling rates up to 250 MHz. For this bit-wise DDR format, the parallel data bus uses half as many LVDS pairs as there are bits in the sample. For example, a 16-bit ADC uses eight LVDS pairs for data plus an LVDS clock pair for bit-wise DDR. For higher sample rates up to 1 GHz, a sample-wise DDR format is often used. For sample-wise DDR, the data bus width has as many LVDS pairs as the bit resolution of the ADC. On one clock edge, a data sample from the ADC is registered; on the next clock edge, the next data sample from the ADC is registered.

The serial FPGA program also supports several data formats. For one-wire serial formats, the data is serialized onto a single LVDS pair at a rate that is 12 times the sample rate for an ADC with a 12-bit resolution. A one-wire serialization format also is used for 14-bit and 16-bit data at data rates 14 or 16 times the sample rate, respectively. For serial data formats, a DDR LVDS bit clock is used to strobe the serial data bits and to de-serialize the data. An additional clock pair operating at the sample rate of the ADC identifies the sample-word boundaries in the serial data. For multichannel ADCs, a single-bit clock and a single sample-rate clock (frame clock) is used for all of the LVDS data channels. The other common serial data format is two-wire serialization. Two-wire serialization is similar to one-wire serialization except that a data channel uses two LVDS pairs to carry the serialized data at a rate that is half of what it is for one-wire serialization.

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1.2 DAC EVM Pattern Generator

Some TI high-speed DAC’s have LVDS inputs for the digitized data. These DACs are generally available on an EVM that connects directly to the TSW1400EVM. The common connector between the DAC EVM and the TSW1400EVM is a Samtec high-speed connector with differential pairs routed to adjacent pins and the pairs separated by a ground pin. A common pinout for the connector across a family of EVMs has been established. At present, the interface between these DAC EVM’s and the TSW1400EVM has defined connections for 32 pairs of LVDS data lines, two data output clock pairs, four control pairs, two input clock pairs (sync, strobes, and so on), eight general purpose CMOS I/O pins (USB controlled) and 10 general purpose CMOS I/O pins (FPGA controlled). The TSW1400 has a CMOS interface that is currently unsupported. If the DAC EVM supports a CMOS single-ended format, then the TSW3100 system is intended to be used.

2 Hardware Configuration

In this section, the various portions of the TSW1400EVM hardware are described.

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2.1 Power Connections

The TSW1400EVM hardware is designed to operate from a single-supply voltage of 5 Vdc. The power input is controlled by the ON/OFF switch SW7. Make sure this switch is in the “OFF” position before inserting the power plug. Connect the 5 V output of the provided AC-to-DC power supply to J12 of the EVM and the other power supply cable to 110-120 VAC source.

2.1.1 Output Power Regulators

The TSW1400 provides two output power sources with these default settings:

• 3.3 V @ 3 A at J10 and the return at J9

• 1.8 V @ 6 A at J8 and the return to J9.

Both power supplies are derived from on-board switching power supplies and controlled by switch SW7. See the TI TPS54620 (SLVS949) and TPS54325 data sheet (SLVS932) for more information regarding the performance of these devices before deciding to use them to power up external EVM’s.

2.2 Switches, Jumpers and Fuses

2.2.1 Switches and Pushbuttons

Switch SW7 is the main power ON/OFF switch. Dipswitch SW1 has all switches routed to spare pins on the FPGA. Each switch trace has a pullup to 3.3V

and shorts this to ground when the switch is closed. Currently none of the switches are used. Five pushbutton switches are mounted on the TSW1400EVM. One pushbutton switch currently has a

defined function; one of the other switches is reserved for future use. The CPU_RESET (SW6) pushbutton causes the FPGA to reset the internal PLL logic. The CONF/ SPI (SW2) will reload the FPGA from a configuration prom (for future board revision).

Hardware Configuration

2.2.2 Jumpers

Jumpers JP5, JP6, and JP7 allow the option to break the connection on three GPIO signals that are routed between connector J3 and USB controller U3 through buffer U16. When the jumper shunts are removed and buffer U16 is disabled, the user can provided external signals to three signals going to an ADC EVM that is connected to J3 by using pin 1 of JP5, JP6, and JP7. Connecting pins 1 and 2 of Jumper SJP1 will disable U16. Connecting pins 1 and 2 of Jumper SJP2 will disable U17, which is the buffer providing the GPIO signals to the DAC EVM interface connector. See the TSW1400 EVM schematic for more details.

Jumpers JP3 and JP4 set the output voltage of buffers U16 and U17. These buffers provide GPIO signals between the TSW1400 and ADC and DAC EVM’s. When set to pins 1-2, the buffers will provide 1.8 V CMOS logic level signal interface to the ADC and DAC EVM connectors. When set to 2-3, the level will be 3 V. JP3 controls the ADC signals, and JP4 controls the DAC signals. See the TSW1400 EVM schematic for more details.

Jumper JP8 sets the signal output voltage of CMOS_PORT1[19:1] bus on connector J1. When set to pins 1-2, the FPGA will provide 1.8 V CMOS logic level signals. When set to 2-3, the level will be 3 V.

2.2.3 Fuses

Fuse F1 is in line with the EVM input power. This is used along with diode D14 to protect the board from surges and over voltage on the input power supply.

Fuse F2, when installed, will provide 6VDC to the DAC EVM interface connector J4.

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Hardware Configuration

2.3 LED's

Eleven LED’s are on the TSW1400EVM to indicate the presence of power and the state of the FPGA.

The LED on the left edge of the board illuminates to indicate the presence of a 5-V power to the board after SW7 is placed in the “ON” position.

LED D1 illuminates to indicate that the FPGA programming has completed and is now operational. USER_LED0 and LED1 indicate transmission of data samples over SPI interface. USER_LED2 turns off when the FPGA is in reset mode. USER_LED3 indicates the FPGA PLL1 is locked to the ADC input clock from port 0. USER_LED4 indicates the FPGA PLL2 is locked to the ADC input clock from port 1. USER_LED5 indicates that the DDR memory initialization is complete and the interface is ready to

use. USER_LED6 and LED7 indicate that the two SPI FIFO’s are empty. LED D10 indicates the presence of 6-V power to the DAC EVM interface connector J4.

2.4 Connectors

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CAUTION

When using this 6 VDC for a DAC EVM, make sure the DAC EVM power connection is removed.

The TSW1400 EVM has several connectors to allow for direct plug in of various TI CMOS and LVDS ADC and DAC EVM’s.

2.4.1 Input LVDS ADC Interface Connector

The connection between the TSW1400EVM and the ADC EVM to be tested is through a 128-pin High speed Samtec connector. 35 LVDS data pairs plus two LVDS clock pairs have a defined position in the connector pinout that is common between the TSW1400EVM and many TI ADC EVMs. For the parallel LVDS DDR data format, the bit clock runs at the same rate as the sample clock to the ADC. For the serial LVDS data format, the bit clock runs at a higher multiple of the ADC sample clock and is used to strobe the serial data into the TSW1400EVM and then de-serialize the data. For the serial LVDS data format, a second clock is provided, called the frame clock or FCLK, that runs at the sample rate and is used to delineate the sample boundaries in the serial data stream. The frame clock line can be used as a second clock in the parallel LVDS DDR format that uses two data buses. The data direction for the LVDS data pairs is always defined as the ADC EVM driving the signal through the connector to the TSW1400EVM FPGA, with integrated 100 Ω termination in the FPGA.

For one-channel parallel DDR bit-wise data formats, eight of the LVDS data pairs are used to support up to 16-bit-resolution ADCs at up to 250-MHz sampling rates. For one-channel parallel DDR sample-wise data formats, 14 of the LVDS data pairs are used to support up to 14-bit-resolution ADCs at up to 500-MHz sampling rates. For two-channel parallel DDR bit-wise data formats, 14 of the LVDS data pairs are used to support two channels of 14-bit resolution at up to 250-MHz sampling rate.

For serial data formats, eight of the LVDS data pairs support up to eight channels of one-wire serial ADCs at up to 65-MHz sampling rate or four channels of two-wire serial ADCs at up to 125-MHz sampling rates.

Eight extra CMOS single-ended signals are defined in the Samtec connector that are sourced from the USB interface through the connector to the ADC EVM. These signals, in the future, will allow the GUI to control the SPI serial programming of the ADC for those ADC EVMs that support this feature.

The Samtec connectors snap together with no screws or other mechanism to hold the TSW1400EVM and the ADC EVM together. The TSW1400EVM comes with standoff posts for setting the TSW1400EVM flat on a bench or table. The ADC EVM has shorter standoff posts so that the TSW1400EVM and ADC EVM will lay flat on a bench or table and stay snapped together during use.

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2.4.2 JTAG Connector

The TSW1400EVM includes an industry-standard JTAG connector that connects to the JTAG ports of the FPGA and the programming pins of the FPGA EEPROM. Jumpers on the TSW1400EVM allow for either the FPGA or the FPGA EEPROM to be programmed from the JTAG chain. The JTAG connector is to be used for trouble shooting only. The board default setup is with the FPGA JTAG pins connected to the USB interface. This allows the FPGA to be programmed by the GUI though the USB interface. The current design does not support the use of the FPGA EEPROM. Every time the TSW1400 EVM is powered down, the FPGA configuration is removed. The user must program the FPGA through the GUI after every time the board is powered up.

In future versions, once the FPGA is power-cycled or re-programmed by the CONF/SPI pushbutton, the current loaded FPGA bit file will be lost and the FPGA will revert to the bit file that is stored in the FPGA EEPROM.

2.4.3 Input CMOS ADC Interface Connector

The TSW1400EVM includes a CMOS ADC interface connector (J1) which is currently not supported. For ADC EVM’s that require CMOS data capture, the TSW1200EVM is recommended.

2.4.4 Output LVDS Connector

The connection between the TSW1400EVM and the DAC EVM to be tested is through a 192-pin High speed Samtec connector. 32 LVDS output data pairs plus two LVDS output clock pairs, four differential control pairs (sync, strobes, and so on), two input clock pairs, eight general purpose CMOS I/O pins (USB controlled) and 10 general purpose CMOS I/O pins (FPGA controlled). These signals have a defined position in the connector pinout that is common between the TSW1400EVM and many TI DAC EVM’s.

Software Start up

2.4.5 Output CMOS DAC Interface Connector

The TSW1400 has a CMOS interface that is currently unsupported. If the DAC EVM supports a CMOS single-ended format, then the TSW3100 system is recommended to be used.

2.4.6 USB I/O Connection

Control of the TSW1400EVM is through a USB connection to a PC running Windows operating system. For the computer, the drivers needed to access the USB port are included on the TSW1400 installation software that can be downloaded from the web. The drivers are automatically installed during the installation process. On the TSW1400EVM, the USB port is used to identify the type and serial number of the EVM under test, load the desired FPGA configuration file, capture data from ADC EVM’s, and send test pattern data to the DAC EVM’s.

On first connection of the USB port to a computer, the Microsoft Found New Hardware Wizard appears. Follow the dialog box prompts as covered in the Software Installation section of this User’s Guide.

3 Software Start up

3.1 Installation Instructions

• Download the latest version of the GUI software files and User’s Guide manual to a local location on a host PC. These can be found on the TI website by entering “TSW1400EVM” in the search parameter window at TI.com.

• Unzipping the software package will generate a folder called “High Speed Data Converter Pro xpx", where xpx is the version number. Under this folder will be a “setup.bat file, a folder called “EVM GUI” and another folder called “FTDI”. The EVM GUI folder contains the GUI code and the other folder contains the drivers for the USB interface.

• If running the software for the first time, run the file called “setup.bat”. This will load the FTDI drivers followed by installing the HighSpeed Data Converter Pro GUI software.

• Follow the on-screen instructions during installation.

• Once installed, the GUI executable will reside in the following directory.

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Software Start up

•

C:\Program Files\Texas Instruments\High Speed Data Converter Pro.

• Connect one end of a mini-USB cable to J5 (top right corner) of the TSW1400 and the other end to a host PC USB port.

NOTE: Launch and connect the TSW1400 GUI to the EVM before starting older TI HSDC GUI’s.

• If not already connected, connect the provided 5 VDC power supply to J12, located on the bottom left corner of the board and the end to 110-120 VAC source. Set SW7 to the “ON” position.

• To start the GUI, click on the file called “High Speed Data Converter Pro.exe", located under “C:\Program Files\Texas Instruments\High Speed Data Converter Pro”.

NOTE: If an older version of the GUI has already been installed, make sure to uninstall it before loading a newer version.

3.2 USB Interface and Drivers

The TSW1400 GUI will first attempt to connect to the EVM USB interface. If the GUI identifies a valid board serial number, a pop-up will open displaying this value, as shown in Figure 2. The serial number will also have an EVM type number attached to it. This indicates to the GUI which of the three TSW140x boards is being used. It is possible to connect several TSW1400 EVM’s to one host PC but the GUI can only connect to one at a time. In the case were multiple boards are connected to the PC, the pop-up will display all of the serial numbers found. It is then up to the user to select which board the GUI will be associated.

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Figure 2. TSW1400EVM Serial Number

Click on “OK” to connect the GUI to the board. If the FPGA firmware version read by the GUI does not match the firmware to be used as determined by the device selected, the following message will appear as shown in Figure 3. This message also appears after power up as the FPGA is not programmed.

Figure 3. Firmware Does Not Match the Device Selected

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Click on “OK”. The Top level GUI will now open and appear as shown in Figure 4.

Software Start up

Figure 4. TSW1400EVM GUI Top Level

After the software has established a connection, if the message “Board not Connected” opens, double check the USB cable connections and that power switch SW7 is in the “ON” position. If the cable connections appear fine, try establishing a connection by clicking on the “Instrument Option” tab at the top left of the GUI and select “Connect to the Board” (see Figure 5). If this still does not correct this issue, check the status of the host USB port.

Figure 5. Connecting GUI to EVM

When the software is installed and the USB cable has been connected the TSW1400EVM and the PC, the TSW1400 USB serial converter should be located in the Hardware Device Manager under the Universal Serial Bus controllers as shown in Figure 6. This is a quad device which is why there is an A, B, C, and D USB Serial Converter shown. When the USB cable is removed, these four will no longer be visible in the Device Manager. If the drivers are present in the Device Manager window and the software still does not connect, cycle power to the board and repeat the steps above.

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User Interface

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3.3 Device ini Files

Included in the installation for the TSW1400 GUI software is a subdirectory of ini files for each category of ADC and DAC that is supported by the TSW1400EVM. TI strongly recommends that these files are not edited except at the factory. These files contain necessary information for the GUI software to properly configure the TSW1400EVM FPGA registers for proper operation with the desired ADC or DAC EVM. Some of the entries within the ini file are obvious, such as defining the bit resolution for a device to be 11, 12, 14, or 16 bits. Other entries in the ini file define for the FPGA which LVDS pairs within the Samtec connector define the data bus, and correct operation may not be possible if these entries are edited. The use of ini files allows for new device types to be supported by the TSW1400EVM as they become available without having to modify, re-release, or re-install the TSW1400 GUI software. New device types may be supported at a later date simply by adding a new ini file to the proper subdirectory. This file can be found on the TI website under the TSW1400 product folder.

4 User Interface

When the TSW1400 GUI software is started, the initial setup screen of Figure 4 appears. The TSW1400EVM serial number is reported in the lower center of the GUI. After the FPGA is loaded with the selected firmware, the GUI would reports the firmware version in the bottom left and the interface type will be reported in the lower right. The connection status should read “Connected” and be highlighted in green (lower center of the GUI). The status pane, located in the lower right, will report “IDLE”. Many of the TSW1400 software controls are available from the main screen, such as “ADC or DAC” mode, “Select device”, “Capture and Test Selection” (ADC mode only), and “Load File to transfer to TSW1400” (DAC mode only).

Figure 6. Hardware Device Manager

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4.1 Toolbar

The toolbar contains options and settings that are independent of the device selected for test or the test to be performed, such as configuration options and save/recall operations. The operations available under the toolbar are grouped in categories as follows: File, Instrument Option, Data Capture Option, Test Option and Help.

4.1.1 File Options

The file tab contains all of the options for saving or importing test results. Placing the mouse indicator over the File tab will open a window with the available options as shown in Figure 7.

There are options for saving the ADC captured data as CSV or Binary format in a directory specified by the user for export or archival purposes. The “Save as CSV File” and “Save as Binary File” will save the results that are displayed in the test window. If the Single Tone FFT test is active, then the FFT plot will be saved, along with the performance statistics and setup information. If the Time Domain test is active, then the Time Domain plot will be saved along with the time domain statistics. The “Save Screen shot as “ option, when selected, will open a window that will allow the user to save the current GUI screen shot as either a bmp, jpeg, or png file in the directory specified by the user.

The GUI provides an option to use simulated input data in place of an actual ADC evm. To use this feature, select ‘Simulate ADC” in the device selection drop down. Click on the “Capture” button. A new window will open asking for an input test file. This file must be in text format having integer values from

-32768 to 32767, one column per channel, and will be used by the GUI as input data for display and

analysis. For two channel test cases, this file must be 16 bit interleaved binary data, where channel 1 is the first sample and channel 2 is the second sample.

User Interface

Figure 7. File Tab Options

4.1.2 Instrument Options

The Instrument Options menu tab contains four options: Reinitialize Instrument, Read EVM Setup Procedure, Download Firmware, and Connect to the Board as shown in Figure 8.

Figure 8. Instrument Options

The Read ADC EVM Setup Procedure command causes the TSW1400 software to read a comment string from the ini file for the device that is currently selected and then display that comment string in the status pane. This comment string generally contains necessary setup information pertaining to the EVM under test, such as possibly requiring a non-default data format or required jumper setting for the EVM to communicate properly with the TSW1400EVM.

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