Texas Instruments TSB41LV03APFP, TSB41LV03AIPFP Datasheet

Fully Supports Provisions of IEEE 1394-1995 Standard for High Performance Serial Bus† and the P1394a Supplement

Fully Interoperable With FireWire and i.LINK Implementation of IEEE Std 1394

Fully Compliant With OpenHCI Requirements

Provides Three P1394a Fully Compliant Cable Ports at 100/200/400 Megabits per Second (Mbits/s)

Full P1394a Support Includes: Connection Debounce, Arbitrated Short Reset, Multispeed Concatenation, Arbitration Acceleration, Fly-By Concatenation, Port Disable/Suspend/Resume

Extended Resume Signaling for Compatibility With Legacy DV Devices

Power-Down Features to Conserve Energy in Battery Powered Applications Include: Automatic Device Power-Down During Suspend, Device Power-Down Terminal, Link Interface Disable via LPS, and Inactive Ports Powered Down

Ultra Low-Power Sleep Mode

Node Power Class Information Signaling for System Power Management

Cable Power Presence Monitoring

Cable Ports Monitor Line Conditions for Active Connection to Remote Node

description

TSB41LV03A, TSB41LV03AI

IEEE 1394a THREE-PORT CABLE TRANSCEIVER/ARBITER

SLLS364A – JULY 1999 – REVISED MAY 2000

Data Interface to Link-Layer Controller Through 2/4/8 Parallel Lines at 49.152 MHz

Interface to Link Layer Controller Supports Low Cost TI Bus-Holder Isolation and Optional Annex J Electrical Isolation

Interoperable With Link-Layer Controllers Using 3.3-V and 5-V Supplies

Interoperable With Other Physical Layers (PHYs) Using 3.3-V and 5-V Supplies

Low Cost 24.576-MHz Crystal Provides Transmit, Receive Data at 100/200/400 Mbits/s, and Link-Layer Controller Clock at

49.152 MHz

Incoming Data Resynchronized to Local Clock

Logic Performs System Initialization and Arbitration Functions

Encode and Decode Functions Included for Data–Strobe Bit Level Encoding

Separate Cable Bias (TPBIAS) for Each Port

Single 3.3-V Supply Operation

Low Cost High Performance 80-Pin TQFP (PFP) Thermally Enhanced Package

Direct Drop-In Upgrade for TSB41LV03PFP

The TSB41L V03A provides the digital and analog transceiver functions needed to implement a three-port node in a cable-based IEEE 1394 network. Each cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The TSB41LV03A is designed to interface with a line layer controller (LLC), such as the TSB12LV21, TSB12LV22, TSB12LV23, TSB12LV31, TSB12LV41, TSB12LV42 or TSB12L V01A.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

†

Implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thompson, Limited. i.LINK is a trademark of Sony Corporation FireWire is a trademark of Apple Computers Incorporated.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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SLLS364A – JULY 1999 – REVISED MAY 2000

description (continued)

The TSB41LV03A requires only an external 24.576 MHz crystal as a reference. An external clock may be provided instead of a crystal. An internal oscillator drives an internal phase-locked loop (PLL), which generates the required 393.216 MHz reference signal. This reference signal is internally divided to provide the clock signals used to control transmission of the outbound encoded strobe and data information. A 49.152 MHz clock signal is supplied to the associated LLC for synchronization of the two chips and is used for resynchronization of the received data. The power-down (PD) function, when enabled by asserting the PD terminal high, stops operation of the PLL.

The TSB41L V03A supports an optional isolation barrier between itself and its LLC. When the ISO is tied high, the LLC interface outputs behave normally . When the ISO terminal is tied low, internal differentiating logic is enabled, and the outputs are driven such that they can be coupled through a capacitive or transformer galvanic isolation barrier as described in Annex J of IEEE Std 1394-1995 and in the P1394a Supplement (section 5.9.4) (hereafter referred to as Annex J type isolation). T o operate with TI bus holder isolation, the ISO terminal on the PHY must be high.

Data bits to be transmitted through the cable ports are received from the LLC on two, four, or eight parallel paths (depending on the requested transmission speed). They are latched internally in the TSB41LV03A in synchronization with the 49.152-MHz system clock. These bits are combined serially , encoded, and transmitted at 98.304, 196.608, or 392.216 Mbits/s (referred to as S100, S200, and S400 speed respectively) as the outbound data-strobe information stream. During transmission, the encoded data information is transmitted differentially on the TPB cable pair(s), and the encoded strobe information is transmitted differentially on the TPA cable pair(s).

During packet reception the TP A and TPB transmitters of the receiving cable port are disabled, and the receivers for that port are enabled. The encoded data information is received on the TPA cable pair, and the encoded strobe information is received on the TPB cable pair. The received data-strobe information is decoded to recover the receive clock signal and the serial data bits. The serial data bits are split into two-, four-, or eight-bit parallel streams (depending upon the indicated receive speed), resynchronized to the local 49.152-MHz system clock and sent to the associated LLC. The received data is also transmitted (repeated) on the other active (connected) cable ports.

Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states during initialization and arbitration. The outputs of these comparators are used by the internal logic to determine the arbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of this common-mode voltage is used during arbitration to set the speed of the next packet transmission. In addition, the TPB channel monitors the incoming cable common-mode voltage on the TPB pair for the presence of the remotely supplied twisted-pair bias voltage.

input terminal

The TSB41L V03A provides a 1.86-V nominal bias voltage at the TPBIAS terminal for port termination. The PHY contains three independent TPBIAS circuits. This bias voltage, when seen through a cable by a remote receiver, indicates the presence of an active connection. This bias voltage source must be stabilized by an external filter capacitor of 1 µF.

The line drivers in the TSB41L V03A, operating in a high-impedance current mode, are designed to work with external 1 12-Ω line-termination resistor networks in order to match the 110-Ω cable impedance. One network is provided at each end of a twisted-pair cable. Each network is composed of a pair of series-connected 56-Ω resistors. The midpoint of the pair of resistors that is directly connected to the twisted-pair A terminals is connected to its corresponding TPBIAS voltage terminal. The midpoint of the pair of resistors that is directly connected to the twisted-pair B terminals is coupled to ground through a parallel R-C network with recommended values of 5 kΩ and 220 pF. The values of the external line-termination resistors are designed to meet the standard specifications when connected in parallel with the internal receiver circuits. An external resistor connected between the R0 and R1 terminals sets the driver output current, along with other internal operating currents. This current setting resistor has a value of 6.3 kΩ ±1%. This may be accomplished by placing a 6.34-kΩ ±1% resistor in parallel with a 1-MΩ resistor.

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IEEE 1394a THREE-PORT CABLE TRANSCEIVER/ARBITER

SLLS364A – JULY 1999 – REVISED MAY 2000

description (continued)

When the power supply of the TSB41L V03A is off while the twisted-pair cables are connected, the TSB41L V03A transmitter and receiver circuitry presents a high-impedance signal to the cable and will not load the TPBIAS voltage at the other end of the cable.

When the TSB41LV03A is used with one or more of the ports not brought out to a connector, the twisted-pair terminals of the unused ports must be terminated for reliable operation. For each unused port, the TPB+ and TPB– terminals can be tied together and then pulled to ground, or the TPB+ and TPB– terminals can be connected to the suggested termination network. The TP A+ and TPA– and TPBIAS terminals of an unused port can be left unconnected. The TPBias terminal can be connected to a 1-µF capacitor to ground or left floating.

The TESTM, SE, and SM terminals are used to set up various manufacturing test conditions. For normal operation, the TESTM terminal should be connected to V while SM should be connected directly to ground.

Four package terminals are used as inputs to set the default value for four configuration status bits in the self-ID packet, are hardwired high or low as a function of the equipment design. The PC0–PC2 terminals are used to indicate the default power-class status for the node (the need for power from the cable or the ability to supply power to the cable). See T able 9 for power-class encoding. The C/LKON terminal is used as an input to indicate that the node is a contender either isochronous resource manager (IRM) or for bus manager (BM).

, SE should be tied to ground through a 1-kΩ resistor,

The TSB41LV03A supports suspend/resume as defined in the IEEE P1394a specification. The suspend mechanism allows pairs of directly-connected ports to be placed into a low-power conservation state (suspended state) while maintaining a port-to-port connection between 1394 bus segments. While in the suspended state, a port is unable to transmit or receive data transaction packets. However, a port in the suspended state is capable of detecting connection status changes and detecting incoming TPBias. When all three ports of the TSB41LV03A are suspended all circuits except the bandgap reference generator and bias detection circuits are powered down resulting in significant power savings. For additional details of suspend/resume operation refer to the P1394a specification. The use of suspend/resume is recommended for new designs.

The port transmitter and receiver circuitry is disabled during power down (when the PD input terminal is asserted high), during reset (when the RESET port, or when controlled by the internal arbitration logic. The TPBias output is disabled during power-down, during reset, or when the port is disabled as commanded by the LLC.

The CNA (cable-not-active) terminal provides a high when there are no twisted-pair cable ports receiving incoming bias (i.e., they are either disconnected or suspended), and can be used along with LPS to determine when to power-down the TSB41L V03A. The CNA output is not debounced. When the PD terminal is asserted high, the CNA detection circuitry is enabled (regardless of the previous state of the ports) and a pull-down is activated on the RESET

The LPS (link power status) terminal works with the C/LKON terminal to manage the power usage in the node. The LPS signal from the LLC is used in conjunction with the LCtrl bit (see Table 1 and Table 2 in the APPLICA TION INFORMATION section) to indicate the active/power status of the LLC. The LPS signal is also used to reset, disable, and initialize the PHY-LLC interface (the state of the PHY-LCC interface is controlled solely by the LPS input regardless of the state of the LCtrl bit).

terminal so as to force a reset of the TSB41LV03A internal logic.

input terminal is asserted low), when no active cable is connected to the

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TSB41LV03A, TSB41LV03AI IEEE 1394a THREE-PORT CABLE TRANSCEIVER/ARBITER

SLLS364A – JULY 1999 – REVISED MAY 2000

description (continued)

The LPS input is considered inactive if it remains low for more than 2.6 µs and is considered active otherwise. When the TSB41L V03A detects that LPS is inactive, it will place the PHY -LLC interface into a low–power reset state in which the CTL and D outputs are held in the logic zero state and the LREQ input is ignored; however, the SYSCLK output remains active. If the LPS input remains low for more than 26 µs, the PHY-LLC interface is put into a low–power disabled state in which the SYSCLK output is also held inactive. The PHY -LLC interface is also held in the disabled state during hardware reset. The TSB41L V03A will continue the necessary repeater functions required for normal network operation regardless of the state of the PHY–LLC interface. When the interface is in the reset or disabled state and LPS is again observed active, the PHY will initialize the interface and return it to normal operation.

When the PHY-LLC interface in the low-power disabled state, the TSB41LV03A will automatically enter a low-power mode if all ports are inactive (disconnected, disabled, or suspended). In this low-power mode, the TSB41LV03A disables its internal clock generators and also disables various voltage and current reference circuits depending on the state of the ports (some reference circuitry must remain active in order to detect new cable connections, disconnections, or incoming TPBias, for example). The lowest power consumption (the

low-power sleep

enable bit cleared. The TSB41L V03A will exit the low-power mode when the LPS input is asserted high or when a port event occurs which requires that the TSB41L V03A become active in order to respond to the event or to notify the LLC of the event (e.g., incoming bias is detected on a suspended port, a disconnection is detected on a suspended port, a new connection is detected on a nondisabled port, etc.). The SYSCLK output will become active (and the PHY -LLC interface will be initialized and become operative) within 7.3 ms after LPS is asserted high when the TSB41LV03A is in the low-power mode.

mode) is attained when all ports are either disconnected, or disabled with the port’s interrupt

ultra

The PHY uses the C/LKON terminal to notify the LLC to power up and become active. When activated, the C/LKON signal is a square wave of approximately 163 ns period. The PHY activates the C/LKON output when the LLC is inactive and a wake-up event occurs. The LLC is considered inactive when either the LPS input is inactive, as described above, or the LCtrl bit is cleared to 0. A wake-up event occurs when a link-on PHY packet addressed to this node is received, or conditionally when a PHY interrupt occurs. The PHY deasserts the C/LKON output when the LLC becomes active (both LPS active and the LCtrl bit set to 1). The PHY also deasserts the C/LKON output when a bus-reset occurs unless a PHY interrupt condition exists which would otherwise cause C/LKON to be active.

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TSB41LV03A, TSB41LV03AI

IEEE 1394a THREE-PORT CABLE TRANSCEIVER/ARBITER

SLLS364A – JULY 1999 – REVISED MAY 2000

PFP PACKAGE

(TOP VIEW)

AGND

AGND AGND

R0 R1

DGND FILTER0 FILTER1

PLLV

PLLGND PLLGND

RESET

DGND

AGND

TPBIAS2

59 58 57 56 5560 54

61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

TP A2+

TP A2–

5678

TPB2+

TPB2–

TPBIAS1

TP A1+

TPA1–

52 51 5053

TSB41LV03A

9 10 11 12 13

TPB1+

TPB1–

49 48

DDAVDD

TPBIAS0

47 46 45 44

14 15 16 17

TPA0+

TPA0–

TPB0+

43 42 41

18 19 20

AGND

TPB0–

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

AGND AGND AGND AGND AGND AV

SM SE TESTM DV

DGND CPS ISO PC2 PC1 PC0 C/LKON DGND

LREQ

SYSCLK

CTL0

DGND

CTL1

DD–5V

CNA

DGND

LPS

DGND

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TSB41LV03A, TSB41LV03AI IEEE 1394a THREE-PORT CABLE TRANSCEIVER/ARBITER

SLLS364A – JULY 1999 – REVISED MAY 2000

functional block diagram

CPS LPS

ISO

CNA

SYSCLK

LREQ

CTL0 CTL1

D0 D1 D2 D3 D4 D5 D6 D7

Link

Interface

I/O

Received Data

Decoder/Retimer

Arbitration

and Control

State Machine

Logic

TPA0+ TPA0–

Cable Port 0

TPB0+ TPB0–

PC0 PC1 PC2

C/LK0N

R0 R1

TPBIAS0 TPBIAS1 TPBIAS2

RESET

Bias Voltage

and

Current Generator

Transmit

Data

Encoder

Cable Port 1

Cable Port 2

Crystal Oscillator,

PLL System,

and

Clock Generator

TPA1+ TPA1–

TPB1+ TPB1–

TPA2+ TPA2–

TPB2+ TPB2–

XI XO

FILTER0

FILTER1

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I/O

DESCRIPTION

TSB41LV03A, TSB41LV03AI

IEEE 1394a THREE-PORT CABLE TRANSCEIVER/ARBITER

SLLS364A – JULY 1999 – REVISED MAY 2000

Terminal Functions

TERMINAL

NAME TYPE NO.

AGND Supply 36, 37, 38,

CNA CMOS 17 O Cable not active output. This terminal is asserted high when there are no ports receiving incoming

CPS CMOS 27 I Cable power status input. This terminal is normally connected to cable power through a 400-kΩ

CTL0 CTL1

C/LKON CMOS 22 I/O Bus manager contender programming input and link-on output. On hardware reset, this terminal is

DGND Supply 3, 16, 20,

D0–D7 CMOS

Supply 34, 35, 47,

CMOS 5 V tol

5 V tol

Supply 6, 29, 30,

39, 40, 41, 60, 61, 64,

48, 54, 62,

4 5

21, 28, 70,

7, 8, 10,

11, 12, 13,

14, 15

68, 69, 79

– Analog circuit ground terminals. These terminals should be tied together to the low-impedance

circuit board ground plane.

– Analog circuit power terminals. A combination of high-frequency decoupling capacitors near each

terminal are suggested, such as paralleled 0.1 µF and 0.001 µF. Lower frequency 10-µF filtering capacitors are also recommended. These supply terminals are separated from PLLVDD and DV internal to the device to provide noise isolation. They should be tied at a low-impedance point on the circuit board.

bias voltage.

resistor. This circuit drives an internal comparator that is used to detect the presence of cable power .

I/O Control I/Os. These bidirectional signals control communication between the TSB41L V03A and the

LLC. Bus holders are built into these terminals.

used to set the default value of the contender status indicated during self-ID. Programming is done by tying the terminal through a 10-kΩ resistor to a high (contender) or low (not contender). The resistor allows the link-on output to override the input. However, it is recommended that this terminal should be programmed low , and that the contender status be set via the C register bit.

If the TSB41LV03A is used with an LLC that has a dedicated terminal for monitoring LKON and also setting the contender status, then a 10-kΩ series resistor should be placed on the LKON line between the PHY and LLC to prevent bus contention.

Following hardware reset, this terminal is the link-on output, which is used to notify the LLC to power–up and become active. The link-on output is a square-wave signal with a period of approximately 163 ns (8 SYSCLK cycles) when active. The link-on output is otherwise driven low, except during hardware reset when it is high impedance.

The link-on output is activated if the LLC is inactive (LPS inactive or the LCtrl bit cleared) and when: a) the PHY receives a link-on PHY packet addressed to this node, b) the PEI (port-event interrupt) register bit is 1, or c) any of the CTOI (configuration-timeout interrupt), CPSI (cable-power-status interrupt), or STOI

(state-timeout interrupt) register bits are 1 and the RPIE (resuming-port interrupt enable) register bit is also 1.

Once activated, the link-on output will continue active until the LLC becomes active (both LPS active and the LCtrl bit set). The PHY also deasserts the link-on output when a bus–reset occurs unless the link-on output would otherwise be active because one of the interrupt bits is set (i.e., the link-on output is active due solely to the reception of a link-on PHY packet).

NOTE: If an interrupt condition exists which would otherwise cause the link-on output to be activated if the LLC were inactive, the link-on output will be activated when the LLC subsequently becomes inactive.

– Digital circuit ground terminals. These terminals should be tied together to the low-impedance circuit

board ground plane.

I/O Data I/Os. These are bidirectional data signals between the TSB41LV03A and the LLC. Bus holders

are built into these terminals.

– Digital circuit power terminals. A combination of high-frequency decoupling capacitors near each

terminal are suggested, such as paralleled 0.1 µF and 0.001 µF. Lower frequency 10-µF filtering capacitors are also recommended. These supply terminals are separated from PLLVDD and AV internal to the device to provide noise isolation. They should be tied at a low-impedance point on the circuit board.

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I/O

DESCRIPTION

IEEE 1394a THREE-PORT CABLE TRANSCEIVER/ARBITER

SLLS364A – JULY 1999 – REVISED MAY 2000

Terminal Functions (Continued)

TERMINAL

NAME TYPE NO.

FILTER0 FILTER1

ISO CMOS 26 I Link interface isolation control input. This terminal controls the operation of output differentiation

LPS CMOS

LREQ CMOS

PC0 PC1 PC2

PD CMOS

PLLGND Supply 74, 75 – PLL circuit ground terminals. These terminals should be tied together to the low impedance circuit

PLLV

RESET CMOS 78 I Logic reset input. Asserting this terminal low resets the internal logic. An internal pullup resistor to

R0 R1

SE CMOS 32 I T est control input. This input is used in manufacturing test of the TSB41L V03A. For normal use this

CMOS 71

19 I Link power status input. This terminal is used to monitor the active/power status of the link layer

5 V tol

5 V tol CMOS 23

24 25

18 I Power-down input. A high on this terminal turns off all internal circuitry except the cable-active

5 V tol

Supply 73 – PLL circuit power terminals. A combination of high-frequency decoupling capacitors near each

Bias 66

I/O PLL filter terminals. These terminals are connected to an external capacitor to form a lag-lead filter

required for stable operation of the internal frequency-multiplier PLL running off of the crystal oscillator. A 0.1-µF ± 10% capacitor is the only external component required to complete this filter.

logic on the CTL and D terminals. If an optional isolation barrier of the type described in Annex J of IEEE Std 1394-1995 is implemented between the TSB41LV03A and LLC, the ISO be tied low to enable the differentiation logic. If no isolation barrier is implemented (direct connection), or TI bus holder isolation is implemented, the ISO the differentiation logic. For additional information refer to TI application note

Isolation

, SLLA011.

controller and to control the state of the PHY-LLC interface. This terminal should be connected to either the VDD supplying the LLC through a 10 kΩ resistor, or to a pulsed output which is active when the LLC is powered. A pulsed signal should be used when an isolation barrier exists between the LLC and PHY.(See Figure 8)

The LPS input is considered inactive if it is sampled low by the PHY for more than 2.6 µs (128 SYSCLK cycles), and is considered active otherwise (i.e., asserted steady high or an oscillating signal with a low time less than 2.6 µs). The LPS input must be high for at least 21 ns in order to be guaranteed to be observed as high by the PHY.

When the TSB41LV03A detects that LPS is inactive, it will place the PHY-LLC interface into a low-power reset state. In the reset state, the CTL and D outputs are held in the logic zero state and the LREQ input is ignored; however, the SYSCLK output remains active. If the LPS input remains low for more than 26 µs (1280 SYSCLK cycles), the PHY–LLC interface is put into a low–power disabled state in which the SYSCLK output is also held inactive. The PHY-LLC interface is placed into the disabled state upon hardware reset.

The LLC is considered active only if both the LPS input is active and the LCtrl register bit is set to 1, and is considered inactive if either the LPS input is inactive or the the LCtrl register bit is cleared to 0.

1 I LLC Request input. The LLC uses this input to initiate a service request to the TSB41LV03A. Bus

holder is built into this terminal.

I Power class programming inputs. On hardware reset, these inputs set the default value of the power

class indicated during self-ID. Programming is done by tying the terminals high or low. Refer to T able 9 for encoding.

monitor circuits, which control the CNA output. Asserting the PD input high also activates an internal pull-down on the RESET

board ground plane.

terminal are suggested, such as paralleled 0.1 µF and 0.001 µF. Lower frequency 10-µF filtering capacitors are also recommended. These supply terminals are separated from DVDD and AV internal to the device to provide noise isolation. They should be tied at a low-impedance point on the circuit board.

VDD is provided so only an external delay capacitor in parallel with a resistor are required for proper power-up operation (see RESET

terminal also incorporates an internal pulldown which is activated when the PD input is asserted high. This input is otherwise a standard logic input, and can also be driven by an open-drain type driver.

– Current setting resistor terminals. These terminals are connected to an external resistance to set the

internal operating currents and cable driver output currents. A resistance of 6.3 kΩ ±1% is required to meet the IEEE Std 1394-1995 output voltage limits.

terminal should be tied to GND through a 1-kΩ pulldown resistor.

terminal so as to force a reset of the internal control logic.

power-up reset

in the APPLICATIONS INFORMATION section). The

terminal should be tied high to disable

terminal should

Serial Bus Galvanic

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I/O

DESCRIPTION

diff

ible to th

diff

ible to th

TSB41LV03A, TSB41LV03AI

IEEE 1394a THREE-PORT CABLE TRANSCEIVER/ARBITER

SLLS364A – JULY 1999 – REVISED MAY 2000

Terminal Functions (Continued)

TERMINAL

NAME TYPE NO.

SM CMOS 33 I T est control input. This input is used in the manufacturing test of the TSB41LV03A. For normal use

SYSCLK CMOS 2 O System clock output. Provides a 49.152-MHz clock signal, synchronized with data transfers, to

TESTM CMOS 31 I T est control input. This input is used in the manufacturing test of the TSB41L V03A. For normal use

TPA0+ TPA1+ TPA2+

TPA0– TPA1– TPA2–

TPB0+ TPB1+ TPB2+

TPB0– TPB1– TPB2–

TPBIAS0 TPBIAS1 TPBIAS2

DD-5V

XI XO

Cable 45

52 58

Cable 44

51 57

Cable 43

50 56

Cable 42

49 55

Cable 46

53 59

Supply 9 – 5-V VDD terminal. This terminal should be connected to the LLC VDD supply when a 5-V LLC is

Crystal 76

this terminal should be tied to GND.

the LLC.

this terminal should be tied to VDD.

I/O

Twisted-pair cable A differential-signal terminals. Board traces from each pair of positive and negative

I/O

external load resistors and to the cable connector.

I/O

Twisted-pair cable B differential-signal terminals. Board traces from each pair of positive and negative

I/O

external load resistors and to the cable connector.

I/O Twisted-pair bias output. This provides the 1.86 V nominal bias voltage needed for proper

operation of the twisted-pair cable drivers and receivers, and for signaling to the remote nodes that there is an active cable connection. Each of these terminals, except for an unused port, must be decoupled with a 1.0 µF capacitor to ground. For the unused port, this terminal can be left unconnected.

used, and should be connected to the PHY DVDD when a 3-V LLC is used. A combination of high-frequency decoupling capacitors near this terminal is suggested, such as paralleled 0.1 µF and 0.001 µF. When this terminal is tied to a 5-V supply, all terminal bus holders are disabled, regardless of the state of the ISO are enabled when the ISO

– Crystal oscillator inputs. These terminals connect to a 24.576 MHz parallel resonant fundamental

mode crystal. The optimum values for the external shunt capacitors are dependent on the specifications of the crystal used (see section).

erential signal terminals should be kept matched and as short as poss

terminal. When this terminal is tied to a 3-V supply, bus holders

terminal is high.

crystal selection

in the APPLICATIONS INFORMATION

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TSB41LV03A, TSB41LV03AI IEEE 1394a THREE-PORT CABLE TRANSCEIVER/ARBITER

SLLS364A – JULY 1999 – REVISED MAY 2000

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

†

Supply voltage range, VDD (see Note 1) –0.3 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI (see Note 1) –0.5 V to VDD+0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-V tolerant I/O supply voltage range, V 5-V tolerant input voltage range, V

I-5V

–0.5 V to V

–0.3 V to 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DD-5V

+0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range at any output, VO –0.5 V to VDD+0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Electrostatic discharge (see Note 2) HBM:2 kV, MM:200 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free air temperature, TA(TSB41LV03A) 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(TSB41LV03AI) –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground.

2. HBM is Human Body Model, MM is Machine Model.

DISSIPATION RATING TABLE

PACKAGE

PFP

‡

This is the inverse of the traditional junction-to-ambient thermal resistance (R

1 oz. trace and copper pad with solder.

1 oz. trace and copper pad without solder.

For more information, refer to TI application note

TA ≤ 25°C

POWER RATING

5.05 W 50.5 mW/°C 2.79 W 2.02 W

3.05 W 30.5 mW/°C 1.68 W 1.22 W

2.01 W 20.1 mW/°C 1.11 W 0.80 W

DERATING FACTOR

ABOVE TA = 25°C

PowerPAD Thermally Enhanced Package,

‡

TA = 70°C

POWER RATING

θJA

TA = 85°C

POWER RATING

TI literature number SLMA002.

PowerPAD is a trademark of Texas Instruments.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Suppl

oltage, V

High level in ut voltage, V

Low level in ut voltage, V

(

)

°C

characteristics table)

Differential input voltage, V

Common-mode input voltage, V

IEEE 1394a THREE-PORT CABLE TRANSCEIVER/ARBITER

recommended operating conditions

y v

Output current, I Output current, I

Maximum junction temperature, T

see

θJA

characteristics table

Power-up reset time, t

Receive input jitter

Receive input skew

†

All typical values are at VDD = 3.3 V and TA = 25°C.

‡

For a node that does not source power; see Section 4.2.2.2 in IEEE P1394a.

OL/OH O

ues listed in therma

Source power node 3 3.3 3.6 Non-source power node 2.7 Case1 (Bus Holder): ISO = VDD, V

Case2 (5 V Tol): ISO LREQ, CTL0, CTL1, D0–D7

C/LKON, PC0, PC1, PC2, ISO, PD 0.7×V RESET 0.6×V Case1 (Bus Holder): ISO = VDD, V

Case2 (5 V Tol): ISO LREQ, CTL0, CTL1, D0–D7

C/LKON, PC0, PC1, PC2, ISO, PD 0.2×V RESET 0.3×V CTL0, CTL1, D0–D7, CNA, C/LKON, and SYSCLK –12 12 mA TPBIAS outputs –5.6 1.3 mA R

= 19.8°C/W TA = 70°C TSB41LV03A 86

θJA

= 19.8°C/W TA = 85°C TSB41LV03AI 101

θJA

= 32.8°C/W TA = 70°C TSB41LV03A 96.5

θJA

= 32.8°C/W TA = 85°C TSB41LV03AI 112

θJA

= 49.8°C/W TA = 70°C TSB41LV03A 110.3

θJA

= 49.8°C/W TA = 85°C TSB41LV03AI 125

θJA

Cable inputs, during data reception 118 260 Cable inputs, during arbitration 168 265 TPB cable inputs, Source power node 0.476 2.515

TPB cable inputs, Non-source power node 0.476 2.015 RESET input 2 ms TPA, TPB cable inputs, S100 operation ±1.08 TPA, TPB cable inputs, S200 operation ±0.5 TPA, TPB cable inputs, S400 operation ±0.315 Between TPA and TPB cable inputs, S100 operation ±0.8 Between TPA and TPB cable inputs, S200 operation ±0.55 Between TPA and TPB cable inputs, S400 operation ±0.5

= VDD, V

DD-5V

= 5 V

DD-5V

= 5 V

= V

TSB41LV03A, TSB41LV03AI

SLLS364A – JULY 1999 – REVISED MAY 2000

MIN TYP

‡

2.6

DD DD

†

MAX UNIT

3 3.6

1.2

DD DD

‡

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TSB41LV03A, TSB41LV03AI

ZIDDifferential impedance

Drivers disabled

ZICCommon-mode impedance

Drivers disabled

IEEE 1394a THREE-PORT CABLE TRANSCEIVER/ARBITER

SLLS364A – JULY 1999 – REVISED MAY 2000

electrical characteristics over recommended ranges of operating conditions (unless otherwise noted) driver

PARAMETER TEST CONDITION MIN MAX UNIT

DIFF

SP200

SP400

OFF

†

Limits defined as algebraic sum of TPA+ and TPA– driver currents. Limits also apply to TPB+ and TPB– algebraic sum of driver currents.

‡

Limits defined as absolute limit of each of TPB+ and TPB– driver currents.

receiver

TH-R

TH-CB VTH+ Positive arbitration comparator threshold voltage Drivers disabled 89 168 mV VTH– Negative arbitration comparator threshold voltage Drivers disabled –168 –89 mV

TH–SP200

TH–SP400

Differential output voltage 56 Ω, See Figure 1 172 265 mV Driver difference current, TP A+, TPA–, TPB+, TPB– Drivers enabled, speed signaling off. –1.05†1.05 Common-mode speed signaling current, TPB+, TPB– S200 speed signaling enabled –4.84‡–2.53 Common-mode speed signaling current, TPB+, TPB– S400 speed signaling enabled –12.4‡–8.10 Off state differential voltage Drivers disabled, See Figure 1 20 mV

PARAMETER TEST CONDITION MIN TYP MAX UNIT

Receiver input threshold voltage Drivers disabled –30 30 mV Cable bias detect threshold, TPBx cable inputs Drivers disabled 0.6 1.0 V

Speed signal threshold

TPBIAS–TPA common mode voltage, drivers disabled

10 14 kΩ

20 kΩ

49 131 mV

314 396 mV

† ‡ ‡

4 pF

24 pF

mA mA mA

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g g,,,

Pullup current, /RESET input

TSB41LV03A, TSB41LV03AI

IEEE 1394a THREE-PORT CABLE TRANSCEIVER/ARBITER

SLLS364A – JULY 1999 – REVISED MAY 2000

electrical characteristics over recommended ranges of operating conditions (unless otherwise noted) (continued)

device

PARAMETER TEST CONDITION MIN TYP MAX UNIT

See Note 3 163

DD–ULP

OH–AJ

OL–AJ

BH+

BH–

IRST

SE–PU

VIT+

VIT–

†

Measured at cable power side of resistor.

‡

This parameter applicable only when ISO

NOTES: 3. Transmit Max Packet (3 ports transmitting max size isochronous packet – 4096 bytes, sent on every isochronous interval, s400,

Supply current

Supply current – ultra low power mode Power status threshold, CPS input

High-level output voltage, CTL0, CTL1, D0–D7, CNA, C/LKON, SYSCLK outputs

Low-level output voltage, CTL0, CTL1, D0–D7, CNA, C/LKON, SYSCLK outputs

High-level Annex J output voltage, CTL0, CTL1, D0–D7, C/LKON, SYSCLK outputs

Low-level Annex J output voltage, CTL0, CTL1, D0–D7, C/LKON, SYSCLK outputs

Positive peak bus holder current, D0–D7, CTL0–CTL1, LREQ

Negative peak bus holder current, D0–D7, CTL0–CTL1, LREQ

Input current, LREQ, LPS, PD, TESTM, SM, PC0–PC2 inputs

Off-state output current, CTL0, CTL1, D0–D7, C/LKON I/O’s

Pullup current, SE input VI = 1.5 V or 0 V –50 –5 µA Positive input threshold voltage, LREQ,

CTL0, CTL1, D0–D7 inputs Positive input threshold voltage, LPS inputs Negative input threshold voltage, LREQ,

CTL0, CTL1, D0–D7 inputs Negative input threshold voltage, LPS

inputs TPBIAS output voltage At rated IO current 1.665 2.015 V

data value of 0xCCCCCCCCh), VDD= 3.3 V, TA=25°C

4. Repeat typical packet (1 port receiving DV packets on every isochronous interval, 2 ports repeating the packet, s100), V TA= 25°C

5. Idle (3 ports transmitting cycle starts), VDD = 3.3 V, TA = 25°C

†

‡

low.

See Note 4 122 See Note 5 104 VDD = 3.3 V, TA = 25°C,

Ports disabled, PD=0V, LPS=0V 400–kΩ resistor VDD=2.7 V , IOH = –4 mA 2.2 V VDD=3 to 3.6 V, IOH = –4 mA 2.8 V

IOL = 4 mA 0.4 V Annex J: IOH= –9 mA,

/ISO = 0V, V VDD ≥ 3.0V

Annex J: IOL= 9 mA, /ISO = 0V, V VDD ≥ 3.0V

/ISO = 3.6V , VDD = 3.6V, VI = 0 V to VDD,V

ISO = 3.6V, VDD = 3.6V, VI = 0 V to VDD,V

/ISO=0V, VDD = 3.6 V 1 µA

VO = VDD or 0 V ±5 µA

= 1.5 V or 0

DD_5V=VDD

ref=VDD

/ISO= 0 V, V /ISO= 0 V, V

ref=VDD

†

= V

DD_5V

TSB41LV03A –90 –20 TSB41LV03AI –100 –20

, ISO= 0 V VDD/2+0.3 VDD/2+0.9 V

/ISO= 0 V,

× 0.42

DD_5V=VDD DD_5V=VDD,

× 0.42

= V

4.7 7.5 V

VDD–0.4 V

0.05 1 mA

–1.0 –0.05 mA

VDD/2–0.9 VDD/2–0.3 V

+0.2 V

ref

150 µA

0.4 V

+1 V

ref

= 3.3 V ,

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TSB41LV03A, TSB41LV03AI

recommended test board, chi soldered or greased to

tdDelay time, SYSCLK to CTL0, CTL1, D1–D7

50% to 50%,See Figure 3

IEEE 1394a THREE-PORT CABLE TRANSCEIVER/ARBITER

SLLS364A – JULY 1999 – REVISED MAY 2000

electrical characteristics over recommended ranges of operating conditions (unless otherwise noted) (continued)

thermal characteristics

PARAMETER TEST CONDITION MIN TYP MAX UNIT

Junction-to-free-air thermal resistance

θJA

Junction-to-case-thermal resistance

θJC

Junction-to-free-air thermal resistance

θJA

Junction-to-case-thermal resistance

θJC

Junction-to-free-air thermal resistance

θJA

Junction-to-case-thermal resistance

θJC

switching characteristics

PARAMETER TEST CONDITION MIN TYP MAX UNIT

Jitter, transmit Between TPA and TPB ±0.15 ns Skew, transmit Between TPA and TPB ±0.10 ns

TP differential rise time, transmit 10% to 90%, At 1394 connector 0.5 1.2 ns

TP differential fall time, transmit 90% to 10%, At 1394 connector 0.5 1.2 ns

Setup time, CTL0, CTL1, D1–D7, LREQ to

SYSCLK Hold time, CTL0, CTL1, D1–D7, LREQ after

SYSCLK

Board mounted, No air flow, High conductivity TI

thermal land with 1 oz. copper Board mounted, No air flow, High conductivity TI

recommended test board with thermal land but no solder or grease thermal connection to thermal land with 1 oz. copper

Board mounted, No air flow, High conductivity JEDEC test board with 1 oz. copper

50% to 50%, See Figure 2 5 ns

50% to 50%, See Figure 2 2 ns

TSB41LV03A 2 11 TSB41LV03AI 1 11

19.8 °C/W

0.17 °C/W

32.8 °C/W

0.17 °C/W

49.8 °C/W

3.6 °C/W

PARAMETER MEASUREMENT INFORMATION

TPAx+ TPBx+

56 Ω

TPAx– TPBx–

Figure 1. Test Load Diagram

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Address

TSB41LV03A, TSB41LV03AI

IEEE 1394a THREE-PORT CABLE TRANSCEIVER/ARBITER

SLLS364A – JULY 1999 – REVISED MAY 2000

PARAMETER MEASUREMENT INFORMATION

SYSCLK

D, CTL, LREQ

Figure 2. Dx, CTLx, LREQ Input Setup and Hold Time Waveforms

SYSCLK

D, CTL, LREQ

Figure 3. Dx and CTLx Output Delay Relative to SYSCLK Waveforms

internal register configuration

APPLICATION INFORMATION

There are 16 accessible internal registers in the TSB41L V03A. The configuration of the registers at addresses 0h through 7h (the base registers) is fixed, while the configuration of the registers at addresses 8h through Fh (the paged registers) is dependent upon which one of eight pages, numbered 0h through 7h, is currently selected. The selected page is set in base register 7h.

The configuration of the base registers is shown in T able 1, and corresponding field descriptions given in T able 2 The base register field definitions are unaffected by the selected page number.

A reserved register or register field (marked as Reserved or Rsvd in the following register configuration tables) is read as 0, but is subject to future usage. All registers in address pages 2 through 6 are reserved.

Table 1. Base Register Configuration

BIT POSITION

0 1 2 3 4 5 6 7

0000 Physical ID R CPS 0001 RHB IBR Gap_Count 0010 Extended (111b) Rsvd Num_Ports (0011b) 0011 PHY_Speed (010b) Rsvd Delay (0000b) 0100 LCtrl C Jitter (000b) Pwr_Class 0101 RPIE ISBR CTOI CPSI STOI PEI EAA EMC 0110 Reserved 0111 Page_Select Rsvd Port_Select

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