Texas Instruments TS3A227E Datasheet

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SCDS358B –NOVEMBER 2014–REVISED FEBRUARY 2015

TS3A227E Autonomous Audio Accessory Detection and Configuration Switch

1 Features 3 Description

• Supple Range of 2.5 V to 4.5 V

• Accessory Insertion/Removal Detection with Adjustable De-bounce Timings

• Accessory Configuration Detection: – Stereo 3-pole Headphone – 4-pole Standard Headset with MIC on Sleeve – 4-pole OMTP Headset with MIC on Ring2

• Key Press Detection for Up to 4 Keys

• Ultra Low Ground FET RONof 60 mΩ

• Power Off Noise Removal

• Isolation of MICBIAS From Audio Jack to Remove Click/Pop Noise

• Integrated Codec Sense Line

• Manual I2C Control

• FM Transmission Capability

• Dual Small Package Options – 16 Pin DSBGA – 16 Pin QFN

2 Applications

• Mobile Phones

• Tablets

• Notebooks and Ultrabooks

• Anywhere a 3.5 mm Audio Jack is Used

The TS3A227E is an autonomous audio accessory detection and configuration switch that detects 3-pole or 4-pole audio accessories and configures internal switches to route the signals accordingly.

The internal ground FETS of the TS3A227E have an ultra-low RONof 60 mΩ to minimize crosstalk impact. The ground FETs are also designed to pass FM signals, making it possible to use the ground line of the accessory as an FM antenna in mobile audio applications.

Internal isolation switches allow the TS3A227E to remove the click/pop noise that can be generated during and insertion or removal of an audio accessory. In addition depletion FETs prevent a floating ground while the device is unpowered, removing the humming noise present when leaving accessories plugged into an unpowered system.

A low-power sleep mode is provided which shuts down internal circuitry to achieve very low quiescent current draw when no headset is inserted.

The TS3A227E features integrated key press detection for detecting up to 4 keys with press and release support.

Manual I2C control allows the TS3A227E to adapt to application needs by providing control over debounce settings and switch states.

Device Information

PART NUMBER PACKAGE BODY SIZE (NOM)

TS3A227E

(1) For all available packages, see the orderable addendum at

the end of the datasheet.

TS3A227E

(1)

QFN (16) 3.50 mm × 3.50 mm DSBGA (16) 1.79 mm × 1.79 mm

4 Simplified Schematic

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

TS3A227E

SCDS358B –NOVEMBER 2014–REVISED FEBRUARY 2015

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1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description ............................................................. 1

4 Simplified Schematic............................................. 1

5 Revision History..................................................... 2

6 Pin Configuration and Functions......................... 3

7 Specifications......................................................... 4

7.1 Absolute Maximum Ratings...................................... 4

7.2 ESD Ratings ............................................................ 4

7.3 Recommended Operating Conditions....................... 5

7.4 Thermal Information.................................................. 5

7.5 Electrical Characteristics........................................... 6

7.6 I2C Interface Timing Characteristics ......................... 8

7.7 Timing Diagrams....................................................... 9

7.8 Typical Characteristics............................................ 12

8 Parameter Measurement Information ................ 12

9 Detailed Description ............................................ 17

9.1 Overview ................................................................. 17

9.2 Functional Block Diagram....................................... 18

9.3 Feature Description................................................. 19

9.4 Device Functional Modes........................................ 20

9.5 Register Maps ........................................................ 24

9.6 Register Field Descriptions..................................... 24

10 Application and Implementation........................ 33

10.1 Application Information.......................................... 33

10.2 Typical Application ............................................... 33

11 Power Supply Recommendations..................... 47

12 Layout................................................................... 48

12.1 Layout Guidelines ................................................. 48

12.2 Layout Example (QFN)......................................... 48

12.3 Layout Example (DSBGA).................................... 49

13 Device and Documentation Support................. 50

13.1 Trademarks........................................................... 50

13.2 Electrostatic Discharge Caution............................ 50

13.3 Glossary................................................................ 50

14 Mechanical, Packaging, and Orderable

Information........................................................... 50

5 Revision History

Changes from Revision A (December 2014) to Revision B Page

• Added DSBGA package to the Thermal Information table. ................................................................................................... 5

• Updated SWITCH RESISTANCE for the DSBGA package. ................................................................................................. 6

Changes from Original (July 2014) to Revision A Page

• Initial release of full version document. ................................................................................................................................. 1

Product Folder Links: TS3A227E

GND

TIP

GND

SDA

VDD

MICP

GNDA

RING2

SLEEVE

SCL

THERMALPAD

16 15 14 13

5 6 7 8

RING2_SENSE

SLEEVE_SENSE

GND_SENSE

DET_TRIGGER

MC_PRESENT

INT

4 3 2 1

VDD

SLEEVE_

SENSE

GND

INT

SDA

SCL

GND

TIP

RING2

MICP

RING2_ SENSE

MIC_

PRESENT

GND_

SENSE

DET_

TRIGGER

SLEEVE GNDA

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6 Pin Configuration and Functions

TS3A227E

SCDS358B –NOVEMBER 2014–REVISED FEBRUARY 2015

NAME RVA YFF

DET_TRIGGER 15 B1 I/O GND 1, 2 A2, B2 GND Primary ground connection for the TS3A227E. Must be connected to system ground. GNDA 11 D2 I/O GND_SENSE 5 A4 I/O Ground sense line for the codec. INT 13 C2 GND MIC_PRESENT 16 A1 I/O Open drain output to indicate to the host that a headset with a microphone is inserted..

MICP 6 B4 I/O Microphone signal connection to the codec. Microphone bias is applied to this pin. RING2 12 D1 O

RING2_SENSE 7 C4 GND SCL 9 C3 I

SDA 3 B3 I/O SLEEVE 10 D3 O

SLEEVE_SENSE 8 D4 GND

THERMAL PAD GND TIP 14 C1 I/O Connect to the TIP pin of the 3.5 mm jack.

VDD 4 A3 PWR Power input to the TS3A227E. External de-coupling capacitors are required on this pin.

DSBGA – YFF

Top View

Pin Functions

TYPE DESCRIPTION

A falling edge from high to low on this pin triggers accessory detection. This pin can be connected the headset jack to allow automatic pull-down to ground after headset insertion to initialize detection.

Ground connection for the internal ground FETs of the TS3A227E. If FM is being supported connect this pin to the FM matching network. If FM is not being support connect this pin to system ground.

Open drain interrupt output from the TS3A227E to notify the host that an event has occurred. If I2C is not used this pin must be grounded.

Headset current return path if RING2 is ground for the headset. Connect to 3.5 mm jack RING2 connection with low DC resistance trace.

Connected to the RING2 pin of the 3.5 mm jack. If RING2 pin on plug in is MIC signal, this is connected to MICP. If not, this is connected to GND_SENSE and becomes the ground sensing feedback for the accessory

Clock from I2C bus. This can be connected to VDD if I2C is not used. Bidirectional data from/to I2C bus. This can be connected to VDD if I2C is not used.

Headset current return path if SLEEVE is GND for headset. Connect to 3.5 mm jack SLEEVE connection with low DC resistance trace.

Connected to the SLEEVE pin of the 3.5 mm jack. If SLEEVE pin on plug in is MIC signal, this is connected to MICP. If not, this is connected to GND_SENSE and becomes the ground sensing feedback for the accessory

The THERMAL PAD of the RVA – QFN package must be connected to any internal PCB ground plane using multiple vias for best thermal performance.

QFN – RVA

Top View

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TS3A227E

SCDS358B –NOVEMBER 2014–REVISED FEBRUARY 2015

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range referenced with respect to GND (unless otherwise noted)

MIN MAX UNIT

Input Voltage VDD –0.3 5 V

SDA, SCL, INT, MIC_PRESENT –0.3 VDD+ 0.5 V TIP –3.3 VDD+ 0.5 V DET_TRIGGER –2.2 VDD+ 0.5 V GND_SENSE, RING2, SLEEVE, RING2_SENSE, SLEEVE_SENSE, –0.3 3.6

MICP, GNDA 0.5

ON-state switch Combined continuous current through R2GNDFET and SLV GNDFET 500 mA current

Operating ambient temperature range –40 85 °C T

stg

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) This rating is exclusive and the voltage on the pins must not exceed either 3.6 and VDD. E.g. if VDD= 4.5 V the voltage on the pin must

not exceed 3.6 V and if VDDis = 2.5 V the voltage on the pin must not exceed 3.0 V.

Continuous current through R2DFET and SLV DFET 50 Continuous current through S1 20 Continuous current through S2 20 Continuous current through S3PR 50 Continuous current through S3PS 50 Continuous current through S3GR 100 Continuous current through S3GS 100

Storage temperature range –65 150 °C

(1)

(2)

and VDD+ V

7.2 ESD Ratings

VALUE UNIT

Human body model (HBM), ESD stress voltagenew note #1 to the ESD Ratings table and combined MIN MAX column to VALUE

Electrostatic discharge Charged device model (CDM), ESD stress voltage

(ESD)

Contact discharge model (IEC) ESD stress voltage on TIP, DET_TRIGGER, RING2_SENSE, SLEEVE_SENSE, RING2, SLEEVE

(1) (2)

(1) (3)

(1)

(1) Electrostatic Discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges

into the device (2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

±2000 V

±500 V

±8000 V

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TS3A227E

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SCDS358B –NOVEMBER 2014–REVISED FEBRUARY 2015

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN MAX UNIT

VDD Power supply voltage range 2.5 4.5 V

VIDigital input voltage range

VIOInput/output voltage range V

SDA, SCL 0 V DET_TRIGGER –2.2 V RING2_SENSE, SLEEVE_SENSE, RING2,

SLEEVE, GND_SENSE, MICP

0 3.3

(1)

TIP –3 V

VOOutput voltage range INT, MIC_PRESENT 0 V

VIHInput logic high

VILInput logic low

Operating ambient temperature –40 85 °C

SDA, SCL 1.2 V DET_TRIGGER 0.65 × V

SDA, SCL 0 0.4 V DET_TRIGGER 0 0.4 × V

DD DD

and VDD

DD DD DD

(1) This rating is exclusive and the voltage on the pins must not exceed either 3.3 and VDD. E.g. if VDD= 4.5 V the voltage on the pin must

not exceed 3.3 V and if VDDis = 2.5 V the voltage on the pin must not exceed 2.5 V.

V V

V V V

7.4 Thermal Information

TS3A227E TS3A227E

THERMAL METRIC

θJA

θJC(top)

θJB

θJC(bot)

Junction-to-ambient thermal resistance 45.9 77.9 Junction-to-case (top) thermal resistance 52.6 0.6 Junction-to-board thermal resistance 21.2 12.5 Junction-to-top characterization parameter 0.9 2.3 Junction-to-board characterization parameter 21.2 12.5 Junction-to-case (bottom) thermal resistance 4.3 -

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(1)

RTE YFF UNIT

16 PINS 16 PINS

°C/W

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SCDS358B –NOVEMBER 2014–REVISED FEBRUARY 2015

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7.5 Electrical Characteristics

Unless otherwise noted the specification applies over the VDD and ambient operating temperature range.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SUPPLY VOLTAGE

VDD Supplyvoltage 2.5 3.3 4.5 V

No accessory inserted. I2C bus inactive VDD= 2.5 V to 4.5 V

Manual switch control = ’1’ , I2C bus inactive, VDD= 2.5 V to 4.5 V, Depletion FETs on

Manual switch control = ’1’ , I2C bus inactive, VDD= 2.5 V to 4.5 V Depletion FETs off

3-pole accessory inserted.

Quiescent current

I2C bus inactive VDD= 2.5 V to 4.5 V

3-pole accessory inserted. I2C bus inactive,

(1)

, FM Support = ’0’

(1)

FM Support = ’1’

VDD= 2.5 V to 4.5 V 4-pole Accessory inserted.

I2C bus inactive,

(1)

VDD= 2.5 V to 4.5 V

4-pole Accessory inserted.

DD_1.8

Quiescent current addition from using a

1.8 V I2C bus.

(2)

KP detection enabled I2C bus inactive,

No accessory inserted. I2C bus inactive at 1.8 V,

VDD= 2.5 V to 4.5 V

(1)

VDD= 2.5 V to 4.5 V

SWITCH RESISTANCE

RING2 GNDFET on resistance (DSBGA

R2GNDFT

SLVGNDFT

Package) RING2 GNDFET on resistance (QFN

Package) SLEEVE GNDFET on resistance (DSBGA

Package) SLEEVE GNDFET on resistance (QFN

VDD= 3.3 V, V I

= 75 mA

GNDA

GND

= 0V,

Package)

S3PS

S3PR

S3GS

S3GR

R2DFET

SLVDFET

S3PS on resistance VDD= 3.3 V, 3 6.5

S3PR on resistance 3 6.5

SLEEVE_SENSE/RING2_SENSE

= ±10 mA

MICP

S3GS on resistance VDD= 3.3 V, 0.5 1

S3GR on resistance 0.5 1

SLEEVE_SENSE/RING2_SENSE

GND_SENSE

= ±75 mA Switch 1 on resistance 15 30 Switch 2 on resistance 15 30 RING2 depletion FET on resistance 75 150

VDD= 3.3 V, I

GND

= 10 mA

SLEEVE depletion FET on resistance 75 150

SWITCH LEAKAGE CURRENT

RING2 pin off leakage 1 SLEEVE pin off leakage 1

OFF

RING2_SENSE pin off leakage 1 SLEEVE_SENSE pin off leakage 1

VIN= 0 V to 3.3 V, VDD= 3.3 V µA

MICP pin off leakage 1 GND_SENSE pin off leakage 1

S2PS, S3PR, S3GS, S3GR on leakage V

SLEEVE/RING2

= 0V, VDD= 3.3 V 1 µA

(1) The I2C bus is inactive if both the SDA and SCL lines are tied to VDD. (2) If the I2C bus is operating at 1.8 V the I (3) The I2C bus is inactive if both the SDA and SCL lines are tied to 1.8 V.

current number will be in addition to the other current consumption numbers specified.

DD_1.8

(3)

= 0 V to 2.7 V, Ω

(1)

0.5 10 µA

7 15 µA

20 40 µA

11 20 µA

25 45 µA

25 40 µA

30 45 µA

1 8 µA

40 85

60 95

40 85

60 95

mΩ

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SCDS358B –NOVEMBER 2014–REVISED FEBRUARY 2015

Electrical Characteristics (continued)

Unless otherwise noted the specification applies over the VDD and ambient operating temperature range.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SWITCH TIMING

VDD= 2.5 V, 3.3 V, 4.5 V, RL= 300 Ω, CL= 50 pF V

SLEEVE_SENSE/RING2_SENSE

3.3 V (VDD= 3.3 V, VDD= 4.5 V)

= 2.5 V (VDD= 2.5 V),

VDD= 2.5 V, 3.3 V, 4.5 V RPU= 1500 Ω, CL= 50 pF VPU= 2.5 V (VDD= 2.5 V),

3.3 V (VDD= 3.3 V, VDD= 4.5 V) VDD= 2.5 V, 3.3 V, 4.5 V

RPU= 1500 Ω, CL= 50 pF VPU= 2.5 V (VDD= 2.5 V),

3.3 V (VDD= 3.3 V, VDD= 4.5 V) VDD= 2.5 V, 3.3 V, 4.5 V

RL= 300 Ω, CL= 50 pF V

SLEEVE_SENSE/RING2_SENSE

3.3 V (VDD= 3.3 V, VDD= 4.5 V)

= 2.5 V (VDD= 2.5 V),

VDD= 2.5 V, 3.3 V, 4.5 V RPU= 1500 Ω, CL= 50 pF VPU= 2.5 V (VDD= 2.5 V),

3.3 V (VDD= 3.3 V, VDD= 4.5 V) VDD= 2.5 V, 3.3 V, 4.5 V

RPU= 1500 Ω, CL= 50 pF VPU= 2.5 V (VDD= 2.5 V),

3.3 V (VDD= 3.3 V, VDD= 4.5 V)

VDD= 3.3 V, IOL= 10 mA

= 3 mA 0 0.4

OLMAX

SDA, SCL 1.2 V DET_TRIGGER V

VDDx

0.65 SDA, SCL 0 0.4 DET_TRIGGER 0 VDDx 0.4

VDD= 3.3 V, I

/DET_TRIGGER

= 1 µA 0.5 1 1.85 MΩ

OFF

DIGITAL I/O

PU/DT

Turn off time for S3PS, S3PR, S3GS, S3GR

Turn off time for S1, S2, RING2 GNDFET, SLEEVE GNDFET

Turn off time for RING2 DFET and SLEEVE DFET

Turn on time for S3PS, S3PR, S3GS, S3GR

Turn on time for S1, S2, RING2 GNDFET, SLEEVE GNDFET

Turn on time for RING2 DFET and SLEEVE DFET

MIC_PRESENT low level output voltage 0 0.4 INT low level output voltage 0 0.4 V SDA low level output voltage VDD= 3.3 V, I

Input logic high V

Input logic low

Internal DET_TRIGGER pull-up resistance

TS3A227E

5 µs

500 µs

1 µs

35 µs

1 µs

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SCDS358B –NOVEMBER 2014–REVISED FEBRUARY 2015

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Electrical Characteristics (continued)

Unless otherwise noted the specification applies over the VDD and ambient operating temperature range.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DYNAMIC CHARACTERISTICS

PSR

217

PSR

20k

ISO

SEP

BW Bandwidth through GNDFETs VIN= 60 mVPP, I THD

200

THD

500

SNR –90 –110 dB

DET

power-up

REMOVAL

Power supply rejection –85 –110 dB

SLEEVE_SENSE or RING2_SENSE to MICP Isolation

SLEEVE_SENSE to RING2_SENSE Separation

MICP to RING2_SENSE or SLEEVE_SENSE total harmonic distortion

MICP to RING2_SENSE or SLEEVE_SENSE signal to noise ratio

Detection sequence duration high to low and INT transition from high to low. 175 210 ms

Power up time Power-up time 20 25 ms

Removal wait period low to high and RING2/SLEEVE DFETs turning 50 65 ms

VDD= 3.3 V ± 200 mVPP, f = 217 Hz, RLat RING2= 50 Ω

VDD= 3.3 V ± 200 mVPP, f = 1 kHz, RLat RING2= 50 Ω

VDD= 3.3 V ± 200 mVPP, f = 20 kHz, RLat RING2= 50 Ω

VIN= 200 mVPP, f = 20 Hz – 20 kHz, RL= 50 Ω –90 dB

VIN= 200 mVPP, f = 20 Hz – 20 kHz, RL= 50 Ω –75 dB

= 10 mA 120 150 MHz

BIAS

VIN= 1.5 V + 200 mVPP, f = 20 Hz – 20 kHz, RS= 600 Ω, RL= 600 Ω

VIN= 1.5 V + 500 mVPP, f = 20 Hz – 20 kHz, RS= 600 Ω, RL= 600 Ω

VIN= 1 V RS= 600 Ω, RL= 600 Ω

Time between DET_TRIGGER transition from Default 90 ms insertion debounce.

Time from VDD> 2.5 V till I2C communication is ready

Time between DET_TRIGGER transition from on

, f = 20 Hz – 20 kHz,

RMS

–95 –120

–70 –90

0.003 %

0.002%

7.6 I2C Interface Timing Characteristics

Unless otherwise noted the specification applies over the VDD and ambient operating temperature range

STANDARD MODE FAST MODE I2C

I2C BUS BUS

MIN MAX MIN MAX

20 + 0.1

3.45 0.3 0.9 µs

scl

sch

scl

sds

sdh

icr

icf

ocf

buf

sts

sth

sps

vd(data)

vd(ack)

PARAMETER

I2C clock frequency 0 100 0 400 kHz I2C clock high time 4 0.6 µs I2C clock low time 4.7 1.3 µs I2C spike time 50 50 ns I2C serial data setup time 250 100 ns I2C serial data hold time 0 0 ns I2C input rise time 1000 21 300 ns I2C input fall time 300 21 300 ns

I2C output fall time; 10 pF to 400 pF bus 300 300 µs I2C bus free time between Stop and Start 4.7 1.3 µs

I2C Start or repeater Start condition setup time 4.7 0.6 µs I2C Start or repeater Start condition hold time 4 0.6 µs I2C Stop condition setup time 4 0.6 µs Valid data time; SCL low to SDA output valid 3.45 0.3 0.9 µs Valid data time of ACK condition; ACK signal from SCL low to SDA

(out) low I2C bus capacitive loading 0 400 0 400 pF

UNIT

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DET_TRIGGER

INT

Insertion

de-bounce time (90 ms default )

Accessory detection time

(A) (B) (D) (E) (F)

Removal wait time

MIC_PRESENT

High

(C)

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7.7 Timing Diagrams

TS3A227E

SCDS358B –NOVEMBER 2014–REVISED FEBRUARY 2015

A. (This is the point that DET_TRIGGER has stopped glitching and is fully low. The de-bounce time of 90 ms starts from

the point that the pin is constantly below the VILlevel. Any time the DET_TRIGGER pin cross the VIHlevel the de-

bounce timer will restart. B. Point B is the end of the insertion de-bounce time and the beginning of accessory detection. C. Detection has completed at this point. The switches will be routed before the INT pin is pulled low. D. INT is cleared after the host reads the interrupt register. E. The headset is removed here. The switch states will change immediately and INT will be pulled low. F. After a 50 ms removal de-bounce timer the TS3A227E will go back into sleep mode if manual switch control is not

enabled

Figure 1. 3-Pole Accessory

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DET_TRIGGER

INT

Insertion

de-bounce time (90 ms default )

Accessory detection time

(A) (B) (D) (E) (F)

Removal wait time

MIC_PRESENT

High

(C)

TS3A227E

SCDS358B –NOVEMBER 2014–REVISED FEBRUARY 2015

Timing Diagrams (continued)

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A. This is the point that DET_TRIGGER has stopped glitching and is fully low. The de-bounce time of 90 ms starts from

the point that the pin is constantly below the VILlevel. Any time the DET_TRIGGER pin cross the VIH level the de-

low. D. INT is cleared after the host reads the interrupt register. E. The headset is removed here. The switch states will change immediately and INT will be pulled low. The

MIC_PRESENT pin will be released. F. After a 50 ms removal de-bounce timer the TS3A227E will go back into sleep mode if manual switch control is not

enabled

Figure 2. 4-Pole Accessory

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DET_TRIGGER

INT

Insertion

de-bounce time (90 ms default )

Accessory detection time

(A) (B) (C) (D) (E) ( F)

Removal wait time

MIC_PRESENT

High

TS3A227E

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SCDS358B –NOVEMBER 2014–REVISED FEBRUARY 2015

Timing Diagrams (continued)

7.7.1 Removal

A removal event will interrupt any on-going process in the TS3A227E. The following diagram depicts how the device “jumps” during a removal.

If the removal event occurs during the insertion de-bounce period the TS3A227E will jump to the (A) point of the diagram depicted by the green arrow and line.

Any time after point (B) has been reached and the accessory is removed the device jumps to point (E), which includes key press detection. Under Manual Switch Control the switch states will not change.

Figure 3. Removal Timing During Insertion

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GND

R2/SLV DFET

SLEEVE/RING2

Channel ON RON= V

SLEEVE/RING2

/ I

GND

GNDA

R2/SLV GNDFET

SLEEVE/RING2

Channel ON RON= V

SLEEVE/RING2

/ I

GNDA

Frequency (Hz)

THD (%)

10 2030 50 100 200 5001000 10000 100000

0.0005

0.001

0.0015

0.002

0.0025

0.003

0.0035

D001

200 mVpp 500 mVpp

TS3A227E

SCDS358B –NOVEMBER 2014–REVISED FEBRUARY 2015

7.8 Typical Characteristics

8 Parameter Measurement Information

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Figure 4. S3PX THD

Figure 5. RING2/SLEEVE GNDFET On Resistance Measurement

Figure 6. RING2/SLEEVE DFET On Resistance Measurement

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OUT

Switch

Channel OFF

RING 2_SENSE/SLEEVE_ SENSE

S3PS/R S3GS/R

MICP/GND_SENSE

Channel ON RON= V

MICP/GND_SENSE

/ I

RING2_SENSE /SLEEVE_SENSE

GND

S1/S2

MICP/GND_SENSE

Channel ON RON= V

MICP/GND_SENSE

/ I

GND

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TS3A227E

SCDS358B –NOVEMBER 2014–REVISED FEBRUARY 2015

Parameter Measurement Information (continued)

Figure 7. S1/S2 On Resistance Measurement

Figure 8. S3PS, S3PR, S3GS, S3GR On Resistance Measurement

Figure 9. Switch Off Leakage Current

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Switch

Network Analyzer

Source Signal

50 Ω

Channel Off

MICP/GND_SENSE

SLEEVE_SENSE/RING2 _SENSE

50 Ω

Switch

Channel ON

3.3 V ± 200 mV

Reference

Test

Source Generator

Source Signal

50 Ω

OUT

Switch

Channel ON

Leakage

TS3A227E

SCDS358B –NOVEMBER 2014–REVISED FEBRUARY 2015

Parameter Measurement Information (continued)

Figure 10. Switch On Leakage Current

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Figure 11. Power Supply Rejection Ratio (PSRR)

Figure 12. Switch Off Isolation

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Audio Analyzer

Source Signal

600 Ω

MICP

SLEEVE_SENSE/RING2_SENSE

Switch

Network Analyzer

Source Signal

50 Ω

MICP

SLEEVE_SENSE

50 Ω

GND_SENSE V

RING2_SENSE

Switches

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TS3A227E

SCDS358B –NOVEMBER 2014–REVISED FEBRUARY 2015

Parameter Measurement Information (continued)

Figure 13. Channel Separation

Figure 14. Total Harmonic Distortion (THD) and SNR

Product Folder Links: TS3A227E

Digital

Core

SDA

SCL

TEST

SCL

TEST

OFF

TEST

SCL

TEST

90 %

10 %

OFF

MICP/GND _SENSE

Digital

Core

SDA

SCL

TEST

TS3A227E

SCDS358B –NOVEMBER 2014–REVISED FEBRUARY 2015

Parameter Measurement Information (continued)

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Figure 15. S3 t

OFF/tO

Figure 16. S1, S2, GNDFET and DFET tON/t

Product Folder Links: TS3A227E

OFF

TS3A227E

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SCDS358B –NOVEMBER 2014–REVISED FEBRUARY 2015

9 Detailed Description

9.1 Overview

The TS3A227E is an autonomous audio accessory switch with adjustable de-bounce settings, ultra-low RON ground FETs, depletion FETs and manual I2C control.

The detection sequence is initiated via the external DET_TRIGGER pin or via I2C command. The device incorporates internal de-bounce timings that remove the need for external RC circuits, reducing cost and overall PCB footprint. Additionally all switches of the TS3A227E and the internal de-bounce timings can be controlled through I2C.

Before an insertion, TS3A227E isolates the MICBIAS voltage output from the audio jack to remove click/pop noise that can be created during an insertion event. In addition the device also includes depletion FETs to ground the accessory SLEEVE and RING2 pins when VDD is not powered. This removes the humming noise that can be created when plugging an accessory into and unpowered system.

The TS3A227E detects the presence and configuration of the microphone in an attached headset upon insertion. Upon detection of a microphone the TS3A227E automatically connects a system analog microphone pin (MICP) to the appropriate audio jack connection. The device also automatically routes the device GNDA pin to the headset ground. After a 4-pole headset insertion the host can enable the Key Press detection feature of the TS3A227E.

The device also features an ultra-low power sleep mode to conserve battery life when an accessory is not inserted.

For FM transmission the ground FETs of the device can be used as an FM transmission path by placing the FM receiver and matching network on the GNDA pin. The FM support bit must be set to ‘1’ through I2C for FM transmission to pass.

Product Folder Links: TS3A227E

BATTERY

DIGITAL BASEBAND

MIC_PRESENT

SCL

SDA

INTB

VDD

MICROPHONE

AMPLIFIER

EMI

FILTER

EMI

FILTER

RING2_SENSE

SLEEVE_SENSE

TIP

DET_TRIGGER

RING2

SLEEVE

MICP

GND_SENSE

AUDIO

AMPLIFIER

Mic Switch

Matrix

ESD Protection

Depletion FETs

GND Switch

Matrix

TS3A227 E

Detection

Circuitry

Digital interface

control

GND GNDA

Receiver

S1 and S2

TS3A227E

SCDS358B –NOVEMBER 2014–REVISED FEBRUARY 2015

9.2 Functional Block Diagram

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Product Folder Links: TS3A227E

R M GL

16-2 kΩ

16- 2 kΩ

600-4kΩ

OMTP

4-pole TRRS

Tip Ring1 SleeveRing2

R G ML

16-2 kΩ

16- 2 kΩ

600-4kΩ

Standard

Tip Ring Sleeve

3-pole TRS

R GL

16-2 kΩ

16- 2 kΩ

TRS

TS3A227E

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SCDS358B –NOVEMBER 2014–REVISED FEBRUARY 2015

9.3 Feature Description

9.3.1 Accessory Configuration Detection

There are currently two difference configurations for headsets with microphones as shown in Table 1. Many codecs requires that the system designer make a tough decision via a hardware connection which headset they would like to support. This is done by directly connecting the microphone bias and the ground connections to the sleeve and ring2 pins of the audio jack. For the end user this leaves a headset standard as fully unsupported.

Table 1. Two Difference Configurations for Headsets

PHYSICAL CONNECTOR INTERNAL IMPEDANCE NETWORK PIN NAME CONFIGURATION

Tip Audio Left Ring Audio Right

Sleeve Ground

Tip Audio Left Ring1 Audio Right Ring2 Ground

Sleeve Microphone

Tip Audio Left Ring1 Audio Right Ring2 Microphone

Sleeve Ground

The TS3A227E fills this system gap by detecting the presence and location of the microphone and automatically routing the MICBIAS and ground lines to support each headset. This enhances the overall user experience by allowing headsets from all manufacturers.

9.3.2 Optional Manual I2C Control

The TS3227E also features optional manual I2C control for enhanced system flexibility. This allows the system designer to manually control the switches and de-bounce settings at their discretion enabling the TS3A227E to adapt to unique use cases.

This is an optional feature that does not need to be used for the device to operate autonomously.

9.3.3 Adjustable De-bounce Timings

The TS3A227E features manual control of the insertion de-bounce timer with selectable values. The default insertion de-bounce timer is 90 ms.

This eliminates the need for external RC components which reduces BOM cost, the PCB footprint of the external RC components. Further information on how to select an appropriate de-bounce timer can be found in the application and implementation section.

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+ 42 hidden pages

Texas Instruments TS3A227E Datasheet

1 Features 3 Description

2 Applications

4 Simplified Schematic

Table of Contents

5 Revision History

6 Pin Configuration and Functions

7 Specifications

7.1 Absolute Maximum Ratings

7.2 ESD Ratings

7.3 Recommended Operating Conditions

7.4 Thermal Information

7.5 Electrical Characteristics

7.6 I2C Interface Timing Characteristics

7.7 Timing Diagrams

7.7.1 Removal

7.8 Typical Characteristics

8 Parameter Measurement Information

9 Detailed Description

9.1 Overview

9.2 Functional Block Diagram

9.3 Feature Description

9.3.1 Accessory Configuration Detection

9.3.2 Optional Manual I2C Control

9.3.3 Adjustable De-bounce Timings