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324
5
DBV PACKAGE
(TOP VIEW)
1IN
GND
EN
OUT
NR
Fixed Option
324
6
DBV PACKAGE
(TOP VIEW)
1
IN
GND
EN
OUT
NR
5
FB
Adjustable Option
TPS79328
RIPPLE REJECTION
vs
FREQUENCY
IN
EN
OUT
NR
GND
YEQ
PACKAGE
(TOP VIEW)
10 100 1 k 10 k
10
40
80
100 k 1 M 10 M
Ripple Rejection (dB)
Frequency (Hz)
I
OUT
= 10 mA
50
0
VIN = 3.8 V
C
OUT
= 10 µF
CNR = 0.01 µF
I
OUT
= 200 mA
20
30
60
70
90
100
A3 A1
C3 C1
B2
0
0.05
0.10
0.15
0.20
0.25
0.30
100 1 k 10 k 100 k
Frequency (Hz)
I
OUT
= 1 mA
VIN = 3.8 V
C
OUT
= 2.2 µF
C
NR
= 0.1 µF
I
OUT
= 200 mA
TPS79328
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
Output Spectral Noise Density (µV/√Hz)
TPS79301, TPS79318
TPS79325, TPS79328, TPS793285
TPS79330, TPS79333, TPS793475
SLVS348H – JULY 2001 – REVISED OCTOBER 2004
ULTRALOW-NOISE, HIGH PSRR, FAST RF 200-mA LOW-DROPOUT LINEAR
REGULATORS IN NanoStar™ WAFER CHIP SCALE AND SOT23
FEATURES DESCRIPTION
• 200-mA RF Low-Dropout Regulator
With Enable
• Available in 1.8-V, 2.5-V, 2.8-V, 2.85-V, 3-V,
3.3-V, 4.75-V, and Adjustable (1.22-V to 5.5-V)
• High PSRR (70 dB at 10 kHz)
• Ultralow-Noise (32 µV
, TPS79328)
RMS
• Fast Start-Up Time (50 µs)
• Stable With a 2.2-µF Ceramic Capacitor
• Excellent Load/Line Transient Response
• Very Low Dropout Voltage (112 mV at Full
Load, TPS79330)
• 5- and 6-Pin SOT23 (DBV) and NanoStar Wafer
Chip Scale (YEQ) Packages
APPLICATIONS
• RF: VCOs, Receivers, ADCs is reduced to less than 1 µA. The TPS79328 exhibits
• Audio
• Cellular and Cordless Telephones
• Bluetooth™, Wireless LAN
• Handheld Organizers, PDAs
The TPS793xx family of low-dropout (LDO)
low-power linear voltage regulators features high
power-supply rejection ratio (PSRR), ultralow-noise,
fast start-up, and excellent line and load transient
responses in NanoStar wafer chip scale and SOT23
packages. NanoStar packaging gives an ultrasmall
footprint as well as an ultralow profile and package
weight, making it ideal for portable applications such
as handsets and PDAs. Each device in the family is
stable, with a small 2.2-µF ceramic capacitor on the
output. The TPS793xx family uses an advanced,
proprietary BiCMOS fabrication process to yield extremely low dropout voltages (e.g., 112 mV at
200 mA, TPS79330). Each device achieves fast
start-up times (approximately 50 µs with a 0.001-µF
bypass capacitor) while consuming very low quiescent current (170 µA typical). Moreover, when the
device is placed in standby mode, the supply current
approximately 32 µV
of output voltage noise at
RMS
2.8-V output with a 0.1-µF bypass capacitor. Applications with analog components that are
noise-sensitive, such as portable RF electronics,
benefit from the high PSRR and low-noise features
as well as the fast response time.
Bluetooth is a trademark of Bluetooth Sig, Inc.
NanoStar is a trademark of Texas Instruments.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily
include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Figure 1.
Copyright © 2001–2004, Texas Instruments Incorporated
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TPS79301, TPS79318
TPS79325, TPS79328, TPS793285
TPS79330, TPS79333, TPS793475
SLVS348H – JULY 2001 – REVISED OCTOBER 2004
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
AVAILABLE OPTIONS
PRODUCT VOLTAGE PACKAGE T
TPS79301 1.22 V to 5.5 V SOT23 (DBV) PGVI TPS79301DBVR
TPS79318 1.8 V
TPS79325 2.5 V
TPS79328 2.8 V
TPS793285 2.85 V
TPS79330 3 V
TPS79333 3.3 V SOT23 (DBV) PHUI TPS79333DBVR
TPS793475 4.75 V SOT23 (DBV) PHJI TPS793475DBVR
(1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet.
(2) DBV R indicates tape and reel of 3000 parts. YEQ R indicates tape and reel of 3000 parts. YEQ T indicates tape and reel of 250 parts.
SOT23 (DBV) PHHI TPS79318DBVR
CSP (YEQ) E3 TPS79318YEQ
SOT23 (DBV) PGWI TPS79325DBVR
CSP (YEQ) E4 TPS79325YEQ
SOT23 (DBV) PGXI TPS79328DBVR
CSP (YEQ) -40 ° C to +125 ° C E2 TPS79328YEQ
SOT23 (DBV) PHII TPS793285DBVR
CSP (YEQ) E5 TPS793285YEQ
SOT23 (DBV) PGYI TPS79330DBVR
CSP (YEQ) E6 TPS79330YEQ
(1) (2)
J
SYMBOL PART NUMBER
ABSOLUTE MAXIMUM RATINGS
over operating temperature range (unless otherwise noted)
VINrange -0.3 V to 6 V
V
range -0.3 V to VIN+ 0.3 V
EN
V
range -0.3 V to 6 V
OUT
Peak output current Internally limited
ESD rating, HBM 2 kV
ESD rating, CDM 500 V
Continuous total power dissipation See Dissipation Ratings Table
Junction temperature range, DBV package -40 ° C to 150 ° C
Junction temperature range, YEQ package -40 ° C to 125 ° C
Storage temperature range, T
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
stg
(1)
UNIT
-65 ° C to 150 ° C
2
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TPS79301, TPS79318
TPS79325, TPS79328, TPS793285
TPS79330, TPS79333, TPS793475
SLVS348H – JULY 2001 – REVISED OCTOBER 2004
DISSIPATION RATINGS TABLE
BOARD PACKAGE R
(1)
Low-K
(2)
High-K
(1)
Low-K
(2)
High-K
DBV 65 ° C/W 255 ° C/W 3.9 mW/ ° C 390 mW 215 mW 155 mW
DBV 65 ° C/W 180 ° C/W 5.6 mW/ ° C 560 mW 310 mW 225 mW
YEQ 27 ° C/W 255 ° C/W 3.9 mW/ ° C 390 mW 215 mW 155 mW
YEQ 27 ° C/W 190 ° C/W 5.3 mW/ ° C 530 mW 296 mW 216 mW
θ JC
R
θ JA
ABOVE TA= 25 ° C RATING RATING RATING
(1) The JEDEC low-K (1s) board design used to derive this data was a 3-inch x 3-inch, two layer board with 2 ounce copper traces on top
of the board.
(2) The JEDEC high-K (2s2p) board design used to derive this data was a 3-inch x 3-inch, multilayer board with 1 ounce internal power and
ground planes and 2 ounce copper traces on top and bottom of the board.
ELECTRICAL CHARACTERISTICS
DERATING FACTOR POWER POWER POWER
over recommended operating temperature range TJ= -40 to 125 ° C, V
C
= 10 µF, C
OUT
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VINInput voltage
I
Continuous output current 0 200 mA
OUT
V
Internal reference (TPS79301) 1.201 1.225 1.250 V
FB
Output voltage range (TPS79301) V
Output voltage TPS793285 0 µA < I
Line regulation ( ∆ V
Load regulation ( ∆ V
Dropout voltage
(V
= V
IN
OUT(nom)
Output current limit V
GND pin current 0 µA < I
Shutdown current
FB pin current V
Power-supply ripple rejection TPS79328 dB
Output noise voltage (TPS79328) µV
= 0.01 µF (unless otherwise noted). Typical values are at 25 ° C.
NR
(1)
TPS79318 0 µA < I
TPS79325 0 µA < I
TPS79328 0 µA < I
TPS79330 0 µA < I
TPS79333 0 µA ≤ I
TPS793475 0 µA < I
%/ ∆ VIN)
OUT
OUT
(2)
- 0.1V)
(3)
(1)
%/ ∆ I
) 0 µA < I
OUT
TPS79328 I
TPS793285 I
TPS79330 I
TPS79333 I
TPS793475 I
V
OUT
OUT
OUT
OUT
OUT
OUT
OUT
V
EN
FB
< 200 mA, 2.8 V < VIN< 5.5 V 1.764 1.8 1.836 V
OUT
< 200 mA, 3.5 V < VIN< 5.5 V 2.45 2.5 2.55 V
OUT
< 200 mA, 3.8 V < VIN< 5.5 V 2.744 2.8 2.856 V
OUT
< 200 mA, 3.85 V < VIN< 5.5 V 2.793 2.85 2.907 V
OUT
< 200 mA, 4 V < VIN< 5.5 V 2.94 3 3.06 V
OUT
< 200 mA, 4.3 V < VIN< 5.5 V 3.234 3.3 3.366 V
OUT
< 200 mA, 5.25 V < VIN< 5.5 V 4.655 4.75 4.845 V
OUT
+ 1 V < VIN≤ 5.5 V 0.05 0.12 %/V
< 200 mA, TJ= 25 ° C 5 mV
OUT
= 200 mA 120 200
= 200 mA 120 200
= 200 mA 112 200 mV
= 200 mA 102 180
= 200 mA 77 125
= 0 V 285 600 mA
< 200 mA 170 220 µA
OUT
= 0 V, 2.7 V < VIN< 5.5 V 0.07 1 µA
= 1.8 V 1 µA
f = 100 Hz, TJ= 25 ° C, I
f = 100 Hz, TJ= 25 ° C, I
f = 10 kHz, TJ= 25 ° C, I
f = 100 kHz, TJ= 25 ° C, I
BW = 200 Hz to 100 kHz,
I
= 200 mA
OUT
EN
OUT
OUT
OUT
OUT
C
NR
C
NR
C
NR
C
NR
TA≤ 25 ° C TA= 70 ° C TA= 85 ° C
= VIN, V
= V
IN
OUT(nom)
+ 1 V
(1)
, I
OUT
2.7 5.5 V
FB
= 10 mA 70
= 200 mA 68
= 200 mA 70
= 200 mA 43
= 0.001 µF 55
= 0.0047 µF 36
= 0.01 µF 33
= 0.1 µF 32
= 1 mA,
5.5 - V
DO
V
RMS
(1) Minimum VINis 2.7 V or V
(2) Dropout is not measured for the TPS79318 and TPS79325 since minimum VIN= 2.7 V.
(3) For adjustable versions, this applies only after VINis applied; then V
+ VDO, whichever is greater.
OUT
transitions high to low.
EN
3
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TPS79301, TPS79318
TPS79325, TPS79328, TPS793285
TPS79330, TPS79333, TPS793475
SLVS348H – JULY 2001 – REVISED OCTOBER 2004
ELECTRICAL CHARACTERISTICS (continued)
over recommended operating temperature range TJ= -40 to 125 ° C, V
C
= 10 µF, C
OUT
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Time, start-up (TPS79328) RL= 14 Ω , C
High level enable input voltage 2.7 V < VIN< 5.5 V 1.7 V
Low level enable input voltage 2.7 V < VIN< 5.5 V 0 0.7 V
EN pin current V
UVLO threshold V
UVLO hysteresis 100 mV
= 0.01 µF (unless otherwise noted). Typical values are at 25 ° C.
NR
= 1 µF C
OUT
= 0 -1 1 µA
EN
rising 2.25 2.65 V
CC
= VIN, V
EN
C
= 0.001 µF 50
NR
= 0.0047 µF 70 µs
NR
C
= 0.01 µF 100
NR
= V
IN
OUT(nom)
+ 1 V, I
= 1 mA,
OUT
IN
V
4
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ADJUSTABLE VERSION
_
+
Thermal
Shutdown
Bandgap
Reference
1.22V
Current
Sense
R2
GND
EN
SHUTDOWN
V
ref
UVLO
ILIM
External to
the Device
R1
UVLO
2.45V
250 kΩ
NR
FB
59 k
QuickStart
OUTIN
IN
_
+
Thermal
Shutdown
Current
Sense
R1
R2
GND
EN
SHUTDOWN
V
ref
UVLO
ILIM
250 kΩ
NR
QuickStart
Bandgap
Reference
1.22V
UVLO
2.45V
R2 = 40 kΩ
IN
IN OUT
TPS79301, TPS79318
TPS79325, TPS79328, TPS793285
TPS79330, TPS79333, TPS793475
SLVS348H – JULY 2001 – REVISED OCTOBER 2004
FUNCTIONAL BLOCK DIAGRAMS
FIXED VERSION
Terminal Functions
TERMINAL
NAME
GND 2 2 A1 Regulator ground
OUT 6 5 C1 Output of the regulator.
SOT23 SOT23 WCSP
ADJ FIXED FIXED
NR 4 4 B2
EN 3 3 A3
FB 5 N/A N/A This terminal is the feedback input voltage for the adjustable device.
IN 1 1 C3 Unregulated input to the device.
Connecting an external capacitor to this pin bypasses noise generated by the internal bandgap.
This improves power-supply rejection and reduces output noise.
Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into
shutdown mode. EN can be connected to IN if not used.
DESCRIPTION
5
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2.795
2.796
2.797
2.798
2.799
2.800
2.801
2.802
2.803
2.804
2.805
0 50 100 150 200
I
OUT
(mA)
VIN = 3.8 V
C
OUT
= 10 µF
TJ = 25°C
V
OUT
(V)
0
50
100
150
200
250
−40−25−10 5 20 35 50 65 80 95 110125
T
J
(°C)
I
OUT
= 1 mA
VIN = 3.8 V
C
OUT
= 10 µF
I
OUT
= 200 mA
I
GND
(µA)
2.775
2.780
2.785
2.790
2.795
2.800
2.805
−40−25−10 5 20 35 50 65 80 95 110 125
T
J
(°C)
I
OUT
= 200 mA
I
OUT
= 1 mA
VIN = 3.8 V
C
OUT
= 10 µF
V
OUT
(V)
0
0.05
0.10
0.15
0.20
0.25
0.30
100 1 k 10 k 100 k
Frequency (Hz)
I
OUT
= 1 mA
VIN = 3.8 V
C
OUT
= 2.2 µF
C
NR
= 0.1 µF
I
OUT
= 200 mA
Output Spectral Noise Density (µV/√Hz)
0
0.05
0.10
0.15
0.20
0.25
0.30
100 1 k 10 k 100 k
Frequency (Hz)
I
OUT
= 1 mA
I
OUT
= 200 mA
VIN = 3.8 V
C
OUT
= 10 µF
C
NR
= 0.1 µF
Output Spectral Noise Density (µV/√Hz)
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
100 1 k 10 k 100 k
Frequency (Hz)
VIN = 3.8 V
I
OUT
= 200 mA
C
OUT
= 10 µF
CNR = 0.1 µF
CNR = 0.001 µF
CNR = 0.0047 µF
CNR = 0.01 µF
Output Spectral Noise Density (µV/√Hz)
100 1 M10 1 k
Frequency (Hz)
10 k 100 k
I
OUT
= 1 mA
0
0.5
1.0
1.5
2.0
2.5
0
I
OUT
= 100 mA
10 M
VIN = 3.8 V
C
OUT
= 10 µF
TJ = 25° C
ZO (Ω)
0
20
40
60
80
100
120
140
160
180
−40−25−10 5 20 35 50 65 80 95 110125
I
OUT
= 200 mA
I
OUT
= 10 mA
VIN = 2.7 V
C
OUT
= 10 µF
T
J
(°C)
V
DO
(mV)
0.001 0.01 0.1
C
NR
(µF)
0
10
20
30
40
50
60
V
OUT
= 2.8 V
I
OUT
= 200 mA
C
OUT
= 10 µF
BW = 100 Hz to 100 kHz
RMS, Output Noise (V
RMS
)
TPS79301, TPS79318
TPS79325, TPS79328, TPS793285
TPS79330, TPS79333, TPS793475
SLVS348H – JULY 2001 – REVISED OCTOBER 2004
TYPICAL CHARACTERISTICS (SOT23 PACKAGE)
TPS79328 TPS79328 TPS79328
OUTPUT VOLTAGE OUTPUT VOLTAGE GROUND CURRENT
OUTPUT CURRENT JUNCTION TEMPERATURE JUNCTION TEMPERATURE
vs vs vs
Figure 2. Figure 3. Figure 4.
TPS79328 OUTPUT SPECTRAL TPS79328 OUTPUT SPECTRAL TPS79328 OUTPUT SPECTRAL
NOISE DENSITY NOISE DENSITY NOISE DENSITY
vs vs vs
FREQUENCY FREQUENCY FREQUENCY
Figure 5. Figure 6. Figure 7.
ROOT MEAN SQUARE OUTPUT TPS79328
NOISE OUTPUT IMPEDANCE DROPOUT VOLTAGE
vs vs vs
C
NR
FREQUENCY JUNCTION TEMPERATURE
6
Figure 8. Figure 9. Figure 10.
www.ti.com
10 100 1 k 10 k
10
40
80
100 k 1 M 10 M
Ripple Rejection (dB)
Frequency (Hz)
I
OUT
= 10 mA
50
0
VIN = 3.8 V
C
OUT
= 10 µF
CNR = 0.01 µF
I
OUT
= 200 mA
20
30
60
70
90
100
10 100 1 k 10 k
20
60
100
100 k 1 M 10 M
Ripple Rejection (dB)
Frequency (Hz)
VIN = 3.8 V
C
OUT
= 2.2 µF
CNR = 0.01 µF
I
OUT
= 10 mA
I
OUT
= 200 mA
40
70
90
30
50
80
10
0
10 100 1 k 10 k
20
60
100
100 k 1 M 10 M
Ripple Rejection (dB)
Frequency (Hz)
VIN = 3.8 V
C
OUT
= 2.2 µF
CNR = 0.1 µF
I
OUT
= 10 mA
I
OUT
= 200 mA
40
70
90
30
50
80
10
0
3
Time (µs)
0 604020 80 100 140120 160 180 200
VIN = 3.8 V
V
OUT
= 2.8 V
I
OUT
= 200 mA
C
OUT
= 2.2 µF
TJ = 25°C
1
2
0
0
2
CNR = 0.0047 µF
CNR = 0.01 µF
4
CNR = 0.001 µF
V
EN
(V)V
OUT
(V)
Time (µs)
0 302010 40 50 7060 80 90 100
I
OUT
= 200 mA
C
OUT
= 2.2 µF
CNR = 0.01 µF
0
-20
3.8
dv
dt
0.4 V
µs
20
4.8
V
IN
(mV) V
OUT
(mV)
Time (µs)
0
0 15010050 200 250 350300 400 450
20
0
−20
100
500
VIN = 3.8 V
C
OUT
= 10 µF
−40
200
300
di
dt
0.02A
µs
1mA
I
OUT
(mA) ∆V
OUT
(mV)
500 mV/div
1s/div
V
IN
V
OUT
V
OUT
= 3 V
RL = 15 Ω
100
50
0 20 40 60 80 100 120
150
200
250
140 160 180 200
0
I
OUT
(mA)
TJ = 125°C
TJ = 25°C
TJ = −55°C
V
DO
(mV)
0
50
100
150
200
2.5 3.0 3.5 4.0 4.5
5.0
V
IN
(V)
I
OUT
= 200 mA
TJ = 25°C
TJ = −40°C
TJ = 125°C
V
DO
(mV)
TYPICAL CHARACTERISTICS (SOT23 PACKAGE) (continued)
TPS79328 TPS79328 TPS79328
RIPPLE REJECTION RIPPLE REJECTION RIPPLE REJECTION
vs vs vs
FREQUENCY FREQUENCY FREQUENCY
Figure 11. Figure 12. Figure 13.
TPS79301, TPS79318
TPS79325, TPS79328, TPS793285
TPS79330, TPS79333, TPS793475
SLVS348H – JULY 2001 – REVISED OCTOBER 2004
TPS79328 OUTPUT VOLTAGE,
ENABLE VOLTAGE
vs TPS79328 TPS79328
TIME (START-UP) LINE TRANSIENT RESPONSE LOAD TRANSIENT RESPONSE
Figure 14. Figure 15. Figure 16.
DROPOUT VOLTAGE DROPOUT VOLTAGE
vs vs
POWER-UP / POWER-DOWN OUTPUT CURRENT INPUT VOLTAGE
TPS79301
Figure 17. Figure 18. Figure 19.
7
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0.01
0.1
10
100
0 0.02 0.04 0.06 0.08 0.20
I
OUT
(A)
1
Region of Instability
Region of Stability
C
OUT
= 2.2 µF
VIN = 5.5 V, V
OUT
≥ 1.5 V
TJ = −40°C to 125°C
ESR, Equivalent Series Resistance (Ω)
0.01
0.1
10
100
0 0.02 0.04 0.06 0.08
0.20
I
OUT
(A)
1
Region of Instability
Region of Stability
C
OUT
= 10 µF
VIN = 5.5 V
TJ = −40°C to 125°C
ESR, Equivalent Series Resistance (Ω)
TPS79301, TPS79318
TPS79325, TPS79328, TPS793285
TPS79330, TPS79333, TPS793475
SLVS348H – JULY 2001 – REVISED OCTOBER 2004
TYPICAL CHARACTERISTICS (SOT23 PACKAGE) (continued)
TYPICAL REGIONS OF STABILITY TYPICAL REGIONS OF STABILITY
EQUIVALENT SERIES RESISTANCE EQUIVALENT SERIES RESISTANCE
(ESR) (ESR)
vs vs
OUTPUT CURRENT OUTPUT CURRENT
Figure 20. Figure 21.
8
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V
IN
V
OUT
TPS793xx
GNDEN NR
IN OUT
V
IN
V
OUT
0.1µF
0.01µF
2.2µF
TPS79301, TPS79318
TPS79325, TPS79328, TPS793285
TPS79330, TPS79333, TPS793475
SLVS348H – JULY 2001 – REVISED OCTOBER 2004
APPLICATION INFORMATION
The TPS793xx family of low-dropout (LDO) regulators has been optimized for use in noise-sensitive
battery-operated equipment. The device features extremely low dropout voltages, high PSRR, ultralow output
noise, low quiescent current (170 µA typically), and enable-input to reduce supply currents to less than 1 µA
when the regulator is turned off.
A typical application circuit is shown in Figure 22 .
Figure 22. Typical Application Circuit
External Capacitor Requirements
A 0.1-µF or larger ceramic input bypass capacitor, connected between IN and GND and located close to the
TPS793xx, is required for stability and improves transient response, noise rejection, and ripple rejection. A
higher-value input capacitor may be necessary if large, fast-rise-time load transients are anticipated or the device
is located several inches from the power source.
Like most low dropout regulators, the TPS793xx requires an output capacitor connected between OUT and GND
to stabilize the internal control loop. The minimum recommended capacitance is 2.2 µF. Any 2.2-µF or larger
ceramic capacitor is suitable, provided the capacitance does not vary significantly over temperature. If load
current is not expected to exceed 100 mA, a 1.0-µF ceramic capacitor can be used.
The internal voltage reference is a key source of noise in an LDO regulator. The TPS793xx has an NR pin which
is connected to the voltage reference through a 250-k Ω internal resistor. The 250-k Ω internal resistor, in
conjunction with an external bypass capacitor connected to the NR pin, creates a low pass filter to reduce the
voltage reference noise and, therefore, the noise at the regulator output. In order for the regulator to operate
properly, the current flow out of the NR pin must be at a minimum, because any leakage current creates an IR
drop across the internal resistor thus creating an output error. Therefore, the bypass capacitor must have
minimal leakage current. The bypass capacitor should be no more than 0.1-µF to ensure that it is fully charged
during the quickstart time provided by the internal switch shown in the Functional Block Diagrams
As an example, the TPS79328 exhibits only 32 µV
of output voltage noise using a 0.1-µF ceramic bypass
RMS
capacitor and a 2.2-µF ceramic output capacitor. Note that the output starts up slower as the bypass capacitance
increases due to the RC time constant at the NR pin that is created by the internal 250-k Ω resistor and external
capacitor.
Board Layout Recommendation to Improve PSRR and Noise Performance
To improve ac measurements like PSRR, output noise, and transient response, it is recommended that the board
be designed with separate ground planes for V
pin of the device. In addition, the ground connection for the bypass capacitor should connect directly to the GND
pin of the device.
and V
IN
, with each ground plane connected only at the GND
OUT
9
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P
D(max
)
T
J
maxT
A
R
JA
P
D
VINV
OUT
I
OUT
V
OUT
V
REF
1
R
1
R
2
R
1
V
OUT
V
ref
1
R
2
C
1
(3 x 107) x (R
1
R2)
(R
1
x R2)
TPS79301, TPS79318
TPS79325, TPS79328, TPS793285
TPS79330, TPS79333, TPS793475
SLVS348H – JULY 2001 – REVISED OCTOBER 2004
APPLICATION INFORMATION (continued)
Power Dissipation and Junction Temperature
Specified regulator operation is assured to a junction temperature of 125 ° C; the maximum junction temperature
should be restricted to 125 ° C under normal operating conditions. This restriction limits the power dissipation the
regulator can handle in any given application. To ensure the junction temperature is within acceptable limits,
calculate the maximum allowable dissipation, P
equal to P
.
D(max)
The maximum power dissipation limit is determined using Equation 1 :
Where:
• TJmax is the maximum allowable junction temperature.
• R
• TAis the ambient temperature.
is the thermal resistance junction-to-ambient for the package (see the Dissipation Ratings Table).
θ JA
The regulator dissipation is calculated using Equation 2 :
Power dissipation resulting from quiescent current is negligible. Excessive power dissipation triggers the thermal
protection circuit.
, and the actual dissipation, PD, which must be less than or
D(max)
(1)
(2)
Programming the TPS79301 Adjustable LDO Regulator
The output voltage of the TPS79301 adjustable regulator is programmed using an external resistor divider as
shown in Figure 23 . The output voltage is calculated using Equation 3 :
Where:
• V
Resistors R1 and R2 should be chosen for approximately 50-µA divider current. Lower value resistors can be
used for improved noise performance, but the solution consumes more power. Higher resistor values should be
avoided as leakage current into/out of FB across R1/R2 creates an offset voltage that artificially increases/decreases the feedback voltage and thus erroneously decreases/increases V
design procedure is to choose R2 = 30.1 k Ω to set the divider current at 50 µA, C1 = 15 pF for stability, and then
calculate R1 using Equation 4 :
In order to improve the stability of the adjustable version, it is suggested that a small compensation capacitor be
placed between OUT and FB. For voltages <1.8 V, the value of this capacitor should be 100 pF. For voltages
>1.8 V, the approximate value of this capacitor can be calculated as shown in Equation 5 :
The suggested value of this capacitor for several resistor ratios is shown in the table below. If this capacitor is
not used (such as in a unity-gain configuration) or if an output voltage <1.8 V is chosen, then the minimum
recommended output capacitor is 4.7 µF instead of 2.2 µF.
= 1.2246 V typ (the internal reference voltage)
REF
. The recommended
OUT
(3)
(4)
(5)
10
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22 pF
15 pF
15 pF
OUTPUT VOLTAGE
PROGRAMMING GUIDE
OUTPUT
VOLTAGE
R1 R2
2.5 V
3.3 V
3.6 V
C1
31.6 k
Ω
51 k
Ω
59 k
Ω
30.1 k
Ω
30.1 k
Ω
30.1 k
Ω
0 pF1.22 V short open
TPS793xx
GNDNR
FB
IN OUT
EN
V
IN
V
OUT
R1
C1
R2
1µF
1µF
0.01µF
TPS79301, TPS79318
TPS79325, TPS79328, TPS793285
TPS79330, TPS79333, TPS793475
SLVS348H – JULY 2001 – REVISED OCTOBER 2004
APPLICATION INFORMATION (continued)
Figure 23. TPS79301 Adjustable LDO Regulator Programming
Regulator Protection
The TPS793xx PMOS-pass transistor has a built-in back diode that conducts reverse current when the input
voltage drops below the output voltage (e.g., during power-down). Current is conducted from the output to the
input and is not internally limited. If extended reverse voltage operation is anticipated, external limiting might be
appropriate.
The TPS793xx features internal current limiting and thermal protection. During normal operation, the TPS793xx
limits output current to approximately 400 mA. When current limiting engages, the output voltage scales back
linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device failure,
care should be taken not to exceed the power dissipation ratings of the package or the absolute maximum
voltage ratings of the device. If the temperature of the device exceeds approximately 165 ° C, thermal-protection
circuitry shuts it down. Once the device has cooled down to below approximately 140 ° C, regulator operation
resumes.
11
www.ti.com
0.625 Max
NOTES:A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. NanoStar package configuration.
D. This package is tin-lead (SnPb); consult the factory for availability of lead-free material.
NanoStar is a trademark of Texas Instruments.
1,30
1,34
0,79
0,84
TPS79301, TPS79318
TPS79325, TPS79328, TPS793285
TPS79330, TPS79333, TPS793475
SLVS348H – JULY 2001 – REVISED OCTOBER 2004
TPS793xxYEQ NanoStar ™ Wafer Chip Scale Information
Figure 24. NanoStar ™ Wafer Chip Scale Package
12
PACKAGE OPTION ADDENDUM
www.ti.com
13-Oct-2004
PACKAGING INFORMATION
ORDERABLE DEVICE STATUS(1) PACKAGE TYPE PACKAGE DRAWING PINS PACKAGE QTY
TPS79301DBVR ACTIVE SOP DBV 6 3000
TPS79318DBVR ACTIVE SOP DBV 5 3000
TPS79318DBVT ACTIVE SOP DBV 5 250
TPS79318YEQR ACTIVE DSBGA YEQ 5 3000
TPS79318YEQT ACTIVE DSBGA YEQ 5 250
TPS79325DBVR ACTIVE SOP DBV 5 3000
TPS79325YEQR ACTIVE DSBGA YEQ 5 3000
TPS79325YEQT ACTIVE DSBGA YEQ 5 250
TPS793285DBVR ACTIVE SOP DBV 5 3000
TPS793285DBVT ACTIVE SOP DBV 5 250
TPS793285YEQR ACTIVE DSBGA YEQ 5 3000
TPS793285YEQT ACTIVE DSBGA YEQ 5 250
TPS79328DBVR ACTIVE SOP DBV 5 3000
TPS79328YEQR ACTIVE DSBGA YEQ 5 3000
TPS79328YEQT ACTIVE DSBGA YEQ 5 250
TPS79330DBVR ACTIVE SOP DBV 5 3000
TPS79330YEQR ACTIVE DSBGA YEQ 5 3000
TPS79330YEQT ACTIVE DSBGA YEQ 5 250
TPS79333DBVR ACTIVE SOP DBV 5 3000
TPS793475DBVR ACTIVE SOP DBV 5 3000
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
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