DAvailable in 2.5 V, 3.3 V
DProgrammable Slew Rate Control
DOutput Noise Typically 56 µV
RMS
DOnly 17 µA Quiescent Current at 150 mA
D1 µA Quiescent Current in Standby Mode
DDropout Voltage Typically 150 mV at 150 mA
(TPS78833)
DOver Current Limitation
D–40°C to 125°C Operating Junction
Temperature Range
D5-Pin SOT-23 (DBV) Package
DBV PACKAGE
(TOP VIEW)
GND
EN
1
IN
2
3
OUT
5
4
SR
DESCRIPTION
The TPS78825 and TPS78833 are very small (SOT-23)
package, low-noise LDOs that regulate the output
voltage to 2.5 V and 3.3 V with input voltage ranging
from 2.7 V to an absolute maximum of 13.5 V. These
devices output 150 mA with a peak current of 350 mA
(typ). The TPS788xx family uses the SR pin to program
the output voltage slew rate to control the in-rush
current. This is specifically used in the USB application
where large load capacitance is present at start-up. The
TPS788xx devices use only 17 µA of quiescent current
and exhibit only 56 µV
a 10 µF output capacitor.
The usual PNP pass transistor has been replaced by a
PMOS pass element. Because the PMOS pass element
behaves as a low-value resistor, the dropout voltage is
very low, typically 150 mV at 150 mA of load current, and
is directly proportional to the load current.
The TPS788xx also features a logic-enabled sleep
mode to shut down the regulator, reducing quiescent
current to 1 µA typical at T
of output voltage noise using
RMS
= 25°C.
J
QUIESCENT CURRENT
FREE-AIR TEMPERATURE
25
VCC = 4.3 V
20
Aµ
15
10
Quiescent Current –
5
0
–40–25–10 5 20 35 50 65 80 95 110125
TA – Free-Air Temperature – °C
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
vs
IO = 150 mA
IO = 1 mA
www.ti.com
OUTPUT VOLTAGE, ENABLE VOLTAGE
5
0
Enable Voltage – V
C
= 0.01 µF
(SR)
3
C
(SR)
2
1
0
– Output Voltage – V
O
030201040 50706080 90 100
V
Copyright 2001, Texas Instruments Incorporated
vs
TIME (START-UP)
= 0.1 µF
VI = 4.3 V
VO = 3.3 V
IO = 150 mA
Co = 10 µF
TJ = 25°C
t – Time – ms
1
TPS78825, TPS78833
SOT 23
SLVS382A – JUNE 2001 – REVISED JULY 2001
T
J
–40°C to 125°C
†
The DBVT indicates tape and reel of 250 parts.
‡
The DBVR indicates tape and reel of 3000 parts.
functional block diagram
AVAILABLE OPTIONS
VOLTAGEPACKAGEPART NUMBERSYMBOL
2.5 V
3.3 V
SOT-23
(DBV)
TPS78825DBVT†TPS78825DBVR
TPS78833DBVTTPS78833DBVRPGTI
‡
PGZI
OUT
EN
GND
SR
IN
150 k
V
ref
Current Limit
/ Thermal
Protection
Terminal Functions
TERMINAL
NAMENO.
EN3IActive low enable
GND2Regulator ground
IN1IThe IN terminal is the input to the device.
OUT5OThe OUT terminal is the regulated output of the device.
SR4IThe SR terminal is used to control the in-rush current.
I/O
DESCRIPTION
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Operating virtual junction temperature range, T
Operating ambient temperature range, T
Storage temperature range, T
§
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to network ground terminal.
BOARD
Low K
High K
¶
The JEDEC Low K (1s) board design used to derive this data was a 3 inch x 3 inch, two layer board with 2 ounce copper traces on top of the board.
#
The JEDEC High K (2s2p) board design used to derive this data was a 3 inch x 3 inch, multilayer board with 1 ounce internal power and ground
planes and 2 ounce copper traces on top and bottom of the board.
VO + 1 V < VI ≤ 10 V, TJ = 25°C0.04
VO + 1 V < VI ≤ 10 V0.1
BW = 200 Hz to 100 kHz,
IO = 150 mA,
TJ = 25°C,
Co = 10 µF,
C
= 0.47 µF
(SR)
R
= 22 Ω
= 22 Ω,
Co = 10 µF,
= 10
TJ = 25°C
VO = 0 V (see Note 4)
C
C
C
= 0.01 µF (unless otherwise noted)
(SR)
56µV
= 0.01 µF10
(byp)
= 0.1 µF50
(byp)
= 0.47 µF300
(byp)
350750mA
,
V
µA
%/V
RMS
ms
Standby currentEN = 0 V, 2.7 V < VI < 10 V12µA
High level enable input voltage2.7 V < VI < 10 V1.7V
Low level enable input voltage2.7 V < VI < 10 V0.9V
Input current (EN)EN = 0–11µA
f = 1 kHz,
Power supply ripple rejectionTPS78833
Dropout voltage (see Note 6)TPS78833
NOTES: 2. To calculate the minimum input voltage for your maximum output current, use the following formula:
VI(min) = VO(max) + VDO (max load)
3. Continuous output current and operating junction temperature are limited by internal protection circuitry , but it is not recommended
that the device operate under conditions beyond those specified in this table for extended periods of time.
4. The minimum IN operating voltage is 2.7 V or V
output current is 200 mA.
5. If VO≤ 2.5 V then V
Line regulation (mV) +ǒ%ńV
If VO > 2.5 V then V
6. IN voltage equals VO(typ) – 100 mV
= 2.7 V, V
Imin
= VO + 1 V, V
Imin
Ǔ
TJ = 25°C,
Co = 10 µF
IO = 150 mA, TJ = 25°C150
IO = 150 mA300
+ 1 V , whichever is greater . The maximum IN voltage is 5.5 V . The maximum
O(typ)
= 5.5 V:
Imax
ǒ
V
V
Imax
O
100
= 5.5 V.
Imax
* 2.7 V
Ǔ
1000
C
= 0.01 µF,
(SL)
IO = 150 mA,
70dB
mV
www.ti.com
3
TPS78825, TPS78833
E
E
SLVS382A – JUNE 2001 – REVISED JULY 2001
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
vs
LOAD CURRENT
3.315
VCC = 4.3 V
TJ = 25°C
3.31
3.305
3.3
3.295
– Output Voltage – V
O
V
3.29
3.285
0 15 30 45 60 75 90 105 120 135 150
IL – Load Current – mA
Figure 1
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
400
Hz
nV/
Output Spectral Noise Density –
300
200
100
0
100
VI = 4.3 V
Co = 4.7 µF
C
= 0.47 µF
(SR)
1 k10 k100 k
f – Frequency – Hz
IO = 150 mA
IO = 1 mA
Figure 4
DROPOUT VOLTAGE
vs
FREE-AIR TEMPERATURE
200
VCC = 3.2 V
IO = 150 mA
150
100
– Dropout Voltage – V
50
DO
V
0
–40–25–10 5 20 35 50 65 80 95 110125
TA – Free-Air Temperature – °C
IO = 1 mA
Figure 7
OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
3.2
VCC = 4.3 V
3.315
3.31
3.305
3.3
3.295
3.29
– Output Voltage – V
3.285
O
V
3.28
3.275
3.27
–40 –25 –10 5 20 35 50 65 80 95 110 125
IO = 150 mA
TA – Free-Air Temperature – °C
IO = 1 mA
Figure 2
ROOT MEAN SQUARED OUTPUT NOIS
vs
SLEW RATE CAPACITANCE
100
(RMS)
Vµ
80
60
40
20
0.0010.010.11
C
RMS – Root Mean Squared Output Noise –
(sr)
VI = 4.3 V
VO = 3.3 V
IO = 150 mA
Co = 10 µF
BW = 200Hz to 100 kHz
– Slew Rate Capacitance – µF
Figure 5
RIPPLE REJECTION
vs
VI = 4.3 V
VO = 3.3 V
Co = 10 µF
C
= 0.47 µF
(SR)
IO = 150 mA
FREQUENCY
IO = 1 mA
f – Frequency – Hz
Ripple Rejection – dB
120
110
100
90
80
70
60
50
40
30
20
10
Figure 8
QUIESCENT CURRENT
vs
FREE-AIR TEMPERATURE
25
VCC = 4.3 V
20
Aµ
15
10
Quiescent Current –
5
0
–40–25–10 5 20 35 50 65 80 95 110125
TA – Free-Air Temperature – °C
IO = 150 mA
IO = 1 mA
Figure 3
OUTPUT IMPEDANCE
vs
FREQUENCY
2
VI = 4.3 V
1.8
Ω
– Output Impedance –Z
Co = 4.7 µF
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
IO = 1 mA
IO = 150 mA
0
1001 M101 k
f – Frequency – Hz
10 k
100 k
o
Figure 6
OUTPUT VOLTAGE, ENABLE VOLTAG
vs
TIME (START-UP)
5
0
Enable Voltage – V
3
2
1
0
– Output Voltage – V
O
V
1 M100 k10 k1 k100
0300200100400 500700600800 900 1000
VI = 4.3 V
VO = 3.3 V
IO = 150 mA
C
= 0.47 µF
(SR)
Co = 10 µF
TJ = 25°C
t – Time – ms
Figure 9
4
www.ti.com
TPS78825, TPS78833
SLVS382A – JUNE 2001 – REVISED JULY 2001
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE, ENABLE VOLTAGE
vs
TIME (START-UP)
5
0
Enable Voltage – V
C
= 0.01 µF
(SR)
3
C
= 0.1 µF
(SR)
2
1
0
– Output Voltage – V
O
030201040 50706080 90 100
V
t – Time – ms
VI = 4.3 V
VO = 3.3 V
IO = 150 mA
Co = 10 µF
TJ = 25°C
Figure 10
TYPICAL REGIONS OF STABILITY
EQUIVALENT SERIES RESISTANCE (ESR)
vs
100
10
OUTPUT CURRENT
VI = 4.3 V
VO = 3.3 V
Co = 4.7 µF
Region of Instability
LINE TRANSIENT RESPONSE
VO = 3.3 V
Co = 10 µF
20
– Input Voltage – V
0
I
–20
5.3
4.3
– Output Voltage – mV V
060402080 100140120160 180 200
O
V
t – Time – µs
dv
dt
Figure 11
LOAD TRANSIENT RESPONSE
0.2 V
=
µs
200
100
0
– Output Current – mA
O
I
50
0
–50
– Change In
O
–100
V
∆
060402080 100140120160 180
Output Voltage – mV
t – Time – µs
Figure 12
TYPICAL REGIONS OF STABILITY
EQUIVALENT SERIES RESISTANCE (ESR)
vs
100
10
OUTPUT CURRENT
VI = 4.3 V
VO = 3.3 V
Co = 10 µF
Region of Instability
0.075 A
dI
=
dt
VI = 4.3 V
VO = 3.3 V
Co = 10 µF
µs
200
1
Region of Stability
ESR – Equivalent Series Resistance – Ω
0.1
06090120150
IO – Output Current – mA
Figure 13
1
Region of Stability
ESR – Equivalent Series Resistance – Ω
0.1
06090120150
IO – Output Current – mA
Figure 14
www.ti.com
5
TPS78825, TPS78833
SLVS382A – JUNE 2001 – REVISED JULY 2001
APPLICATION INFORMATION
The TPS788xx family of low-dropout (LDO) regulators has been optimized for use in battery-operated
equipment. It features extremely low dropout voltages, low output noise, low quiescent current (17 µA typically),
and enable inputs to reduce supply currents to 1 µA when the regulator is turned off. A typical application circuit
is shown in Figure 15.
1
V
I
1 µF
IN
3
EN
GND
2
SR
OUT
4
5
V
O
+
4.7 µF
ESR = 0.2 Ω
0.01 µF
Figure 15. Typical Application Circuit
external capacitor requirements
Although not required, a 0.047-µF or larger ceramic input bypass capacitor , connected between IN and GND
and located close to the TPS788xx, is recommended to improve transient response and noise rejection. A
higher-value electrolytic input capacitor may be necessary if large, fast-rise-time load transients are anticipated
and the device is located several inches from the power source.
Like all low dropout regulators, the TPS788xx requires an output capacitor connected between OUT and GND
to stabilize the internal control loop. The minimum recommended capacitance is 4.7 µF. The ESR (equivalent
series resistance) of the capacitor should be between 0.2 Ω and 10 Ω. to ensure stability . Capacitor values larger
than 4.7 µF are acceptable, and allow the use of smaller ESR values. Capacitances less than 4.7 µF are not
recommended because they require careful selection of ESR to ensure stability. Solid tantalum electrolytic,
aluminum electrolytic, and multilayer ceramic capacitors are all suitable, provided they meet the requirements
described above. Most of the commercially available 4.7 µF surface-mount solid tantalum capacitors, including
devices from Sprague, Kemet, and Nichico, meet the ESR requirements stated above. Multilayer ceramic
capacitors may have very small equivalent series resistances and may thus require the addition of a low value
series resistor to ensure stability.
Size is in mm. The ESR maximum resistance is in Ohms at 100 kHz and TA = 25°C. Contact the
manufacturer for the minimum ESR values.
†
SIZE (H × L × W)
†
6
www.ti.com
SLVS382A – JUNE 2001 – REVISED JULY 2001
TPS78825, TPS78833
APPLICATION INFORMATION
external capacitor requirements (continued)
The external bypass capacitor, used in conjunction with an internal resistor to form a low-pass filter, should be
a low ESR ceramic capacitor. For example, the TPS78833 exhibits only 56 µV
a 0.01 µF ceramic bypass capacitor and a 10-µF ceramic output capacitor. Note that the output will start up
slower as the bypass capacitance increases due to the RC time constant at the bypass pin that is created by
the internal 150-kΩ resistor and external capacitor.
of output voltage noise using
RMS
power dissipation and junction temperature
Specified regulator operation is assured to a junction temperature of 125°C; the maximum junction temperature
should be restricted to 125°C under normal operating conditions. This restriction limits the power dissipation
the regulator can handle in any given application. T o ensure the junction temperature is within acceptable limits,
calculate the maximum allowable dissipation, P
or equal to P
The maximum-power-dissipation limit is determined using the following equation:
D(max)
.
, and the actual dissipation, PD, which must be less than
D(max)
P
D(max)
Where:
T
maxis the maximum allowable junction temperature.
J
is the thermal resistance junction-to-ambient for the package, see the dissipation rating table.
R
θJA
is the ambient temperature.
T
A
The regulator dissipation is calculated using:
P
+
D
Power dissipation resulting from quiescent current is negligible. Excessive power dissipation will trigger the
thermal protection circuit.
+
ǒ
VI* V
TJmax * T
R
Ǔ
O
θJA
I
A
O
regulator protection
The TPS788xx PMOS-pass transistor has a built-in back diode that conducts reverse current when the input
voltage drops below the output voltage (e.g., during power down). Current is conducted from the output to the
input and is not internally limited. If extended reverse voltage operation is anticipated, external limiting might
be appropriate.
The TPS788xx features internal current limiting and thermal protection. During normal operation, the TPS78833
limits output current to approximately 350 mA. When current limiting engages, the output voltage scales back
linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device failure,
care should be taken not to exceed the power dissipation ratings of the package. If the temperature of the device
exceeds approximately 165°C, thermal-protection circuitry shuts it down. Once the device has cooled down to
below approximately 140°C, regulator operation resumes.
www.ti.com
7
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