Datasheet TPS77930DGK, TPS77925DGKR, TPS77925DGK, TPS77918DGK, TPS77918DGKR Datasheet (Texas Instruments)

TPS77901, TPS77918, TPS77925, TPS77930

250-mA LDO REGULATOR WITH INTEGRATED RESET IN A MSOP8 PACKAGE

SLVS283A – MARCH 2000 – REVISED MARCH 2000

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Open Drain Power-On Reset With 220-ms
Delay

D

250-mA Low-Dropout Voltage Regulator

D

Available in 1.8-V, 2.5-V, 3-V, Fixed Output
and Adjustable Versions

D

Dropout Voltage Typically 200 mV
at 250 mA (TPS77930)

D

Ultra Low 92-µA Quiescent Current (Typ)

D

8-Pin MSOP (DGK) Package

D

Low Noise (55 µV

rms

) With No Bypass

Capacitor (TPS77918)

D

2% Tolerance Over Specified Conditions
For Fixed-Output Versions

D

Fast Transient Response

D

Thermal Shutdown Protection

D

See the TPS773xx and TPS774xx Family of
Devices for Active Low Enable

description

The TPS779xx is a low dropout regulator with
integrated power-on reset. The device is capable
of supplying 250 mA of output current with a
dropout of 200 mV (TPS77930). Quiescent
current is 92 µA at full load dropping down to 1 µA
when the device is disabled. The device is
optimized to be stable with a wide range of output
capacitors including low ESR ceramic (10 µF) or
low capacitance (1 µF) tantalum capacitors. The
device has extremely low noise output perfor­mance (55 µV

rms

) without using any added filter
capacitors. TPS779xx is designed to have a fast
transient response for larger load current
changes.

The TPS779xx is offered in 1.8-V, 2.5-V, and 3-V fixed-voltage versions and in an adjustable version
(programmable over the range of 1.5 V to 5.5 V). Output voltage tolerance is 2% over line, load, and temperature
ranges. The TPS779xx family is available in 8-pin MSOP (DGK) packages.

Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 200 mV
at an output current of 250 mA for 3.3 volt option) and is directly proportional to the output current. Additionally ,
since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent
of output loading (typically 92 µA over the full range of output current, 0 mA to 250 mA). These two key
specifications yield a significant improvement in operating life for battery-powered systems.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

This document contains information on products in more than one phase
of development. The status of each device is indicated on the page(s)
specifying its electrical characteristics.

Copyright  2000, Texas Instruments Incorporated

FB/SENSE

RESET

EN

GND

OUT
OUT
IN
IN

TPS779xx

DGK PACKAGE

(TOP VIEW)

1
2
3
4

8
7
6
5

200

150

100

0
–50 –30 –10 10 30 50 70

300

350

400

90 110 130

250

50

TPS77930

DROPOUT VOLTAGE

vs

JUNCTION TEMPERATURE

TJ – Junction Temperature – °C

– Dropout Voltage – mV
V

DO

IL= 0.05 A

IL= 0.15 A

IL= 0.25 A

VI = 2.9 V

TPS77901, TPS77918, TPS77925, TPS77930
250-mA LDO REGULATOR WITH INTEGRATED RESET IN A MSOP8 PACKAGE

SLVS283A – MARCH 2000 – REVISED MARCH 2000

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description (continued)

The device is enabled when the EN pin is connected to a high-level input voltage. This LDO family also features
a sleep mode; applying a TTL low signal to EN (enable) shuts down the regulator, reducing the quiescent current
to less than 1 µA at TJ = 25°C.

The TPS779xx features an integrated power-on reset, commonly used as a supply voltage supervisor (SVS),
or reset output voltage. The RESET

output of the TPS779xx initiates a reset in DSP, microcomputer or
microprocessor systems at power-up and in the event of an undervoltage condition. An internal comparator in
the TPS779xx monitors the output voltage of the regulator to detect an undervoltage condition on the regulated
output voltage. When OUT reaches 95% of its regulated voltage, RESET will go to a high-impedance state after
a 220 ms delay . RESET will go to low-impedance state when OUT is pulled below 95% (i.e. over load condition)
of its regulated voltage.

AVAILABLE OPTIONS

T

OUTPUT

VOLTAGE

(V)

PACKAGED DEVICES

J

TYP

MSOP
(DGK)

3.0 TPS77930DGK

2.5 TPS77925DGK

–40°C to 125°C

1.8 TPS77918DGK

Adjustable

1.5 V to 5.5 V

TPS77901DGK

The TPS77901 is programmable using an external resistor divider (see
application information). The DGK package is available taped and
reeled. Add an R suffix to the device type (e.g., TPS77901DGKR).

OUT

SENSE

6

5

3

IN

IN

EN

GND

4

7

1

V

I

0.1 µF

10 µF

+

OUT

8

V

O

RESET OutputRESET

2

Figure 1. Typical Application Configuration (For Fixed Output Options)

TPS77901, TPS77918, TPS77925, TPS77930

250-mA LDO REGULATOR WITH INTEGRATED RESET IN A MSOP8 PACKAGE

SLVS283A – MARCH 2000 – REVISED MARCH 2000

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram—adjustable version

220 ms Delay

_
+

V

ref

= 1.1834 V

OUT

FB/SENSE

EN

GND

RESET

_

+

IN

External to the device

R1

R2

functional block diagram—fixed-voltage version

_
+

V

ref

= 1.1834 V

OUT

EN

GND

R1

R2

RESET

_

+

IN

SENSE

220 ms Delay

Terminal Functions (TPS779xx)

TERMINAL

NAME NO.

I/O

DESCRIPTION

FB/SENSE 1 I Feedback input voltage for adjustable device (sense input for fixed options)
RESET 2 O Reset output
EN 3 I Enable input
GND 4 Regulator ground
IN 5, 6 I Input voltage
OUT 7, 8 O Regulated output voltage

TPS77901, TPS77918, TPS77925, TPS77930
250-mA LDO REGULATOR WITH INTEGRATED RESET IN A MSOP8 PACKAGE

SLVS283A – MARCH 2000 – REVISED MARCH 2000

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS779xx RESET timing diagram

†

V

res

is the minimum input voltage for a valid RESET . The symbol V

res

is not currently listed within EIA or JEDEC standards

for semiconductor symbology.

V

I

V

res

†

V

res

t

t

t

V

O

Threshold

Voltage

RESET
Output

220 ms
Delay

220 ms
Delay

Output
Undefined

Output

Undefined

V

IT+

‡

V

IT–

‡

V

IT–

‡

V

IT+

‡

‡

VIT –Trip voltage is typically 5% lower than the output voltage (95%VO) V

IT–

to V

IT+

is the hysteresis voltage.

TPS77901, TPS77918, TPS77925, TPS77930

250-mA LDO REGULATOR WITH INTEGRATED RESET IN A MSOP8 PACKAGE

SLVS283A – MARCH 2000 – REVISED MARCH 2000

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating junction temperature range

(unless otherwise noted)

Ĕ

Input voltage range‡, VI –0.3 V to 13.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range at EN –0.3 V to 16.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum RESET voltage 16.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Peak output current Internally limited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage, V

O

(OUT, FB) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating virtual junction temperature range, TJ –40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ESD rating, HBM 2 kV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

‡

All voltage values are with respect to network terminal ground.

DISSIPATION RATING TABLE – FREE-AIR TEMPERATURES

PACKAGE

AIR FLOW

(CFM)

θ

JA

(°C/W)

θ

JC

(°C/W)

TA < 25°C

POWER RATING

DERATING FACTOR

ABOVE TA = 25°C

TA = 70°C

POWER RATING

TA = 85°C

POWER RATING

0 266.2 3.84 376 mW 3.76 mW/°C 207 mW 150 mW

DGK

150 255.2 3.92 392 mW 3.92 mW/°C 216 mW 157 mW
250 242.8 4.21 412 mW 4.12 mW/°C 227 mW 165 mW

recommended operating conditions

MIN MAX UNIT

Input voltage, V

I

§

2.7 10 V

Output voltage range, V

O

1.5 5.5 V
Output current, IO (see Note 1) 0 250 mA
Operating virtual junction temperature, TJ (see Note 1) –40 125 °C

§

To calculate the minimum input voltage for your maximum output current, use the following equation: V

I(min)

= V

O(max)

+ V

DO(max load)

.

NOTE 1: Continuous current and operating junction temperature are limited by internal protection circuitry, but it is not recommended that the

device operate under conditions beyond those specified in this table for extended periods of time.

TPS77901, TPS77918, TPS77925, TPS77930
250-mA LDO REGULATOR WITH INTEGRATED RESET IN A MSOP8 PACKAGE

SLVS283A – MARCH 2000 – REVISED MARCH 2000

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating junction temperature range (TJ = –40°C to
125°C), V

I

= V

O(typ)

+ 1 V, IO = 1 mA, EN = 5 V, CO = 10 µF (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Adjustable

1.5 V ≤ VO ≤ 5.5 V, TJ = 25°C V

O

j

voltage

1.5 V ≤ VO ≤ 5.5 V 0.98V

O

1.02V

O

p

TJ = 25°C, 2.8 V < VIN < 10 V 1.8

p

1.8 V Output

2.8 V < VIN < 10 V 1.764 1.836

Output voltage (see Notes 2 and 4)

p

TJ = 25°C, 3.5 V < VIN < 10 V 2.5

V

2.5 V Output

3.5 V < VIN < 10 V 2.45 2.55

p

TJ = 25°C, 4.0 V < VIN < 10 V 3.0

3.0 V Output

4.0 V < VIN < 10 V 2.94 3.06
TJ = 25°C 92

Quiescent current (GND current) (see Notes 2 and 4)

125

µ

A

Output voltage line regulation (∆V/V)

VO + 1 V < VI ≤ 10 V, TJ = 25°C 0.005 %/V

gg(

OO

)

(see Note 3)

VO + 1 V < VI ≤ 10 V 0.05 %/V

Load regulation TJ = 25°C 1 mV
Output noise voltage

BW = 300 Hz to 100 kHz, TJ = 25°C,
TPS77930

55 µVrms

Output current Limit VO = 0 V 0.9 1.3 A
Peak output current 2 ms pulse width, 50% duty cycle 400 mA
Thermal shutdown junction temperature 144 °C

EN = V

I,

TJ = 25°C 1 µA

Standby current

EN = V

I

3 µA

FB input current

Adjustable
Voltage

FB = 1.5 V 1 µA

High level enable input voltage 2 V
Low level enable input voltage 0.7 V
Enable input current –1 1 µA
Power supply ripple rejection (TPS77318, TPS77418) f = 1 KHz, TJ = 25°C 55 dB

NOTES: 2. Minimum input operating voltage is 2.7 V or V

O(typ)

+ 1 V , whichever is greater. Maximum input voltage = 10 V, minimum output

current 1 mA.

3. If VO < 1.8 V then V

imax

= 10 V, V

imin

= 2.7 V:

Line Regulation (mV)

+ǒ%ńVǓ

V

O

ǒ

V

imax

*

2.7 V

Ǔ

100

1000

If VO > 2.5 V then V

imax

= 10 V, V

imin

= Vo + 1 V :

Line Regulation (mV)

+ǒ%ńVǓ

V

O

ǒ

V

imax

*ǒVO)

1

Ǔ

Ǔ

100

1000

4. IO = 1 mA to 250 mA

TPS77901, TPS77918, TPS77925, TPS77930

250-mA LDO REGULATOR WITH INTEGRATED RESET IN A MSOP8 PACKAGE

SLVS283A – MARCH 2000 – REVISED MARCH 2000

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating junction temperature range (TJ = –40°C to
125°C), V

I

= V

O(typ)

+ 1 V, IO = 1 mA, EN = 5 V, CO = 10 µF (unless otherwise noted) (continued)

PARAMETER TEST CONDITIONS

MIN TYP MAX UNIT

Minimum input voltage for valid RESET I

(RESET)

= 300 µA 1.1 V

Trip threshold voltage VO decreasing 92 98 %V

O

Hysteresis voltage Measured at V

O

0.5 %V

O

Reset

Output low voltage VI = 2.7 V, I

(RESET)

= 1 mA 0.15 0.4 V

Leakage current V

(RESET)

= 5 V 1 µA

RESET time-out delay 220 ms

p

p

IO = 250 mA, TJ = 25°C 250

V

DO

Dropout voltage (see Note 5)

3 V Output

IO = 250 mA 475

mV

NOTE 5: IN voltage equals VO(Typ) – 100 mV ; 1.8 V , and 2.5 V dropout voltage limited by input voltage range limitations (i.e., 3.3 V input voltage

needs to drop to 3.2 V for purpose of this test).

TYPICAL CHARACTERISTICS

Table of Graphs

FIGURE

p

vs Output current 2, 3

VOOutput voltage

vs Junction temperature 4, 5
Ground current vs Junction temperature 6
Power supply rejection ratio vs Frequency 7
Output spectral noise density vs Frequency 8

Z

o

Output impedance vs Frequency 9

p

vs Input voltage 10

VDODropout voltage

vs Junction temperature 11
Line transient response 12, 14
Load transient response 13, 15
Output voltage vs Time 16
Equivalent series resistance (ESR) vs Output current 18 – 21

TPS77901, TPS77918, TPS77925, TPS77930
250-mA LDO REGULATOR WITH INTEGRATED RESET IN A MSOP8 PACKAGE

SLVS283A – MARCH 2000 – REVISED MARCH 2000

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 2

3.0

2.999

0 50 100 150

3.001

200 250

TPS77930

OUTPUT VOLTAGE

vs

OUTPUT CURRENT

IO – Output Current – mA

– Output Voltage – V
V

O

3.002

2.998

Figure 3

1.800

1.798
0 50 100 150

1.802

200 250

TPS77918

OUTPUT VOLTAGE

vs

OUTPUT CURRENT

IO – Output Current – mA

– Output Voltage – V
V

O

1.799

1.801

Figure 4

2.99

2.97

2.95

3.01

3.03

3.05

TJ – Junction Temperature – °C

TPS77930

OUTPUT VOLTAGE

vs

JUNCTION TEMPERATURE

– Output Voltage – V
V

O

VI = 4.3 V

–40 0 40 80 120 140

IO = 250 mA

Figure 5

TJ – Junction Temperature – °C

TPS77918

OUTPUT VOLTAGE

vs

JUNCTION TEMPERATURE

– Output Voltage – V
V

O

1.80

1.78

1.76

1.84

1.82

–40 0 40 80 120

VI = 2.8 V

140

IO = 1 mA
IO = 50 mA

1.86

IO = 250 mA

TPS77901, TPS77918, TPS77925, TPS77930

250-mA LDO REGULATOR WITH INTEGRATED RESET IN A MSOP8 PACKAGE

SLVS283A – MARCH 2000 – REVISED MARCH 2000

9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

TPS779xx

GROUND CURRENT

vs

JUNCTION TEMPERATURE

TJ – Junction Temperature – °C

Ground Current – Aµ

95

90

85

80

–40 10 60

100

105

115

110 140

110

IO = 1 mA

IO = 250 mA

Figure 6

Figure 7

50

10

20

0

10 100 1k 10k

PSRR – Power Supply Rejection Ratio – dB

70

90

f – Frequency – Hz

TPS77930

POWER SUPPLY REJECTION RATIO

vs

FREQUENCY

100

100k 10M

80

30

40

60

1M

IO = 1 mA

IO = 250 mA

Figure 8

TPS77930

OUTPUT SPECTRAL NOISE DENSITY

vs

FREQUENCY

f – Frequency – Hz

100 1k 10k 100k

10

1

IO = 1 mA

IO = 250 mA

V HzOutput Spectral Noise Density – µ

0.1

0.01

TPS77901, TPS77918, TPS77925, TPS77930
250-mA LDO REGULATOR WITH INTEGRATED RESET IN A MSOP8 PACKAGE

SLVS283A – MARCH 2000 – REVISED MARCH 2000

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

f – Frequency – Hz

– Output Impedance –Z

o

Ω

10 100 100k 10M

10

1

10k1k

IO = 1 mA

IO = 250 mA

TPS77930

OUTPUT IMPEDANCE

vs

FREQUENCY

0.1

0.01
1M

Figure 9

Figure 10

200

150

100

0

2.7 3.2 3.7 4.2

300

350

400

4.7

250

50

TPS77901

DROPOUT VOLTAGE

vs

INPUT VOLTAGE

VI – Input Voltage – V

– Dropout Voltage – mV

V

DO

TJ = 125 °C

TJ = –40 °C

TJ = 25 °C

IO = 250 mA

Figure 11

200

150

100

0

–50 –30 –10 10 30 50 70

300

350

400

90 110 130

250

50

TPS77930

DROPOUT VOLTAGE

vs

JUNCTION TEMPERATURE

TJ – Junction Temperature – °C

– Dropout Voltage – mV
V

DO

IL= 0.05 A

IL= 0.15 A

IL= 0.25 A

VI = 2.9 V

TPS77901, TPS77918, TPS77925, TPS77930

250-mA LDO REGULATOR WITH INTEGRATED RESET IN A MSOP8 PACKAGE

SLVS283A – MARCH 2000 – REVISED MARCH 2000

11

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 12

TPS77918

LINE TRANSIENT RESPONSE

t – Time – ms

V

O

– Change in

V

I

– Input Voltage – V

∆

Output Voltage – mV

3.8

0.30.20.1 0.4 0.5 0.70.6 0.8 0.9 1

CO = 10 µF
TJ = 25 °C
IL = 250 mA

0

0

2.8

10

–10

Figure 13

TPS77918

LOAD TRANSIENT RESPONSE

t – Time – ms

V

O

– Change in

I

O

– Output Current – mA

∆

Output Voltage – mV

250

0.60.40.2 0.8 1 1.41.2 1.6 1.8 2

CO = 10 µF
TJ = 25 °C
IL = 250 mA

0

–50

–100

0

0

Figure 14

TPS77930

LINE TRANSIENT RESPONSE

t – Time – ms

V

O

– Change in

V

I

– Input Voltage – V

∆

Output Voltage – mV

5

0.30.20.1 0.4 0.5 0.70.6 0.8 0.9 1

CO = 10 µF
TJ = 25 °C
IL = 250 mA

0

0

4

10

–10

Figure 15

TPS77930

LOAD TRANSIENT RESPONSE

t – Time – ms

V

O

– Change in∆

Output Voltage – mV

0

0.30.20.1 0.4 0.5 0.70.6 0.8 0.9 1

CO = 10 µF
TJ = 25 °C
IL = 250 mA

0

0

250

–50

–100

I

O

– Output Current – mA

TPS77901, TPS77918, TPS77925, TPS77930
250-mA LDO REGULATOR WITH INTEGRATED RESET IN A MSOP8 PACKAGE

SLVS283A – MARCH 2000 – REVISED MARCH 2000

12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

t – Time – ms

TPS77930

OUTPUT VOLTAGE

vs

TIME (AT STARTUP)

0 2.0

0

0

EN

0.2 1.81.61.41.21.00.4 0.6 0.8

– Output Voltage – V
V

O

Enable Pulse – V

CO = 10 µF

Figure 16

IN

EN

OUT

+

GND

C

O

ESR

R

L

V

I

To Load

Figure 17. Test Circuit for Typical Regions of Stability (Figures 25 through 28) (Fixed Output Options)

TPS77901, TPS77918, TPS77925, TPS77930

250-mA LDO REGULATOR WITH INTEGRATED RESET IN A MSOP8 PACKAGE

SLVS283A – MARCH 2000 – REVISED MARCH 2000

13

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 18

0.1
0 50 100 150 200 250

TYPICAL REGION OF STABILITY

EQUIVALENT SERIES RESISTANCE

†

vs

OUTPUT CURRENT

10

IO – Output Current – mA

ESR – Equivalent Series Resistance – Ω

1

VO = 3.0 V
CO = 1 µF
VI = 4.3 V
TJ = 25°C

Region of Stability

Region of Instability

Region of Instability

Figure 19

0.1

0 50 100 150 200 250

TYPICAL REGION OF STABILITY

EQUIVALENT SERIES RESISTANCE

†

vs

OUTPUT CURRENT

10

IO – Output Current – mA

ESR – Equivalent Series Resistance – Ω

1

Region of Stability

Region of Instability

Region of Instability

VO = 3.0 V
CO = 10 µF
VI = 4.3 V
TJ = 25°C

0.01

Figure 20

0.1
0 50 100 150 200 250

TYPICAL REGION OF STABILITY

EQUIVALENT SERIES RESISTANCE

†

vs

OUTPUT CURRENT

10

IO – Output Current – mA

ESR – Equivalent Series Resistance – Ω

1

VO = 3.0 V
CO = 1 µF
VI = 4.3 V
TJ = 125 °C

Region of Stability

Region of Instability

Region of Instability

Figure 21

0.1

0 50 100 150 200 250

TYPICAL REGION OF STABILITY

EQUIVALENT SERIES RESISTANCE

†

vs

OUTPUT CURRENT

10

IO – Output Current – mA

ESR – Equivalent Series Resistance – Ω

1

Region of Stability

Region of Instability

0.01

Region of Instability

VO = 3.0 V
CO = 10 µF
VI = 4.3 V
TJ = 125°C

†

Equivalent series resistance (ESR) refers to the total series resistance, including the ESR of the capacitor, any series resistance added
externally, and PWB trace resistance to CO.

TPS77901, TPS77918, TPS77925, TPS77930
250-mA LDO REGULATOR WITH INTEGRATED RESET IN A MSOP8 PACKAGE

SLVS283A – MARCH 2000 – REVISED MARCH 2000

14

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

pin functions

enable (EN)

The EN terminal is an input which enables or shuts down the device. If EN is a logic low, the device will be in
shutdown mode. When EN goes to logic high, then the device will be enabled.

sense (SENSE)

The SENSE terminal of the fixed-output options must be connected to the regulator output, and the connection
should be as short as possible. Internally, SENSE connects to a high-impedance wide-bandwidth amplifier
through a resistor-divider network and noise pickup feeds through to the regulator output. It is essential to route
the SENSE connection in such a way to minimize/avoid noise pickup. Adding RC networks between the SENSE
terminal and VO to filter noise is not recommended because it can cause the regulator to oscillate.

feedback (FB)

FB is an input terminal used for the adjustable-output options and must be connected to an external feedback
resistor divider. The FB connection should be as short as possible. It is essential to route it in such a way to
minimize/avoid noise pickup. Adding RC networks between FB terminal and V

O

to filter noise is not

recommended because it can cause the regulator to oscillate.

reset (RESET)

The RESET terminal is an open drain, active low output that indicates the status of VO. When VO reaches 95%
of the regulated voltage, RESET will go to a low-impedance state after a 220-ms delay. RESET will go to a
high-impedance state when V

out

is below 95% of the regulated voltage. The open-drain output of the RESET

terminal requires a pullup resistor.

external capacitor requirements

An input capacitor is not usually required; however, a bypass capacitor (0.047 µF or larger) improves load
transient response and noise rejection if the TPS779xx is located more than a few inches from the power supply .
A higher-capacitance capacitor may be necessary if large (hundreds of milliamps) load transients with fast rise
times are anticipated.

Most low noise LDOs require an external capacitor to further reduce noise. This will impact the cost and board
space. The TPS779xx has a very low noise specification requirement without using any external component.

Like all low dropout regulators, the TPS779xx requires an output capacitor connected between OUT (output
of the LDO) and GND (signal ground) to stabilize the internal control loop. The minimum recommended
capacitance value is 1 µF provided the ESR meets the requirement in Figures 19 and 21. In addition, a low-ESR
capacitor can be used if the capacitance is at least 10 µF and the ESR meets the requirements in Figures 18
and 20. Solid tantalum electrolytic, aluminum electrolytic, and multilayer ceramic capacitors are all suitable,
provided they meet the requirements described previously.

Ceramic capacitors have different types of dielectric material with each exhibiting different temperature and
voltage variation. The most common types are X5R, X7R, Y5U, Z5U, and NPO. The NPO type ceramic type
capacitors are generally the most stable over temperature. However, the X5R and X7R are also relatively stable
over temperature (with the X7R being the more stable of the two) and are therefore acceptable to use. The Y5U
and Z5U types provide high capacitance in a small geometry, but exhibit large variations over temperature;
therefore, the Y5U and Z5U are not generally recommended for use on this LDO. Independent of which type
of capacitor is used, one must make certain that at the worst case condition the capacitance/ESR meets the
requirement specified in Figures 18 – 21.

TPS77901, TPS77918, TPS77925, TPS77930

250-mA LDO REGULATOR WITH INTEGRATED RESET IN A MSOP8 PACKAGE

SLVS283A – MARCH 2000 – REVISED MARCH 2000

15

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

Figure 22 shows the output capacitor and its parasitic impedances in a typical LDO output stage.

LDO

V

I

V

ESR

I

O

R

ESR

C

O

R

LOAD

V

O

+

–

Figure 22. – LDO Output Stage With Parasitic Resistances ESR and ESL

In steady state (dc state condition), the load current is supplied by the LDO (solid arrow) and the voltage across
the capacitor is the same as the output voltage (V(CO) = VO). This means no current is flowing into the C

O

branch. If IO suddenly increases (transient condition), the following occurs;
The LDO is not able to supply the sudden current need due to its response time (t1 in Figure 23). Therefore,

capacitor CO provides the current for the new load condition (dashed arrow). CO now acts like a battery with
an internal resistance, ESR. Depending on the current demand at the output, a voltage drop will occur at R

ESR

.

This voltage is shown as V

ESR

in Figure 22.

When CO is conducting current to the load, initial voltage at the load will be VO = V(CO) – V

ESR

. Due to the
discharge of CO, the output voltage VO will drop continuously until the response time t1 of the LDO is reached
and the LDO will resume supplying the load. From this point, the output voltage starts rising again until it reaches
the regulated voltage. This period is shown as t

2

in Figure 23.

The figure also shows the impact of different ESRs on the output voltage. The left brackets show different levels
of ESRs where number 1 displays the lowest and number 3 displays the highest ESR.

From above, the following conclusions can be drawn:

D

The higher the ESR, the larger the droop at the beginning of load transient.

D

The smaller the output capacitor, the faster the discharge time and the bigger the voltage droop during the
LDO response period.

TPS77901, TPS77918, TPS77925, TPS77930
250-mA LDO REGULATOR WITH INTEGRATED RESET IN A MSOP8 PACKAGE

SLVS283A – MARCH 2000 – REVISED MARCH 2000

16

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

conclusion

To minimize the transient output droop, capacitors must have a low ESR and be large enough to support the
minimum output voltage requirement.

ESR 1
ESR 2

ESR 3

3

1

2

t

1

t

2

I

O

V

O

Figure 23. – Correlation of Different ESRs and Their Influence to the Regulation of VO at a

Load Step From Low-to-High Output Current

TPS77901, TPS77918, TPS77925, TPS77930

250-mA LDO REGULATOR WITH INTEGRATED RESET IN A MSOP8 PACKAGE

SLVS283A – MARCH 2000 – REVISED MARCH 2000

17

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

programming the TPS77901 adjustable LDO regulator

The output voltage of the TPS77901 adjustable regulator is programmed using an external resistor divider as
shown in Figure 24. The output voltage is calculated using:

VO+

V

ref

ǒ1

)

R1
R2

Ǔ

(1)

Where:

V

ref

= 1.1834 V typ (the internal reference voltage)

Resistors R1 and R2 should be chosen for approximately 7-µA divider current. Lower value resistors can be
used but offer no inherent advantage and waste more power. Higher values should be avoided as leakage
currents at FB increase the output voltage error. The recommended design procedure is to choose
R2 = 30.1 kΩ to set the divider current at 7 µA and then calculate R1 using:

R1

+ ǒ

V

O

V

ref

*

1

Ǔ

R2

(2)

OUTPUT

VOLTAGE

R1 R2

2.5 V

3.3 V

3.6 V

UNIT

174
287
324

169
169
169

kΩ
kΩ
kΩ

OUTPUT VOLTAGE

PROGRAMMING GUIDE

V

O

V

I

RESET

OUT

FB/SENSE

R1

R2

GND

EN

IN

TPS77x01

RESET Output

0.1 µF
250 kΩ

C

O

NOTE: To reduce noise and prevent
oscillation, R1 and R2 need to be as close
as possible to the FB/SENSE terminal.

Figure 24. TPS77901 Adjustable LDO Regulator Programming

regulator protection

The TPS779xx PMOS-pass transistor has a built-in back diode that conducts reverse currents when the input
voltage drops below the output voltage (e.g., during power down). Current is conducted from the output to the
input and is not internally limited. When extended reverse voltage is anticipated, external limiting may be
appropriate.

The TPS779xx also features internal current limiting and thermal protection. During normal operation, the
TPS779xx limits output current to approximately 0.9 A. When current limiting engages, the output voltage scales
back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device
failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of
the device exceeds 150°C(typ), thermal-protection circuitry shuts it down. Once the device has cooled below
130°C(typ), regulator operation resumes.

TPS77901, TPS77918, TPS77925, TPS77930
250-mA LDO REGULATOR WITH INTEGRATED RESET IN A MSOP8 PACKAGE

SLVS283A – MARCH 2000 – REVISED MARCH 2000

18

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

power dissipation and junction temperature

Specified regulator operation is assured to a junction temperature of 125°C; the maximum junction temperature
should be restricted to 125°C under normal operating conditions. This restriction limits the power dissipation
the regulator can handle in any given application. T o ensure the junction temperature is within acceptable limits,
calculate the maximum allowable dissipation, P

D(max)

, and the actual dissipation, PD, which must be less than

or equal to P

D(max)

.

The maximum-power-dissipation limit is determined using the following equation:

P

D(max)

+

TJmax*T

A

R

q

JA

Where:

T

J

max is the maximum allowable junction temperature

T

A

is the ambient temperature.

R

θJA

is the thermal resistance junction-to-ambient for the package, i.e., 266.2°C/W for the 8-terminal

MSOP with no airflow.

The regulator dissipation is calculated using:

PD+

ǒ

VI*

V

O

Ǔ

I

O

Power dissipation resulting from quiescent current is negligible. Excessive power dissipation will trigger the
thermal protection circuit.

TPS77901, TPS77918, TPS77925, TPS77930

250-mA LDO REGULATOR WITH INTEGRATED RESET IN A MSOP8 PACKAGE

SLVS283A – MARCH 2000 – REVISED MARCH 2000

19

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

DGK (R-PDSO-G8) PLASTIC SMALL-OUTLINE PACKAGE

0,69

0,41

0,25

0,15 NOM

Gage Plane

4073329/B 04/98

4,98

0,25

5

3,05

4,78

2,95

8

4

3,05
2,95

1

0,38

1,07 MAX

Seating Plane

0,65

M

0,25

0°–6°

0,10

0,15
0,05

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC MO-187

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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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Of course, customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

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Copyright  2000, Texas Instruments Incorporated