TEXAS INSTRUMENTS TPS75003 Technical data

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IN1
IN2
IN3
EN1
SS1
EN2
SS2
EN3

IS1

SW 1

FB1

IS2

SW 2

FB2

OUT 3

FB3

DGN D

3A

BUC K1

3A

BUC K2

300mA

LDO
SS3
DGND

AGN D
DGND

TPS75003

+

+

V

CCAUX

2.5V @ 300m A

V

CCO

3.3V @ 3A

V

CCINT

1.2V @ 3A

V

CCAUX

5V_Input

Triple-Supply Power Management IC

for Powering FPGAs and DSPs

FEATURES DESCRIPTION

• Two 95% Efficient, 3A Buck Controllers and

One 300mA LDO

• Tested and Endorsed by Xilinx for Powering

the Spartan™-3, Spartan-3E and Spartan-3L
FPGAs

• Adjustable (1.2V to 6.5V for Bucks, 1.0V to

6.5V for LDO) Output Voltages on All
Channels

• Input Voltage Range: 2.2V to 6.5V

• Independent Soft-Start for Each Supply

• Independent Enable for Each Supply for

Flexible Sequencing

• LDO Stable with 2.2µF Ceramic Output Cap

• Small, Low-Profile 4.5mm x 3.5mm x 0.9mm

QFN Package

APPLICATIONS

• FPGA/DSP/ASIC Supplies

• Set-Top Boxes

• DSL Modems

• Plasma TV Display Panels

TPS75003

SBVS052D – OCTOBER 2004 – REVISED MARCH 2005

The TPS75003 is a complete power management
solution for FPGA, DSP and other multi-supply appli­cations. The device has been tested with and meets
all of the Xilinx Spartan-3, Spartan-3E and
Spartan-3L start-up profile requirements, including
monotonic voltage ramp and minimum voltage rail
rise time. Independent Enables for each output allow
sequencing to minimize demand on the power supply
at start-up. Soft-start on each supply limits inrush
current during start-up. Two integrated buck control­lers allow efficient, cost-effective voltage conversion
for both low and high current supplies such as core
and I/O. A 300mA LDO is integrated to provide an
auxiliary rail such as V
FPGA. All three supply voltages are offered in
user-programmable options for maximum flexibility.

The TPS75003 is fully specified from -40 ° C to +85 ° C
and is offered in a QFN package, yielding a highly
compact total solution size with high power dissi­pation capability.

on the Xilinx Spartan-3

CCAUX

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Spartan is a trademark of Xilinx, Inc.
All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Copyright © 2004–2005, Texas Instruments Incorporated

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TPS75003

SBVS052D – OCTOBER 2004 – REVISED MARCH 2005

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.

ORDERING INFORMATION

PRODUCT V

(1)

OUT

Buck1: Adjustable

TPS75003 Buck2: Adjustable

LDO: Adjustable

(1) For the most current specifications and package information, see the Package Option Addendum located at the end of this document, or

see the TI website at www.ti.com .

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

V

range (IN1, IN2, IN3) -0.3 to +7.0 V

INX

V

range (EN1, EN2, EN3) -0.3 to V

ENX

V

range (SW1, SW2, SW3) -0.3 to V

SWX

V

range (IS1, IS2, IS3) -0.3 to V

ISX

V

range -0.3 to +7.0 V

OUT3

V

range (SS1, SS2, SS3) -0.3 to V

SSX

V

range (FB1, FB2, FB3) -0.3 to +3.3 V

FBX

Peak LDO output current (I
Continuous total power dissipation See Dissipation Ratings Table —
Junction temperature range, T
Storage temperature range -65 to +150 ° C
ESD rating, HBM 1 kV
ESD rating, CDM 500 V

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics
is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.

) Internally limited —

OUT3

J

(1)

TPS75003 UNIT

+0.3 V

INX

+0.3 V

INX

+0.3 V

INX

+0.3 V

INX

-55 to +150 ° C

DISSIPATION RATINGS

BOARD R

Reference

(1)

Layout

Θ JA

44 22.7mW/ ° C 2.27W 1.25W 0.91W

(1) Refer to PCB Layout section. Internal power dissipation limits are determined by LDO operation: P

2

DERATING FACTOR TA≤ 25 ° C TA= 70 ° C TA= 85 ° C

ABOVE TA= 25 ° C POWER RATING POWER RATING POWER RATING

= (V

– V

) x I

DISS

IN3

OUT3

.

OUT3

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ELECTRICAL CHARACTERISTICS

V

= V

, V

= V

, V

= V

, V

= V

EN1

IN1

EN2

IN2

EN3

IN3

IN1

IN2

= 2.2V, V

TA= -40 ° C to +85 ° C, unless otherwise noted. Typical values are at TA= 25 ° C.

PARAMETER CONDITIONS MIN TYP MAX UNIT

Supply and Logic

V

INX

I

Q

I

SHDN

V

IH1, 2

V

IH3

V

ILX

I

ENX

Buck Controllers 1 and 2

V

OUT1,2

V

FB1,2

I

FB1,2

V

IS1,2

I

IS1,2

∆ V

/ ∆ V

OUT%

∆ V

/ ∆ I

OUT%

n

1,2

t

STR1,2

R

DS,ON1,2

I

SW1,2

t

ON

t

OFF

(1) To be in regulation, minimum V

components. Minimum V
(2) Maximum V
(3) Depends on external components.

Input Voltage Range (IN1, IN2,

(1)

IN3)
Quiescent Current, IQ= I

I

AGND

Shutdown Supply Current V

+

DGND

I

OUT1

EN1

Enable High, enabled
(EN1, EN2)

Enable High, enabled (EN3) 1.14 V
Enable Low, shutdown

(EN1, EN2, EN3)
Enable pin current (EN1, EN2,

EN3)

Adjustable Output Voltage

(2)

Range
Feedback Voltage (FB1, FB2) 1.220 V
Feedback Voltage Accuracy

(1)

(FB1, FB2)
Current into FB1, FB2 pins 0.01 0.5 µA
Reference Voltage for Current

Sense
Current into IS1, IS2 Pins 0.01 0.5 µA

Line Regulation

IN

Load Regulation 0.6 % / A

OUT

Efficiency

Startup Time

(1)

(3)

(3)

Gate Driver P-Channel and V
N-Channel MOSFET Ω
On-Resistance

Measured with the circuit in Figure 1 ,
V

OUT

Measured with the circuit in Figure 1 ,
30mA ≤ I

Measured with the circuit in Figure 1 ,
I

OUT

Measured with the circuit in Figure 1 ,
RL= 6 Ω , C

IN1,2

V

IN1,2

Gate Driver P-Channel and
N-Channel MOSFET Drive Current

Minimum On Time 1.36 1.55 1.84 µs
Minimum Off Time 0.44 0.65 0.86 µs

(or V

IN1

= V

IN3

is dependent on external components and will be less than VIN.

OUT

OUT3

) must be greater than V

IN2

+ V

or 2.2V, whichever is greater.

DO

= 3.0V, V

IN3

= I

= 0mA, I

OUT2

= V

= V

EN2

OUT3

OUT3

= 0V 0.05 3.0 µA

EN3

+ 0.5V ≤ VIN≤ 6.5V

≤ 2A

OUT

= 1A

= 100µF, C

OUT

> 2.5V 4
= 2.2V 6

OUT1,NOM

TPS75003

SBVS052D – OCTOBER 2004 – REVISED MARCH 2005

= 2.5V, C

= 1mA 75 150 µA

= 2.2nF

SS

(or V

OUT2,NOM

= C

OUT1

OUT2

= 47µF, C

2.2 6.5 V

1.4 V

0 0.3 V

0.01 0.5 µA

V

FBX

-2 +2 %

80 100 120 mV

0.1 % / V

94 %

5 ms

100 mA

) by an amount determined by external

= 2.2µF,

OUT3

INX

IN3

V

INX

V
V

V

3

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TPS75003

SBVS052D – OCTOBER 2004 – REVISED MARCH 2005

ELECTRICAL CHARACTERISTICS (continued)

V

= V

, V

= V

, V

= V

, V

= V

EN1

IN1

EN2

IN2

EN3

IN3

IN1

IN2

= 2.2V, V

TA= -40 ° C to +85 ° C, unless otherwise noted. Typical values are at TA= 25 ° C.

PARAMETER CONDITIONS MIN TYP MAX UNIT

LDO

V

OUT3

V

FB3

∆ V

/ ∆ V

OUT%

∆ V

/ ∆ I

OUT%

V

DO

I

CL3

I

FB3

V

n

t

SD

UVLO

Output Voltage Range 1.0 6.5 - V
Feedback Pin Voltage 0.507 V

2.95V ≤ V

Feedback Pin Voltage Accuracy
Line Regulation

IN

Load Regulation 10mA ≤ I

OUT

Dropout Voltage
(V

= V

IN

(4)

(5)

OUT(NOM)

- 0.1)

Current Limit V

(4)

1mA ≤ I
V

OUT3

I

OUT3

OUT

Current into FB3 pin 0.03 0.1 µA
Output Noise 400 µV

Thermal Shutdown Temperature
for LDO

BW = 100Hz - 100kHz,
I

OUT3

Shutdown, Temp Increasing 175

Reset, Temp Decreasing 160
Under-Voltage Lockout Threshold VINRising 1.80 V
Under-Voltage Lockout Hysteresis VINFalling 100 mV

= 3.0V, V

IN3

≤ 6.5V

IN3

≤ 300mA

OUT3

+ 0.5V ≤ V

≤ 300mA 0.01 % / mA

OUT3

OUT3

≤ 6.5V 0.075 % / V

IN3

= 300mA 250 350 mV
= 0.9 x V

OUT(NOM)

= 300mA

= 2.5V, C

= C

OUT1

OUT2

= 47µF, C

-4.0 +4.0 %

375 600 1000 mA

= 2.2µF,

OUT3

DO

V

RMS

° C

(4) To be in regulation, minimum V

components. Minimum V

(5) V

does not apply when V

DO

IN3

(or V

IN1

= V

OUT3

+ V

OUT

) must be greater than V

IN2

+ V

or 2.2V, whichever is greater.

DO

< 2.2V.

DO

OUT1,NOM

(or V

OUT2,NOM

) by an amount determined by external

4

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V

RE F1

Soft

Start

Control

Switch

Control

V

IS1

IS1

SW1

FB1

EN1

SS1

IN1

≤

3A Buck Controller

DGND

V

RE F2

Soft

Start

Control

Switch

Control

V

IS2

IS2

SW2

FB2

EN2

SS2

IN2

≤

3A Buck Controller

DGND

FB3

OUT3IN3

EN3

SS3

Thermal/
Current

Limit

300mA LDO

V

REF 3

AGND

TPS75003

TPS75003

SBVS052D – OCTOBER 2004 – REVISED MARCH 2005

DEVICE INFORMATION

Functional Block Diagram

5

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IN3

OUT3

FB1

FB2

20

1

11

10

DGND

SS3

AGND

EN1

SS1

DGND

SW1

IN1

IS1

19

18

17

16

15

14

13

12

FB3

EN3

EN2

SS2

DGND

SW2

IN2

IS2

2

3

4

5

6

7

8

9

RHL PACKAGE

4.5mm x 3.5mm QFN
(TOP VIEW)

TPS75003

SBVS052D – OCTOBER 2004 – REVISED MARCH 2005

DEVICE INFORMATION (continued)

TERMINAL

NAME RHL

DGND 6, 15, PAD
AGND 18 Ground connection for LDO.

IN1 13 Input supply to BUCK1.
IN2 8 Input supply to BUCK2.

IN3 20 Input supply to LDO.
EN1 17
EN2 4 Same as EN1 but for BUCK2 controller.

EN3 3 Same as EN1 but for LDO.

SS1 16 slowing the ramp-up of current limit. This high-impedance pin is noise-sensitive; careful layout is

SS2 5 Same as SS1 but for BUCK2 regulator.
SS3 19

IS1 12 to an internal reference to set current limit. For a robust output start-up ramp, careful layout and

IS2 9 Same as IS1 but compared to IN2 and used for BUCK2 controller.
SW1 14 Gate drive pin for external BUCK1 P-channel MOSFET.
SW2 7 Same as SW1 but for BUCK2 controller.

FB1 11 Feedback pin. Used to set the output voltage of BUCK1 regulator.
FB2 10 Same as FB1 but for BUCK2 controller.
FB3 2 Same as FB1 but for LDO.

OUT3 1

TERMINAL FUNCTIONS

DESCRIPTION

Ground connection for BUCK1 and BUCK2 converters. Pins 6 and 15 should be connected to the back
side exposed pad by a short metal trace as shown in the PCB Layout section of this data sheet.

Driving the enable pin (ENx) high turns on BUCK1 regulator. Driving this pin low puts it into shutdown
mode, reducing operating current. The enable pin does not trigger on fast negative going transients.

Connecting a capacitor between this pin and ground increases start-up time of the BUCK1 regulator by
important. See Typical Characteristics, Applications and PCB Layout sections for details.

Connecting a capacitor from this pin to ground slows the start-up time of the LDO reference, therby
slowing output voltage ramp-up. See Applications section for details.

Current sense input for BUCK1 regulator. The voltage difference between this pin and IN1 is compared
bypassing are required. See Applications section for details.

Regulated LDO output. A small ceramic capacitor ( ≥ 2.2µF) is needed from this pin to ground to ensure
stability.

6

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L1
5µH
Sumida
CDRH6D38−5R0

IN3

OUT3

FB1

FB2

20

1

11

10

DGND

SS3

AGND

EN1

SS1

DGND

SW1

IN1

IS1

19

18

17

16

15

14

13

12

FB3

EN3

EN2

SS2

DGND

SW2

IN2

IS2

2

3

4

5

6

7

8

9

R3

61.9k

Ω

R4

15.4k

Ω

EN3
EN2

V

IN

EN1

V

IN

1.5nF

1.5nF

0.01µF

R1
33m

Ω

10pF

100µF
Tantalum

100µF
Tantalum

Siliconix
Si2323DS

Siliconix
Si2323DS

Q2

L2
15µH
Sumida
CDRH8D43−150

V

CCINT

1.2V, 2A

Vishay
SS32
D2

0.1µF

1µF

V

CCAUX

2.5V, 300mA
10µF

0.1µF

R5

61.9k

Ω

ON Semiconductor

MBRM120

R6

36.5k

Ω

V

CCO

3.3V, 2A

R2
33m

Ω

100µF

V

IN

Q1

SBVS052D – OCTOBER 2004 – REVISED MARCH 2005

Typical Application Circuit for Powering the Xilinx Spartan-3 FPGA

TPS75003

Figure 1.

7

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0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

I

OUT

(A)

VIN= 3.3V
V

OUT

= 1.2V

TA= +85C

TA=−40C

TA= +25C

5
4
3
2
1
0

−

1

−

2

−

3

−

4

−

5

∆ V

OUT

(%)

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

I

OUT

(A)

VIN= 5V

V

OUT

= 3.3V

5
4
3
2
1
0

−

1

−

2

−

3

−

4

−

5

∆

V

OUT

(%)

TA= +85C

TA=−40C

TA= +25C

3.0
V

IN

(V)

5
4
3
2
1
0

−

1

−

2

−

3

−

4

−

5

∆

V

OUT

(

%)

V

OUT

= 3.3V

I

OUT

= 2A

3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0

TA= +85C

TA= +25C

TA=−40C

2.0
V

IN

(V)

5
4
3
2
1
0

−

1

−

2

−

3

−

4

−

5

∆

V

OUT

(

%)

V

OUT

= 1.2V

I

OUT

= 2A

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0

TA=−40C

TA= +25C

TA= +85C

0 0.5 1.0 1.5 2.0 2.5 3.0

500

400

300

200

100

0

Switching F

requency(kHz)

I

OUT

(A)

V

OUT

= 1.2V

VIN= 3.3V

VIN= 5.0V

−

40C
+25C
+85C

600

500

400

300

200

100

0

Switching Frequency (kHz)

0.01 0.1 1.0 10
I

OUT

(A)

VIN= 5.0V
V

OUT

= 1.2V

VIN= 3.3V

V

OUT

= 1.2V

VIN= 5.0V

V

OUT

= 3.3V

V

OUT

= 1.2V

VIN= 2.2V

TPS75003

SBVS052D – OCTOBER 2004 – REVISED MARCH 2005

Buck Converter

BUCK LOAD REGULATION BUCK LOAD REGULATION

Figure 2. Figure 3.

TYPICAL CHARACTERISTICS

Measured using circuit in Figure 1

BUCK LINE REGULATION BUCK LINE REGULATION

Figure 4. Figure 5.

BUCK SWITCHING FREQUENCY vs I

, T

OUT

A

BUCK SWITCHING FREQUENCY vs I

OUT

8

Figure 6. Figure 7.