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DCQ PACKAGE
SOT223
(TOP VIEW)
DBV PACKAGE
SOT23
(TOP VIEW)
IN
GND
EN
NR/FB
OUT
1
2
3
4
5
1 2 3 4 5
IN
OUT
GND
NR/FB
EN
TAB IS GND
IN
N/C
N/C
EN
8
7
6
5
OUT
N/C
NR/FB
GND
1
2
3
4
DRB PACKAGE
3mm x 3mm SON
(TOP VIEW)
TPS736xx
GNDEN NR
IN OUT
V
IN
V
OUT
Optional Optional
Optional
Typical Application Circuit for Fixed Voltage Versions
Cap-Free, NMOS, 400mA Low-Dropout Regulator
with Reverse Current Protection
FEATURES DESCRIPTION
• Stable with No Output Capacitor or Any Value
or Type of Capacitor
• Input Voltage Range of 1.7V to 5.5V
• Ultra-Low Dropout Voltage: 75mV typ
• Excellent Load Transient Response—with or
without Optional Output Capacitor
• New NMOS Topology Delivers Low Reverse
Leakage Current
• Low Noise: 30µV
• 0.5% Initial Accuracy
• 1% Overall Accuracy Over Line, Load, and
Temperature
• Less Than 1µA max IQin Shutdown Mode
• Thermal Shutdown and Specified Min/Max
Current Limit Protection
• Available in Multiple Output Voltage Versions
– Fixed Outputs of 1.20V to 4.3V
– Adjustable Output from 1.20V to 5.5V
– Custom Outputs Available
typ (10Hz to 100kHz)
RMS
TPS736xx
SBVS038K – SEPTEMBER 2003 – REVISED SEPTEMBER 2005
The TPS736xx family of low-dropout (LDO) linear
voltage regulators uses a new topology: an NMOS
pass element in a voltage-follower configuration. This
topology is stable using output capacitors with low
ESR, and even allows operation without a capacitor.
It also provides high reverse blockage (low reverse
current) and ground pin current that is nearly constant
over all values of output current.
The TPS736xx uses an advanced BiCMOS process
to yield high precision while delivering very low
dropout voltages and low ground pin current. Current
consumption, when not enabled, is under 1µA and
ideal for portable applications. The extremely low
output noise (30µV
powering VCOs. These devices are protected by
thermal shutdown and foldback current limit.
RMS
with 0.1µF C
) is ideal for
NR
APPLICATIONS
• Portable/Battery-Powered Equipment
• Post-Regulation for Switching Supplies
• Noise-Sensitive Circuitry such as VCOs
• Point of Load Regulation for DSPs, FPGAs,
ASICs, and Microprocessors
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2005, Texas Instruments Incorporated
www.ti.com
TPS736xx
SBVS038K – SEPTEMBER 2003 – REVISED SEPTEMBER 2005
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
ORDERING INFORMATION
PRODUCT V
TPS736 xxyyyz XX is nominal output voltage (for example, 25 = 2.5V, 01 = Adjustable
(1)
(2)
OUT
(3)
).
YYY is package designator.
Z is package quantity.
(1) For the most current specification and package information, refer to the Package Option Addendum located at the end of this datasheet
or see the TI website at www.ti.com .
(2) Additional output voltages from 1.25V to 4.3V in 100mV increments are available on a quick-turn basis using innovative factory
EEPROM programming. Minimum order quantities apply; contact factory for details and availability.
(3) For fixed 1.2V operation, tie FB to OUT.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
VINrange -0.3 to 6.0 V
V
range -0.3 to 6.0 V
EN
V
range -0.3 to 5.5 V
OUT
Peak output current Internally limited
Output short-circuit duration Indefinite
Continuous total power dissipation See Dissipation Ratings Table
Junction temperature range, T
Storage temperature range -65 to +150 °C
ESD rating, HBM 2 kV
ESD rating, CDM 500 V
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics
is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
J
(1)
TPS736xx UNIT
-55 to +150 °C
POWER DISSIPATION RATINGS
BOARD PACKAGE R
(2)
Low-K
(3)
High-K
(2)
Low-K
(3) (4)
High-K
DBV 64°C/W 255°C/W 3.9mW/°C 390mW 215mW 155mW
DBV 64°C/W 180°C/W 5.6mW/°C 560mW 310mW 225mW
DCQ 15°C/W 53°C/W 18.9mW/°C 1.89W 1.04W 0.76W
DRB 1.2°C/W 40°C/W 25.0mW/°C 2.50W 1.38W 1.0W
Θ JC
(1)
R
Θ JA
DERATING FACTOR TA≤ 25°C TA= 70°C TA= 85°C
ABOVE TA= 25°C POWER RATING POWER RATING POWER RATING
(1) See Power Dissipation in the Applications section for more information related to thermal design.
(2) The JEDEC Low-K (1s) board design used to derive this data was a 3inch x 3inch, 2-layer board with 2-ounce copper traces on top of
the board.
(3) The JEDEC High-K (2s2p) board design used to derive this data was a 3inch x 3inch, multilayer board with 1-ounce internal power and
ground planes and 2-ounce copper traces on the top and bottom of the board.
(4) Based on preliminary thermal simulations.
2
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TPS736xx
SBVS038K – SEPTEMBER 2003 – REVISED SEPTEMBER 2005
ELECTRICAL CHARACTERISTICS
Over operating temperature range (T
C
= 0.1µF, unless otherwise noted. Typical values are at TJ= 25°C.
OUT
= -40°C to +125°C), V
J
= V
IN
OUT(nom)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
IN
V
FB
Input voltage range
Internal reference (TPS73601) TJ= 25°C 1.198 1.20 1.210 V
(1) (2)
Output voltage range
(TPS73601)
V
OUT
Accuracy
∆ V
%/ ∆ V
OUT
∆ V
%/ ∆ I
OUT
V
DO
Line regulation
IN
Load regulation %/mA
OUT
Dropout voltage
(V
= V
IN
ZO(DO) Output impedance in dropout 1.7V ≤ VIN≤ V
I
CL
I
SC
I
REV
I
GND
I
SHDN
I
FB
PSRR dB
V
N
t
STR
Output current limit
Short-circuit current V
Reverse leakage current
Ground pin current µA
Shutdown current (I
FB pin current (TPS73601) 0.1 0.3 µA
Power-supply rejection ratio
(ripple rejection)
Output noise voltage
BW = 10Hz - 100KHz
Startup time 600 µs
Nominal TJ= 25°C -0.5 +0.5
(1)
over VIN, I
and T 10mA ≤ I
(1)
(3)
OUT(nom)
- 0.1V)
, V
OUT
+ 0.5V ≤ VIN≤ 5.5V;
OUT
V
O(nom)
1mA ≤ I
10mA ≤ I
I
OUT
V
OUT
≤ 400mA
OUT
+ 0.5V ≤ VIN≤ 5.5V 0.01 %/V
≤ 400mA 0.002
OUT
≤ 400mA 0.0005
OUT
= 400mA 75 200 mV
+ V
OUT
DO
= 0.9 × V
OUT(nom)
3.6V ≤ VIN≤ 4.2V, 0°C ≤ TJ≤ 70°C 500 800 mA
= 0V 450 mA
) V
IN
OUT
≤ 0.5V, 0V ≤ VIN≤ V
EN
I
= 10mA (IQ) 400 550
OUT
I
= 400mA 800 1000
OUT
≤ 0.5V, V
EN
f = 100Hz, I
f = 10KHz, I
C
OUT
C
OUT
V
OUT
C
= 0.01µF
NR
OUT
OUT
OUT
= 10µF, No C
= 10µF, C
= 3V, RL= 30 Ω C
OUT
≤ VIN≤ 5.5 0.02 1 µA
= 400mA 58
= 400mA 37
NR
= 0.01µF 8.5 × V
NR
= 1µF,
OUT
) V
GND
(4)
(-I
VEN(HI) Enable high (enabled) 1.7 V
VEN(LO) Enable low (shutdown) 0 0.5 V
IEN(HI) Enable pin current (enabled) V
T
SD
T
J
Thermal shutdown temperature °C
Operating junction temperature -40 125 °C
= 5.5V 0.02 0.1 µA
EN
Shutdown, temperature increasing 160
Reset, temperature decreasing 140
(1)
+ 0.5V
, I
OUT
= 10mA, V
= 1.7V, and
EN
1.7 5.5 V
V
FB
5.5 - V
DO
-1.0 ±0.5 +1.0
0.25 Ω
400 650 800 mA
0.1 10 µA
27 × V
OUT
OUT
IN
V
%
µV
RMS
V
(1) Minimum VIN= V
(2) For V
(3) V
(4) Refer to Applications section for more information.
OUT(nom)
this situation, disable the device before powering down the VIN.
is not measured for the TPS73615 (V
DO
+V
OUT
<1.6V, when VIN≤ 1.6V, the output will lock to VINand may result in a damaging over-voltage level on the output. To avoid
or 1.7V, whichever is greater.
DO
OUT(nom)
= 1.5V) since minimum VIN= 1.7V.
3
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Servo
Error
Amp
Ref
27k
Ω
8k
Ω
Current
Limit
Thermal
Protection
Bandgap
NR
OUT
R
1
R
2
EN
GND
IN
R
1
+ R2= 80k
Ω
4MHz
Charge Pump
V
O
1.2V
1.5V
1.8V
2.5V
2.8V
3.0V
3.3V
R
1
Short
23.2kΩ
28.0kΩ
39.2kΩ
44.2kΩ
46.4kΩ
52.3kΩ
R
2
Open
95.3kΩ
56.2kΩ
36.5kΩ
33.2kΩ
30.9kΩ
30.1kΩ
Table 1. Standard 1%
Resistor Values for
Common Output Voltages
NOTE: V
OUT
= (R1 + R2)/R2 × 1.2 04;
R1R2 ≅ 19kΩ for best
accuracy.
Servo
Error
Amp
Ref
Current
Limit
Thermal
Protection
Bandgap
OUT
FB
R
1
R
2
EN
GND
IN
80k
Ω
8k
Ω
27k
Ω
4MHz
Charge Pump
TPS736xx
SBVS038K – SEPTEMBER 2003 – REVISED SEPTEMBER 2005
FUNCTIONAL BLOCK DIAGRAMS
4
Figure 1. Fixed Voltage Version
Figure 2. Adjustable Voltage Version
www.ti.com
DCQ PACKAGE
SOT223
(TOP VIEW)
1 2 3 4 5
IN
OUT
GND
NR/FB
EN
DBV PACKAGE
SOT23
(TOP VIEW)
IN
GND
EN NR/FB
OUT1
2
3 4
5
TAB IS GND
IN
N/C
N/C
EN
8
7
6
5
OUT
N/C
NR/FB
GND
1
2
3
4
DRB PACKAGE
3mm x 3mm SON
(TOP VIEW)
TPS736xx
SBVS038K – SEPTEMBER 2003 – REVISED SEPTEMBER 2005
PIN ASSIGNMENTS
Terminal Functions
SOT23 SOT223 3x3 SON
NAME PIN NO. PIN NO. PIN NO. DESCRIPTION
IN 1 1 8 Unregulated input supply
GND 2 3 4, Pad Ground
EN 3 5 5 Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the
NR 4 4 3 Fixed voltage versions only—connecting an external capacitor to this pin bypasses
FB 4 4 3 Adjustable voltage version only—this is the input to the control loop error amplifier,
OUT 5 2 1 Output of the Regulator. There are no output capacitor requirements for stability.
(DBV) (DCQ) (DRB)
regulator into shutdown mode. Refer to the Shutdown section under Applications
Information for more details. EN can be connected to IN if not used.
noise generated by the internal bandgap, reducing output noise to very low levels.
and is used to set the output voltage of the device.
5
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0.5
0.4
0.3
0.2
0.1
0
−
0.1
−
0.2
−
0.3
−
0.4
−
0.5
Change in V
OUT
(%)
0 50 100 150 300 350200 250 400
I
OUT
(mA)
Referred to I
OUT
= 10mA
−
40C
+125C
+25C
0.20
0.15
0.10
0.05
0
−
0.05
−
0.10
−
0.15
−
0.20
Change in V
OUT
(%)
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
V
IN
−
V
OUT
(V)
+125C
+25C
−
40C
Referred to VIN= V
OUT
+ 0.5V at I
OUT
= 10mA
100
80
60
40
20
0
V
DO
(mV)
0 50 100 150 200 400250 300 350
I
OUT
(mA)
+125C
+25C
−
40C
TPS73625DBV
100
80
60
40
20
0
V
DO
(mV)
−
50−25 0 25 50 75 100 125
Temperature (C)
TPS73625DBV
30
25
20
15
10
5
0
Percent of Units (%)
−
1.0
−
0.9
−
0.8
−
0.7
−
0.6
−
0.5
−
0.4
−
0.3
−
0.2
−
0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
V
OUT
Error (%)
I
OUT
= 10mA
18
16
14
12
10
8
6
4
2
0
Percent of Units (%)
−
100
−
90
−
80
−
70
−
60
−
50
−
40
−
30
−
20
−
10
0
10
20
30
40
50
60
70
80
90
100
Worst Case dV
OUT
/dT (ppm/C)
I
OUT
= 10mA
All VoltageVersions
TPS736xx
SBVS038K – SEPTEMBER 2003 – REVISED SEPTEMBER 2005
For all voltage versions, at TJ= +25°C, V
LOAD REGULATION LINE REGULATION
Figure 3. Figure 4.
DROPOUT VOLTAGE vs OUTPUT CURRENT DROPOUT VOLTAGE vs TEMPERATURE
TYPICAL CHARACTERISTICS
= V
IN
OUT(nom)
+ 0.5V, I
noted.
OUT
= 10mA, V
= 1.7V, and C
EN
OUT
= 0.1µF, unless otherwise
OUTPUT VOLTAGE ACCURACY HISTOGRAM OUTPUT VOLTAGE DRIFT HISTOGRAM
6
Figure 5. Figure 6.
Figure 7. Figure 8.
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1000
900
800
700
600
500
400
300
200
100
0
I
GND
(
µ
A)
0 100 200 300 400
I
OUT
(mA)
VIN= 5.5V
VIN= 4V
VIN= 2V
1000
900
800
700
600
500
400
300
200
100
0
I
GND
(
µ
A)
−
50−25 0 25 50 75 100 125
Temperature (C)
I
OUT
= 400mA
VIN= 5.5V
VIN= 3V
VIN= 2V
800
700
600
500
400
300
200
100
0
Current Limit (mA)
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
V
OUT
(V)
TPS73633
I
CL
I
SC
1
0.1
0.01
I
GND
(
µ
A)
−
50−25 0 25 50 75 100 125
Temperature (C)
V
ENABLE
= 0.5V
VIN= VO+ 0.5V
800
750
700
650
600
550
500
450
400
Current Limit (mA)
1.5 2.5 3.0 3.5 4.0 4.5 5.02.0 5.5
V
IN
(V)
800
750
700
650
600
550
500
450
400
Current Limit (mA)
−
50−25 0 25 50 75 100 125
Temperature (C)
TYPICAL CHARACTERISTICS (continued)
For all voltage versions, at TJ= +25°C, V
noted.
GROUND PIN CURRENT vs OUTPUT CURRENT GROUND PIN CURRENT vs TEMPERATURE
Figure 9. Figure 10.
TPS736xx
SBVS038K – SEPTEMBER 2003 – REVISED SEPTEMBER 2005
= V
IN
OUT(nom)
+ 0.5V, I
OUT
= 10mA, V
= 1.7V, and C
EN
OUT
= 0.1µF, unless otherwise
CURRENT LIMIT vs V
(FOLDBACK) vs TEMPERATURE
OUT
Figure 11. Figure 12.
CURRENT LIMIT vs V
IN
GROUND PIN CURRENT in SHUTDOWN
CURRENT LIMIT vs TEMPERATURE
Figure 13. Figure 14.
7
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40
35
30
25
20
15
10
5
0
PSRR (dB)
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
V
IN
−
V
OUT
(V)
Frequency = 100kHz
C
OUT
= 10µF
V
OUT
= 2.5V
10k10
90
80
70
60
50
40
30
20
10
0
Ripple Rejection (dB)
100 1k 100k 1M 10M
Frequency (Hz)
I
OUT
= 1mA
C
OUT
= 1µF
I
OUT
= Any
C
OUT
= 0µF
I
OUT
= 1mA
C
OUT
= Any
I
OUT
= 1mA
C
OUT
= 10µF
I
OUT
= 100mA
C
OUT
= Any
I
OUT
= 100mA
C
OUT
= 10µF
IO=100mA
CO=1µF
1
0.1
0.01
e
N
(
µ
V/
√
Hz)
10 100 1k 10k 100k
Frequency (Hz)
C
OUT
= 1µF
C
OUT
= 0µF
C
OUT
= 10µF
I
OUT
= 150mA
1
0.1
0.01
e
N
(
µ
V/
√
Hz)
10 100 1k 10k 100k
Frequency (Hz)
I
OUT
= 150mA
C
OUT
= 1µF
C
OUT
= 0µF
C
OUT
= 10µF
60
50
40
30
20
10
0
V
N
(RMS)
C
OUT
(µF)
0.1 1 10
V
OUT
= 5.0V
V
OUT
= 3.3V
V
OUT
= 1.5V
CNR= 0.01µF
10Hz < Frequency <100kHz
140
120
100
80
60
40
20
0
V
N
(RMS)
CNR(F)
1p 10p 100p 1n 10n
V
OUT
= 5.0V
V
OUT
= 3.3V
V
OUT
= 1.5V
C
OUT
= 0µF
10Hz < Frequency < 100kHz
TPS736xx
SBVS038K – SEPTEMBER 2003 – REVISED SEPTEMBER 2005
TYPICAL CHARACTERISTICS (continued)
For all voltage versions, at TJ= +25°C, V
noted.
= V
IN
OUT(nom)
+ 0.5V, I
OUT
= 10mA, V
= 1.7V, and C
EN
OUT
= 0.1µF, unless otherwise
PSRR (RIPPLE REJECTION) vs FREQUENCY PSRR (RIPPLE REJECTION) vs VIN– V
Figure 15. Figure 16.
NOISE SPECTRAL DENSITY NOISE SPECTRAL DENSITY
C
= 0 µ F C
NR
NR
= 0.01 µ F
OUT
Figure 17. Figure 18.
RMS NOISE VOLTAGE vs C
8
Figure 19. Figure 20.
OUT
RMS NOISE VOLTAGE vs C
NR
www.ti.com
10µs/div
100mV/tick
50mV/tick
20mV/tick
50mA/tick
V
IN
= 3.8V C
OUT
= 0µF
C
OUT
= 1µF
C
OUT
= 10µF
10mA
400mA
V
OUT
V
OUT
V
OUT
I
OUT
10µs/div
50mV/div
50mV/div
1V/div
V
OUT
V
OUT
V
IN
I
OUT
= 400mA
5.5V
4.5V
dV
IN
dt
= 0.5V/µs
C
OUT
= 0µF
C
OUT
= 100µF
100µs/div
1V/div
1V/div
RL= 20
Ω
C
OUT
= 10µF
2V
0V
RL= 1k
Ω
C
OUT
= 0µF
RL= 20
Ω
C
OUT
= 1µF
V
OUT
V
EN
100µs/div
1V/div
1V/div
RL= 20Ω
C
OUT
= 10µF
2V
0V
RL= 1k
Ω
C
OUT
= 0µF
RL= 20
Ω
C
OUT
= 1µF
V
OUT
V
EN
6
5
4
3
2
1
0
−
1
−
2
Volts
50ms/div
V
IN
V
OUT
10
1
0.1
0.01
I
ENABLE
(nA)
−
50−25 0 25 50 75 100 125
Temperature (C)
TYPICAL CHARACTERISTICS (continued)
For all voltage versions, at TJ= +25°C, V
noted.
TPS736xx
SBVS038K – SEPTEMBER 2003 – REVISED SEPTEMBER 2005
= V
IN
OUT(nom)
+ 0.5V, I
OUT
= 10mA, V
= 1.7V, and C
EN
OUT
= 0.1µF, unless otherwise
LOAD TRANSIENT RESPONSE LINE TRANSIENT RESPONSE
TPS73633 TPS73633
Figure 21. Figure 22.
TPS73633 TPS73633
TURN-ON RESPONSE TURN-OFF RESPONSE
POWER UP / POWER DOWN
Figure 23. Figure 24.
TPS73633 I
Figure 25. Figure 26.
ENABLE
vs TEMPERATURE
9
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60
55
50
45
40
35
30
25
20
V
N
(rms)
CFB(F)
10p 100p 1n 10n
V
OUT
= 2.5V
C
OUT
= 0µF
R1= 39.2k
Ω
10Hz < Frequency < 100kHz
160
140
120
100
80
60
40
20
0
I
FB
(nA)
−
50−25 0 25 50 75 100 125
Temperature (C)
25µs/div
200mV/div
200mV/div
V
OUT
V
OUT
I
OUT
400mA
10mA
C
OUT
= 0µF
CFB= 10nF
R1= 39.2k
Ω
C
OUT
= 10µF
5µs/div
100mV/div
100mV/div
V
OUT
V
OUT
V
IN
4.5V
3.5V
C
OUT
= 0µF
V
OUT
= 2.5V
CFB= 10nF
C
OUT
= 10µF
TPS736xx
SBVS038K – SEPTEMBER 2003 – REVISED SEPTEMBER 2005
TYPICAL CHARACTERISTICS (continued)
For all voltage versions, at TJ= +25°C, V
noted.
= V
IN
OUT(nom)
+ 0.5V, I
OUT
= 10mA, V
= 1.7V, and C
EN
OUT
= 0.1µF, unless otherwise
RMS NOISE VOLTAGE vs C
ADJ
IFBvs TEMPERATURE
Figure 27. Figure 28.
TPS73601 TPS73601
LOAD TRANSIENT, ADJUSTABLE VERSION LINE TRANSIENT, ADJUSTABLE VERSION
TPS73601 TPS73601
10
Figure 29. Figure 30.
www.ti.com
TPS736xx
GNDEN NR
IN OUT
V
IN
V
OUT
Optional input capacitor.
May improve source
impedance, noise, or PSRR.
Optional output capacitor.
May improve load transient,
noise, or PSRR.
Optional bypass
capacitor to reduce
output noise.
VN 32V
RMS
(R
1
R2)
R
2
32V
RMS
V
OUT
V
REF
VN(V
RMS
) 27
V
RMS
V
V
OUT
(V)
TPS736xx
GNDEN FB
IN OUT
V
IN
V
OUT
V
OUT
=
×
1.204
(R1+ R2)
R
1
R1C
FB
R
2
Optional input capacitor.
May improve source
impedance, noise, or PSRR.
Optional output capacitor.
May improve load transient,
noise, or PSRR.
Optional capacitor
reduces output noise
and improves
transient response.
VN(V
RMS
) 8.5
V
RMS
V
V
OUT
(V)
TPS736xx
SBVS038K – SEPTEMBER 2003 – REVISED SEPTEMBER 2005
APPLICATION INFORMATION
The TPS736xx belongs to a family of new generation
LDO regulators that use an NMOS pass transistor to
achieve ultra-low-dropout performance, reverse current blockage, and freedom from output capacitor
constraints. These features, combined with low noise
and an enable input, make the TPS736xx ideal for
portable applications. This regulator family offers a
wide selection of fixed output voltage versions and an
adjustable output version. All versions have thermal
and over-current protection, including foldback current limit.
Figure 31 shows the basic circuit connections for the
fixed voltage models. Figure 32 gives the connections
for the adjustable output version (TPS73601). R
R
can be calculated for any output voltage using the
2
1
formula in Figure 32 . Sample resistor values for
common output voltages are shown in Figure 2 . For
best accuracy, make the parallel combination of R
and R
approximately 19k Ω .
2
Figure 31. Typical Application Circuit for
Fixed-Voltage Versions
Input and Output Capacitor Requirements
Although an input capacitor is not required for stability, it is good analog design practice to connect a
0.1µF to 1µF low ESR capacitor across the input
supply near the regulator. This will counteract reactive input sources and improves transient response,
noise rejection, and ripple rejection. A higher-value
capacitor may be necessary if large, fast rise-time
load transients are anticipated or the device is located several inches from the power source.
The TPS736xx does not require an output capacitor
for stability and has maximum phase margin with no
and
capacitor. It is designed to be stable for all available
types and values of capacitors. In applications where
V
– V
IN
< 0.5V and multiple low ESR capacitors
OUT
are in parallel, ringing may occur when the product of
C
1
and total ESR drops below 50n Ω F. Total ESR
OUT
includes all parasitic resistances, including capacitor
ESR and board, socket, and solder joint resistance.
In most applications, the sum of capacitor ESR and
trace resistance will meet this requirement.
Output Noise
A precision band-gap reference is used to generate
the internal reference voltage, V
the dominant noise source within the TPS736xx and
it generates approximately 32µV
100kHz) at the reference output (NR). The regulator
control loop gains up the reference noise with the
same gain as the reference voltage, so that the noise
voltage of the regulator is approximately given by:
. This reference is
REF
RMS
(10Hz to
Figure 32. Typical Application Circuit for
Adjustable-Voltage Versions
(1)
Since the value of V
is 1.2V, this relationship
REF
reduces to:
(2)
for the case of no C
.
NR
An internal 27k Ω resistor in series with the noise
reduction pin (NR) forms a low-pass filter for the
voltage reference when an external noise reduction
capacitor, C
C
= 10nF, the total noise in the 10Hz to 100kHz
NR
, is connected from NR to ground. For
NR
bandwidth is reduced by a factor of ~3.2, giving the
approximate relationship:
for C
= 10nF.
NR
(3)
11
www.ti.com
(Fixed Voltage Version)
dVdt
V
OUT
C
OUT
80k R
LOAD
(Adjustable Voltage Vers ion)
dVdt
V
OUT
C
OUT
80k (R1 R
2
)
R
LOAD
TPS736xx
SBVS038K – SEPTEMBER 2003 – REVISED SEPTEMBER 2005
This noise reduction effect is shown as RMS Noise For large step changes in load current, the TPS736xx
Voltage vs C
The TPS73601 adjustable version does not have the
noise-reduction pin available. However, connecting a
feedback capacitor, C
pin will reduce output noise and improve load transient performance. Operating in the transient dropout region can cause
The TPS736xx uses an internal charge pump to
develop an internal supply voltage sufficient to drive
the gate of the NMOS pass element above V
charge pump generates ~250µV of switching noise at
~4MHz; however, charge-pump noise contribution is
negligible at the output of the regulator for most
values of I
Board Layout Recommendation to Improve PSRR and Noise Performance
To improve ac performance such as PSRR, output
noise, and transient response, it is recommended that
the board be designed with separate ground planes
for V
and V
IN
only at the GND pin of the device. In addition, the
ground connection for the bypass capacitor should
connect directly to the GND pin of the device.
Internal Current Limit
The TPS736xx internal current limit helps protect the
regulator during fault conditions. Foldback helps to
protect the regulator from damage during output
short-circuit conditions by reducing current limit when
V
drops below 0.5V. See Figure 11 in the Typical
OUT
Characteristics section for a graph of I
Shutdown
The Enable pin is active high and is compatible with
standard TTL-CMOS levels. V
turns the regulator off and drops the ground pin
current to approximately 10nA. When shutdown capability is not required, the Enable pin can be connected
to VIN. When a pull-up resistor is used, and operation
down to 1.8V is required, use pull-up resistor values
below 50k Ω .
in the Typical Characteristics section. requires a larger voltage drop from V
NR
avoid degraded transient response. The boundary of
this transient dropout region is approximately twice
, from the output to the FB
FB
the dc dropout. Values of V
insure normal transient response.
an increase in recovery time. The time required to
recover from a load transient is a function of the
. The
OUT
magnitude of the change in load current rate, the rate
of change in load current, and the available headroom (V
to V
IN
voltage drop). Under worst-case
OUT
conditions [full-scale instantaneous load change with
(V
- V
and C
OUT
.
OUT
IN
can take a couple of hundred microseconds to return
) close to dc dropout levels], the TPS736xx
OUT
to the specified regulation accuracy.
Transient Response
The low open-loop output impedance provided by the
NMOS pass element in a voltage follower configur-
, with each ground plane connected
OUT
EN
OUT
below 0.5V (max)
vs V
.
OUT
ation allows operation without an output capacitor for
many applications. As with any regulator, the addition
of a capacitor (nominal value 1µF) from the output pin
to ground will reduce undershoot magnitude but
increase duration. In the adjustable version, the
addition of a capacitor, C
adjust pin will also improve the transient response.
The TPS736xx does not have active pull-down when
the output is over-voltage. This allows applications
that connect higher voltage sources, such as alternate power supplies, to the output. This also results
in an output overshoot of several percent if load
current quickly drops to zero when a capacitor is
connected to the output. The duration of overshoot
can be reduced by adding a load resistor. The
overshoot decays at a rate determined by output
capacitor C
and the internal/external load resist-
OUT
ance. The rate of decay is given by:
IN
- V
IN
, from the output to the
FB
OUT
above this line
to V
to
OUT
(4)
Dropout Voltage
The TPS736xx uses an NMOS pass transistor to
achieve extremely low dropout. When (V
less than the dropout voltage (V
device is in its linear region of operation and the
input-to-output resistance is the R
pass element.
12
(5)
- V
IN
), the NMOS pass
DO
of the NMOS
DS-ON
) is
OUT
www.ti.com
PD (VIN V
OUT
) I
OUT
TPS736xx
SBVS038K – SEPTEMBER 2003 – REVISED SEPTEMBER 2005
Reverse Current
expected ambient temperature and worst-case load.
The NMOS pass element of the TPS736xx provides The internal protection circuitry of the TPS736xx has
inherent protection against current flow from the been designed to protect against overload conditions.
output of the regulator to the input when the gate of It was not intended to replace proper heat sinking.
the pass device is pulled low. To ensure that all Continuously running the TPS736xx into thermal
charge is removed from the gate of the pass element, shutdown will degrade reliability.
the enable pin must be driven low before the input
voltage is removed. If this is not done, the pass
element may be left on due to stored charge on the
gate.
After the enable pin is driven low, no bias voltage is
needed on any pin for reverse current blocking. Note
that reverse current is specified as the current flowing
out of the IN pin due to voltage applied on the OUT
pin. There will be additional current flowing into the
OUT pin due to the 80k Ω internal resistor divider to
ground (see Figure 1 and Figure 2 ).
For the TPS73601, reverse current may flow when
V
is more than 1.0V above V
FB
.
IN
Power Dissipation
The ability to remove heat from the die is different for
each package type, presenting different considerations in the PCB layout. The PCB area around the
device that is free of other components moves the
heat from the device to the ambient air. Performance
data for JEDEC low and high K boards are shown in
the Power Dissipation Ratings table. Using heavier
copper will increase the effectiveness in removing
heat from the device. The addition of plated
through-holes to heat-dissipating layers will also improve the heat-sink effectiveness.
Power dissipation depends on input voltage and load
Thermal Protection
Thermal protection disables the output when the
junction temperature rises to approximately 160°C,
conditions. Power dissipation is equal to the product
of the output current times the voltage drop across
the output pass element (V
to V
IN
):
OUT
allowing the device to cool. When the junction temperature cools to approximately 140°C, the output
circuitry is again enabled. Depending on power dissipation, thermal resistance, and ambient temperature,
the thermal protection circuit may cycle on and off.
Power dissipation can be minimized by using the
lowest possible input voltage necessary to assure the
required output voltage.
This limits the dissipation of the regulator, protecting
it from damage due to overheating.
Any tendency to activate the thermal protection circuit
indicates excessive power dissipation or an inadequate heat sink. For reliable operation, junction
temperature should be limited to 125°C maximum. To
estimate the margin of safety in a complete design
Package Mounting
Solder pad footprint recommendations for the
TPS736xx are presented in Application Bulletin
Solder Pad Recommendations for Surface-Mount De-
vices (AB-132), available from the Texas Instruments
web site at www.ti.com .
(including heat sink), increase the ambient temperature until the thermal protection is triggered; use
worst-case loads and signal conditions. For good
reliability, thermal protection should trigger at least
35°C above the maximum expected ambient condition of your application. This produces a worst-case
junction temperature of 125°C at the highest
(6)
13
PACKAGE OPTION ADDENDUM
www.ti.com
PACKAGING INFORMATION
Orderable Device Status
TPS73601DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
TPS73601DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
TPS73601DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS &
TPS73601DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS &
TPS73601DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS &
TPS73601DCQG4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS &
TPS73601DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS &
TPS73601DCQRG4 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS &
TPS73601DRBR ACTIVE SON DRB 8 3000 Green (RoHS &
TPS73601DRBRG4 ACTIVE SON DRB 8 3000 Green (RoHS &
TPS73601DRBT ACTIVE SON DRB 8 250 Green (RoHS &
TPS73601DRBTG4 ACTIVE SON DRB 8 250 Green (RoHS &
TPS736125DRBR ACTIVE SON DRB 8 3000 Green (RoHS &
TPS736125DRBRG4 ACTIVE SON DRB 8 3000 Green (RoHS &
TPS736125DRBT ACTIVE SON DRB 8 250 Green (RoHS &
TPS736125DRBTG4 ACTIVE SON DRB 8 250 Green (RoHS &
TPS73615DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
TPS73615DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
TPS73615DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS &
TPS73615DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS &
TPS73615DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS &
TPS73615DCQG4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS &
TPS73615DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS &
TPS73615DCQRG4 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS &
TPS73615DRBR ACTIVE SON DRB 8 3000 Green (RoHS &
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
(2)
Lead/Ball Finish MSL Peak Temp
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
Call TI Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
27-Feb-2006
(3)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
TPS73615DRBRG4 ACTIVE SON DRB 8 3000 Green (RoHS &
no Sb/Br)
TPS73615DRBT ACTIVE SON DRB 8 250 Green (RoHS &
no Sb/Br)
TPS73615DRBTG4 ACTIVE SON DRB 8 250 Green (RoHS &
no Sb/Br)
TPS73618DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br)
TPS73618DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br)
TPS73618DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS &
no Sb/Br)
TPS73618DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS &
no Sb/Br)
TPS73618DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS &
no Sb/Br)
TPS73618DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS &
no Sb/Br)
TPS73618DCQRG4 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS &
no Sb/Br)
TPS73625DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br)
TPS73625DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br)
TPS73625DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS &
no Sb/Br)
TPS73625DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS &
no Sb/Br)
TPS73625DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS &
no Sb/Br)
TPS73625DCQG4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS &
no Sb/Br)
TPS73625DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS &
no Sb/Br)
TPS73625DCQRG4 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS &
no Sb/Br)
TPS73630DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br)
TPS73630DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br)
TPS73630DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS &
no Sb/Br)
TPS73630DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS &
no Sb/Br)
TPS73630DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS &
no Sb/Br)
TPS73630DCQG4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS &
no Sb/Br)
TPS73630DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS &
no Sb/Br)
TPS73630DCQRG4 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS &
no Sb/Br)
27-Feb-2006
Lead/Ball Finish MSL Peak Temp
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
Call TI Level-2-260C-1 YEAR
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
(3)
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
TPS73632DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
Lead/Ball Finish MSL Peak Temp
CU NIPDAU Level-1-260C-UNLIM
27-Feb-2006
(3)
no Sb/Br)
TPS73632DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS73632DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS73632DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS73633DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS73633DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS73633DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS73633DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS73633DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS &
CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS73633DCQG4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS &
CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS73633DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS &
CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS73633DCQRG4 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS &
CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS73633DRBR ACTIVE SON DRB 8 3000 Green (RoHS &
CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS73633DRBRG4 ACTIVE SON DRB 8 3000 Green (RoHS &
CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS73633DRBT ACTIVE SON DRB 8 250 Green (RoHS &
CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS73633DRBTG4 ACTIVE SON DRB 8 250 Green (RoHS &
CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS73643DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS73643DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS73643DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS &
CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS73643DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS &
CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
27-Feb-2006
Addendum-Page 4
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
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