TEXAS INSTRUMENTS TPS735xx Technical data

DRBPACKAGE
3mmx3mmSON
(TOPVIEW)
8
7
6
5
OUT
N/C
NR/FB
IN
N/C
N/C
EN
1
2
3
4
GND
DRVPACKAGE
2mmx2mmSON
IN
N/C
EN
6
5
4
OUT
NR/FB
GND
1
2
3
GND
(TOPVIEW)
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TPS735xx
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500mA, Low Quiescent Current, Ultra-Low Noise, High PSRR
Low Dropout Linear Regulator
1
FEATURES
2
500mA Low Dropout Regulator with EN
Low IQ: 46μA
Multiple Output Voltage Versions Available: – Fixed Outputs of 1.0V to 4.3V Using
Innovative Factory EEPROM Programming
– Adjustable Outputs from 1.25V to 6.0V
High PSRR: 60dB at 1kHz
Ultra-low Noise: 28μV
Fast Start-Up Time: 45μs
Stable with a Low-ESR, 2.0μF Typical Output Capacitance
Excellent Load/Line Transient Response
2% Overall Accuracy (Load/Line/Temp, V
> 2.2V)
OUT
Very Low Dropout: 280mV at 500mA
2mm × 2mm SON-6 and 3mm × 3mm SON-8 Packages
RMS
SBVS087H –JUNE 2008–REVISED NOVEMBER 2009
DESCRIPTION
The TPS735xx family of low-dropout (LDO), low-power linear regulators offers excellent ac performance with very low ground current. High power-supply rejection ratio (PSRR), low noise, fast start-up, and excellent line and load transient response are provided while consuming a very low 46μA (typical) ground current. The TPS735xx is stable with ceramic capacitors and uses an advanced BiCMOS fabrication process to yield a typical dropout voltage of 250mV at 500mA output. The TPS735xx uses a precision voltage reference and feedback loop to achieve overall accuracy of 2% (V all load, line, process, and temperature variations. It is fully specified from TJ= –40°C to +125°C and is offered in low-profile, 2mm x 2mm SON and 3mm × 3mm SON packages that are ideal for wireless handsets, printers, and WLAN cards.
> 2.2V) over
OUT
APPLICATIONS
WiFi, WiMax
Printers
Cellular Phones, SmartPhones
Handheld Organizers, PDAs
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 2008–2009, Texas Instruments Incorporated
TPS735xx
SBVS087H –JUNE 2008–REVISED NOVEMBER 2009
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
PRODUCT V
(1)
OUT
(2)
TPS735xx yyy z XX is nominal output voltage (for example, 28 = 2.8V, 285 = 2.85V, 01 = Adjustable).
YYY is package designator. Z is package quantity.
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) Output voltages from 1.0V to 3.6V in 50mV increments are available through the use of innovative factory EEPROM programming;
minimum order quantities may apply. Contact factory for details and availability.
ABSOLUTE MAXIMUM RATINGS
Over operating temperature range (unless otherwise noted).
PARAMETER TPS735xx UNIT
VINrange –0.3 to +7.0 V VENrange –0.3 to VIN+0.3 V V
range –0.3 to VIN+0.3 V
OUT
VFBrange –0.3 to VFB(TYP) +0.3 V Peak output current Internally limited Continuous total power dissipation See Dissipation Ratings Table Junction temperature range, T Storage temperature range , T ESD rating, HBM 2 kV ESD rating, CDM 500 V
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.
J
STG
(1)
–55 to +150 °C –55 to +150 °C
DISSIPATION RATINGS
BOARD PACKAGE R
(1)
Low-K
High-K
High-K
(2)
(2) (3)
DRV 20°C/W 140°C/W 7.1mW/°C 715mW 395mW 285mW DRV 20°C/W 65°C/W 15.4mW/°C 1.54W 845mW 615mW DRB 1.2°C/W 40°C/W 25mW/°C 2.5W 1.38W 1.0W
θJC
R
θJA
(1) The JEDEC low-K (1s) board used to derive this data was a 3in × 3in (7,62cm × 7,62cm), two-layer board with 2-ounce (56,699g)
copper traces on top of the board.
(2) The JEDEC high-K (2s2p) board used to derive this data was a 3in × 3in (7,62cm × 7,62cm), multilayer board with 1-ounce (28,35g)
internal power and ground planes and 2-ounce (56,699g) copper traces on top and bottom of the board.
(3) The R
value of the DRB package is junction-to-pad; note that this is not junction-to-case (top center of IC package).
θJC
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DERATING FACTOR
ABOVE TA= +25°C TA< +25°C TA= +70°C TA= +85°C
TPS735xx
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ELECTRICAL CHARACTERISTICS
Over operating temperature range (TJ= –40°C to +125°C), VIN= V VEN= VIN, C Typical values are at TJ= +25°C.
V
IN
V
FB
V
OUT
V
OUT
V
OUT
ΔV
%/ ΔVINLine regulation
OUT
ΔV
%/ ΔI
OUT
V
DO
I
CL
I
GND
I
SHDN
I
FB
PSRR VIN= 3.85V, V
V
N
T
STR
V
EN(HI)
V
EN(LO)
I
EN(HI)
T
SD
T
UVLO
(1) Minimum VIN= V (2) VDOis not measured for devices with V
= 2.2μF, CNR= 0.01μF, unless otherwise noted. For TPS73501, V
OUT
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input voltage range
(1)
Internal reference (TPS73501) 1.184 1.208 1.232 V Output voltage range (TPS73501) V Output accuracy Nominal TJ= +25°C –1.0 +1.0 %
V
+ 0.3V VIN≤ V
DRB package over VIN, I
, Temp
OUT
Output accuracy
(1)
DRV package over VIN, I
, Temp
OUT
(1)
Load regulation 500μA I
OUT
Dropout voltage (VIN= V
OUT(NOM)
(2)
– 0.1V)
Output current limit VIN= V
Ground pin current 500μA I Shutdown current (I
) VEN≤ 0.4V 0.15 1.0 μA
GND
OUT
1mA I
OUT
V
+ 0.3V VIN≤ 6.5V
OUT
1mA I
OUT
V
+ 0.3V VIN≤ V
OUT
VIN≤ 6.5V –2.0 ±1.0 +2.0 % 1mA I
OUT
V
+ 0.3V VIN≤ V
OUT
VIN≤ 6.5V –3.0 ±1.0 +3.0 % 1mA I
OUT
V
OUT(NOM)
OUT
I
= 500mA 280 500 mV
OUT
V
= 0.9 × V
OUT
OUT(NOM)
VIN≥ 2.7V
OUT
Feedback pin current (TPS73501) –0.5 0.5 μA
f = 100Hz 60 dB
Power-supply rejection ratio
= 2.85V,
CNR= 0.01μF, I
OUT
OUT
= 100mA
f = 1kHz 56 dB f = 10kHz 41 dB f = 100kHz 28 dB
Output noise voltage BW = 10Hz to 100kHz, V
Startup time, V 90% V
= 2.85V,
OUT
RL= 14, C
OUT
= 0% to
OUT
= 2.2μF
OUT
= 2.8V
CNR= 0.01μF 11 x V CNR= none 95 x V CNR= none 45 μs CNR= 0.001μF 45 μs CNR= 0.01μF 50 μs
CNR= 0.047μF 50 μs Enable high (enabled) 1.2 V Enable low (shutdown) 0 0.4 V Enable pin current, enabled VEN= VIN= 6.5V 0.03 1.0 μA
Thermal shutdown temperature
J
Operating junction temperature –40 +125 °C
Shutdown, temperature increasing 165 °C
Reset, temperature decreasing 145 °C
Under-voltage lock-out VINrising 1.90 2.20 2.65 V Hysteresis VINfalling 70 mV
+ VDOor 2.7V, whichever is greater.
OUT
OUT(NOM)
< 2.8V because minimum VIN= 2.7V.
SBVS087H –JUNE 2008–REVISED NOVEMBER 2009
OUT(TYP)
+ 0.5V or 2.7V, whichever is greater; I
= 3.0V.
OUT
OUT
= 1mA,
2.7 6.5 V
6.0 V
500mA, V
500mA, V
500mA, V
500mA, V
OUT
OUT
OUT
> 6.5V
OUT
OUT
+ 3.0V,
OUT
+ 3.0V,
OUT
> 2.2V
2.2V
> 2.2V
> 2.2V
FB
–2.0 ±1.0 +2.0 %
–3.0 ±1.0 +3.0 %
+ 0.3V VIN≤ 6.5V 0.02 %/V
500mA 0.005 %/mA
OUT(NOM)
+ 0.9V, 800 1170 1720 mA
500mA 45 65 μA
OUT OUT
μV
RMS
μV
RMS
V
IN
Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 3
Thermal
Shutdown
UVLO
Current
Limit
3.3MW
Overshoot
Detect
500kW
1.208V
Bandgap
IN
EN
FB
OUT
GND
400W
Thermal
Shutdown
UVLO
Current
Limit
2 Am
Overshoot
Detect
500kW
Quickstart
1.208V
Bandgap
(1)
IN
EN
NR
OUT
GND
400W
NOTE(1): Fixedvoltageversionsbetween1.0Vto1.2Vhavea1.0Vbandgapcircuit
insteadofa1.208Vbandgapcircuit.
8
7
6
5
OUT
N/C
NR/FB
IN
N/C
N/C
EN
1
2
3
4
GND
IN
N/C
EN
6
5
4
OUT
NR/FB
GND
1
2
3
GND
TPS735xx
SBVS087H –JUNE 2008–REVISED NOVEMBER 2009
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FUNCTIONAL BLOCK DIAGRAMS
Figure 1. Fixed Voltage Versions Figure 2. Adjustable Voltage Versions
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DEVICE INFORMATION
PIN CONFIGURATIONS
DRB PACKAGE
3mm × 3mm SON-6
(TOP VIEW)
TPS735xx
NAME DRV DRB DESCRIPTION
IN 6 8 Input supply.
GND 3, Pad 4 Ground. The pad must be tied to GND.
EN 4 5
NR 2 3
FB 2 3
OUT 1 1
N/C 5 2, 6, 7 Not internally connected. This pin must either be left open, or tied to GND.
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DRV PACKAGE
2mm × 2mm SON-6
(TOP VIEW)
PIN DESCRIPTIONS
Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into shutdown mode. EN can be connected to IN if not used.
Fixed voltage versions only; connecting an external capacitor to this pin bypasses noise generated by the internal bandgap. This allows output noise to be reduced to very low levels.
Adjustable version only; this is the input to the control loop error amplifier, and is used to set the output voltage of the device.
Output of the regulator. A small capacitor (total typical capacitance 2.0μF ceramic) is needed from this pin to ground to assure stability.
0.5
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
-
-
-
-
-
ChangeinV (%)
OUT
3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
V (V)
IN
TJ= 40 C- °
TJ=0 C°
TJ=+125 C°
TJ=+85 C°
TJ=+25 C°
I =100mA
OUT
0.5
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
-
-
-
-
-
ChangeinV (%)
OUT
3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
V (V)
IN
TJ= 40 C- °
TJ=0 C°
TJ=+125 C°
TJ=+85 C°
TJ=+25 C°
I =100mA
OUT
2.86
2.85
2.84
2.83
2.82
2.81
2.80
2.79
2.78
2.77
2.76
2.75
2.74
V (V)
OUT
0 50 100 150 200 250 300 350 400 450 500
Load(mA)
TJ= 40 C- °
TJ=+125 C°
TJ=+85 C°
Y-axisrangeis 2%of2.8V±
2.55
2.54
2.53
2.52
2.51
2.50
2.49
2.48
2.47
2.46
2.45
V (V)
OUT
0 50 100 150 200 250 300 350 400 450 500
Load(mA)
TJ= 40 C- °
TJ=+125 C°
TJ=+85 C°
TJ=0 C°
TJ=+25 C°
Y-axisrangeis 2%of2.5V±
500
450
400
350
300
250
200
150
100
50
0
I (na)
GND
-40 -25 -10 5 20 35 50 65 80 95 110 125
T ( )JC
°
VIN=6.5V
VEN=0.4V
VIN=5.0V
VIN=3.3V
60
50
40
30
20
10
0
I ( A)m
GND
0 50 100 150 200 250 300 350 400 450 500
I (mA)
OUT
TJ= 40 C- °
TJ=+125 C°
TJ=+85 C°
TJ=0 C°
TJ=+25 C°
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TYPICAL CHARACTERISTICS
Over operating temperature range (TJ= –40°C to +125°C), VIN= V
VEN= VIN,C
= 2.2μF, CNR= 0.01μF, unless otherwise noted. For TPS73501, V
OUT
+25°C.
TPS73501 LINE REGULATION TPS73525 LINE REGULATION
Figure 3. Figure 4.
TPS73501 LOAD REGULATION TPS73525 LOAD REGULATION
OUT(TYP)
SBVS087H –JUNE 2008–REVISED NOVEMBER 2009
+ 0.5V or 2.7V, whichever is greater; I
= 2.8V. Typical values are at TJ=
OUT
OUT
= 1mA,
Figure 5. Figure 6.
TPS73525 GROUND PIN CURRENT vs TPS73525 GROUND PIN CURRENT (DISABLE) vs
OUTPUT CURRENT TEMPERATURE
Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 5
Figure 7. Figure 8.
400
350
300
250
200
150
100
50
0
V (mV)
DO
0 50 100 150 200 250 300 350 400 450 500
I (mA)
OUT
TJ= 40 C- °
TJ=+125 C°
TJ=+85 C°
TJ=0 C°
TJ=+25 C°
10 100
1k
10k 100k
1M
10M
Frequency(Hz)
90
80
70
60
50
40
30
20
10
0
PSRR(dB)
C =2.2 F
OUT
m
C =0.01 FNRm
I =250mA
OUT
I =
100mA
OUT
I =
500mA
OUT
I =200mA
OUT
I =1mA
OUT
10 100
1k
10k 100k
1M
10M
Frequency(Hz)
90
80
70
60
50
40
30
20
10
0
PSRR(dB)
C =2.2 F
OUT
m
C =0.01 FNRm
I =200mA
OUT
I =
100mA
OUT
I =
500mA
OUT
I =250mA
OUT
I =1mA
OUT
10 100
1k
10k 100k
1M
10M
Frequency(Hz)
90
80
70
60
50
40
30
20
10
0
PSRR(dB)
C =10 F
OUT
m
C =0.01 FNRm
I =200mA
OUT
I =
100mA
OUT
I =
500mA
OUT
I =
200mA
OUT
I =1mA
OUT
TPS735xx
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TYPICAL CHARACTERISTICS (continued)
Over operating temperature range (TJ= –40°C to +125°C), VIN= V VEN= VIN,C
= 2.2μF, CNR= 0.01μF, unless otherwise noted. For TPS73501, V
OUT
OUT(TYP)
+25°C.
TPS73501 DROPOUT VOLTAGE vs POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY
OUTPUT CURRENT (VIN– V
Figure 9. Figure 10.
POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY
(VIN– V
= 0.5V) (VIN– V
OUT
+ 0.5V or 2.7V, whichever is greater; I
= 2.8V. Typical values are at TJ=
OUT
= 1.0V)
OUT
= 0.3V)
OUT
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= 1mA,
OUT
Figure 11. Figure 12.
6 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated
30
25
20
15
10
5
0
TotalNoise( V )m
RMS
0
5
10 15 20 25
C ( F)m
OUT
I =1mA C =0.01 F
OUT
NR
m
140
120
100
80
60
40
20
0
TotalNoise( V )m
RMS
0.01 0.1
1
10
C (nF)
NR
I =1mA C =2.2 F
OUT
OUT
m
10 s/divm
V
OUT
V
EN
C =10 F
OUT
m
C =2.2 F
OUT
m
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0.5-
Voltage(V)
10 s/divm
V
EN
V
OUT
C =2.2 F
OUT
m
C =10 F
OUT
m
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0.5-
Voltage(V)
TPS735xx
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TYPICAL CHARACTERISTICS (continued)
Over operating temperature range (TJ= –40°C to +125°C), VIN= V VEN= VIN,C +25°C.
= 2.2μF, CNR= 0.01μF, unless otherwise noted. For TPS73501, V
OUT
TPS73525 TPS73525
TOTAL NOISE vs C
NR
Figure 13. Figure 14.
TPS73525
TURN-ON RESPONSE TPS73525
(VIN= VEN) EN RESPONSE OVER STABLE V
OUT(TYP)
SBVS087H –JUNE 2008–REVISED NOVEMBER 2009
+ 0.5V or 2.7V, whichever is greater; I
= 2.8V. Typical values are at TJ=
OUT
TOTAL NOISE vs C
OUT
IN
OUT
= 1mA,
Figure 15. Figure 16.
Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 7
10 s/divm
200mV/div
200mV/div
200mV/div
500mA/div
V
OUT
V
OUT
I
OUT
C =470 FOSCON
OUT
m
C =10 F
OUT
m
C =2.2 F
OUT
m
V =3.0V
IN
500mA
1mA
10 s/divm
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0
1.0-
Volts(V)
VIN=EN
V
OUT
R =5W
L
10 s/divm
50mV/div
50mV/div
50mV/div
0.5V/div
V
OUT
V
OUT
V
OUT
V
OUT
V
IN
C =470 FOSCON
OUT
m
C =10 F
OUT
m
C =2.2 F
OUT
m
4V
3V
TPS735xx
SBVS087H –JUNE 2008–REVISED NOVEMBER 2009
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TYPICAL CHARACTERISTICS (continued)
Over operating temperature range (TJ= –40°C to +125°C), VIN= V VEN= VIN,C +25°C.
= 2.2μF, CNR= 0.01μF, unless otherwise noted. For TPS73501, V
OUT
TPS73525
POWER-UP/POWER-DOWN
(VIN= VEN) TPS73525 LOAD TRANSIENT RESPONSE
Figure 17. Figure 18.
TPS73525 LINE TRANSIENT RESPONSE
OUT(TYP)
+ 0.5V or 2.7V, whichever is greater; I
= 2.8V. Typical values are at TJ=
OUT
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= 1mA,
OUT
Figure 19.
8 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated
GNDEN NR
IN OUT
TPS735xx
Optionalbypasscapacitor
toreduceoutputnoise
andincreasePSRR.
Optionalinputcapacitor.
Mayimprovesource
impedance,noise,orPSRR.
V
IN
V
EN
2.2 F Ceramic
m
V
OUT
GNDEN
FB
IN OUT
Optionalinputcapacitor.
Mayimprovesource
impedance,noise,orPSRR.
TPS73501
2.2 F Ceramic
m
V
IN
V
EN
R
1
R
2
C
FB
V
OUT
(R +R )
1 2
R
2
V
OUT
= ´ 1.208
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SBVS087H –JUNE 2008–REVISED NOVEMBER 2009
APPLICATION INFORMATION
The TPS735xx family of LDO regulators combines the high performance required of many RF and Although an input capacitor is not required for precision analog applications with ultra-low current stability, it is good analog design practice to connect consumption. High PSRR is provided by a high gain, a 0.1μF to 1μF low equivalent series resistance high bandwidth error loop with good supply rejection (ESR) capacitor across the input supply near the at very low headroom (VIN– V
). Fixed voltage regulator. The ground of this capacitor should be
OUT
versions provide a noise reduction pin to bypass connected as close as the ground of output capacitor; noise generated by the bandgap reference and to a capacitor value of 0.1μF is enough in this condition. improve PSRR while a quick-start circuit fast-charges When it is difficult to place these two ground points this capacitor at startup. The combination of high close together, a 1μF capacitor is recommended. performance and low ground current also make the This capacitor counteracts reactive input sources and TPS735xx an excellent choice for portable improves transient response, noise rejection, and applications. All versions have thermal and ripple rejection. A higher-value capacitor may be over-current protection and are fully specified from necessary if large, fast rise-time load transients are –40°C to +125°C. anticipated, or if the device is located several inches
Figure 20 shows the basic circuit connections for
fixed voltage models. Figure 21 gives the connections for the adjustable output version (TPS73501). R1and R2can be calculated for any output voltage using the The TPS735xx is designed to be stable with standard formula in Figure 21. ceramic output capacitors of values 2.2μF or larger.
Input and Output Capacitor Requirements
from the power source. If source impedance is not sufficiently low, a 0.1μF input capacitor may be necessary to ensure stability.
X5R and X7R type capacitors are best because they have minimal variation in value and ESR over temperature. Maximum ESR of the output capacitor should be < 1.0, so output capacitor type should be either ceramic or conductive polymer electrolytic.
Figure 20. Typical Application Circuit for
Figure 21. Typical Application Circuit for
space space
Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 9
Fixed Voltage Versions
Adjustable Voltage Versions
Feedback Capacitor Requirements (TPS73501 only)
The feedback capacitor, CFB, shown in Figure 21 is required for stability. For a parallel combination of R
1
and R2equal to 250k, any value from 3pF to 1nF can be used. Fixed voltage versions have an internal 30pF feedback capacitor that is quick-charged at start-up. The adjustable version does not have this quick-charge circuit, so values below 5pF should be used to ensure fast startup; values above 47pF can be used to implement an output voltage soft-start. Larger value capacitors also improve noise slightly. The TPS73501 is stable in unity-gain configuration (OUT tied to FB) without CFB.
Output Noise
In most LDOs, the bandgap is the dominant noise source. If a noise reduction capacitor (CNR) is used with the TPS735xx, the bandgap does not contribute significantly to noise. Instead, noise is dominated by the output resistor divider and the error amplifier input. To minimize noise in a given application, use a
0.01μF noise reduction capacitor; for the adjustable version, smaller value resistors in the output resistor divider reduce noise. A parallel combination that gives 2μA of divider current has the same noise performance as a fixed voltage version. To further
V =xV
N OUT
11VmV
RMS
TPS735xx
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optimize noise, equivalent series resistance of the As with any linear regulator, PSRR and transient output capacitor can be set to approximately 0.2. response are degraded as (VIN– V
) approaches
OUT
This configuration maximizes phase margin in the dropout. This effect is shown in the Typical control loop, reducing total output noise by up to Characteristics section. 10%.
Noise can be referred to the feedback point (FB pin) such that with CNR= 0.01μF, total noise is given approximately by Equation 1:
Startup and Noise Reduction Capacitor
Fixed voltage versions of the TPS735xx use a quick-start circuit to fast-charge the noise reduction capacitor, CNR, if present (see the Functional Block
(1)
The TPS73501 adjustable version does not have the noise-reduction pin available, so ultra-low noise operation is not possible. Noise can be minimized according to the above recommendations.
Board Layout Recommendations to Improve PSRR and Noise Performance
Diagrams). This architecture allows the combination
of very low output noise and fast start-up times. The NR pin is high impedance so a low leakage C
NR
capacitor must be used; most ceramic capacitors are appropriate in this configuration.
Note that for fastest startup, VINshould be applied first, then the enable pin (EN) driven high. If EN is tied to IN, startup is somewhat slower. Refer to the
Typical Characteristics section. The quick-start switch
To improve ac performance such as PSRR, output is closed for approximately 135μs. To ensure that noise, and transient response, it is recommended that CNRis fully charged during the quick-start time, a the board be designed with separate ground planes 0.01μF or smaller capacitor should be used. for VINand V only at the GND pin of the device. In addition, the ground connection for the bypass capacitor should connect directly to the GND pin of the device.
Internal Current Limit
, with each ground plane connected
OUT
Transient Response
As with any regulator, increasing the size of the
output capacitor reduces over/undershoot magnitude
but increases duration of the transient response. In
the adjustable version, adding CFBbetween OUT and The TPS735xx internal current limit helps protect the FB improves stability and transient response. The regulator during fault conditions. During current limit, transient response of the TPS735xx is enhanced by the output sources a fixed amount of current that is an active pull-down that engages when the output largely independent of output voltage. For reliable overshoots by approximately 5% or more when the operation, the device should not be operated in device is enabled. When enabled, the pull-down current limit for extended periods of time. device behaves like a 400resistor to ground.
The PMOS pass element in the TPS735xx has a built-in body diode that conducts current when the voltage at OUT exceeds the voltage at IN. This current is not limited, so if extended reverse voltage operation is anticipated, external limiting may be appropriate.
Undervoltage Lock-Out (UVLO)
The TPS735xx utilizes an undervoltage lock-out
circuit to keep the output shut off until internal
circuitry is operating properly. The UVLO circuit has a
de-glitch feature so that it typically ignores
undershoot transients on the input if they are less
Shutdown than 50μs duration.
The enable pin (EN) is active high and is compatible with standard and low voltage TTL-CMOS levels. When shutdown capability is not required, EN can be connected to IN.
Minimum Load
The TPS735xx is stable and well-behaved with no
output load. To meet the specified accuracy, a
minimum load of 500μA is required. Below 500μA at
Dropout Voltage junction temperatures near +125°C, the output can
The TPS735xx uses a PMOS pass transistor to achieve low dropout. When (VIN– V
) is less than
OUT
the dropout voltage (VDO), the PMOS pass device is in its linear region of operation and the input-to-output resistance is the R
of the PMOS pass element.
DS, ON
Because the PMOS device behaves like a resistor in dropout, V
approximately scales with output
DO
current.
drift up enough to cause the output pull-down to turn
on. The output pull-down limits voltage drift to 5%
typically but ground current could increase by
approximately 50μA. In typical applications, the
junction cannot reach high temperatures at light loads
because there is no appreciable dissipated power.
The specified ground current would then be valid at
no load in most applications.
10 Submit Documentation Feedback Copyright© 2008–2009, Texas Instruments Incorporated
P
D
+
ǒ
VIN*V
OUT
Ǔ
@ I
OUT
TPS735xx
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Thermal Information
Thermal Protection Power Dissipation
Thermal protection disables the output when the The ability to remove heat from the die is different for junction temperature rises to approximately +165°C, each package type, presenting different allowing the device to cool. When the junction considerations in the PCB layout. The PCB area temperature cools to approximately +145°C the around the device that is free of other components output circuitry is again enabled. Depending on power moves the heat from the device to the ambient air. dissipation, thermal resistance, and ambient Performance data for JEDEC low- and high-K boards temperature, the thermal protection circuit may cycle are given in the Dissipation Ratings table. Using on and off. This cycling limits the dissipation of the heavier copper increases the effectiveness in regulator, protecting it from damage as a result of removing heat from the device. The addition of plated overheating. through-holes to heat-dissipating layers also
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an Power dissipation depends on input voltage and load inadequate heatsink. For reliable operation, junction conditions. Power dissipation is equal to the product temperature should be limited to +125°C maximum. of the output current time the voltage drop across the To estimate the margin of safety in a complete design output pass element, as shown in Equation 2: (including heatsink), increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should trigger at least +35°C above the maximum expected ambient condition of your particular application. This configuration produces a worst-case junction temperature of +125°C at the highest expected ambient temperature and worst-case load.
The internal protection circuitry of the TPS735xx has been designed to protect against overload conditions. It was not intended to replace proper heatsinking. Continuously running the TPS735xx into thermal shutdown degrades device reliability.
improves the heatsink effectiveness.
(2)
Note: When the device is used in a condition of
higher input and lower output voltages with the DRV
and DRB packages, PDexceeds the package rating
at room temperature. This equation shows an
example of the DRB package:
PD= (6.5V – 1.0V) × 500mA = 2.75W, which is greater than 2.5W at +25°C.
Package Mounting
Solder pad footprint recommendations for the
TPS735xx are available from the Texas Instruments
web site at www.ti.com.
Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 11
TPS735xx
SBVS087H –JUNE 2008–REVISED NOVEMBER 2009
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REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (March, 2009) to Revision H Page
Revised bullet point in Features list to show very low dropout of 280mV ............................................................................ 1
Changed dropout voltage typical specification from 250mV to 280mV ................................................................................ 3
12 Submit Documentation Feedback Copyright© 2008–2009, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
TPS73501DRBR ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR Purchase Samples
TPS73501DRBT ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR Request Free Samples
TPS73512DRBR ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR Purchase Samples
TPS73512DRBT ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR Request Free Samples
TPS73515DRBR PREVIEW SON DRB 8 3000 TBD Call TI Call TI Samples Not Available TPS73515DRBT PREVIEW SON DRB 8 250 TBD Call TI Call TI Samples Not Available TPS73525DRBR ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR Request Free Samples
TPS73525DRBRG4 ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR Request Free Samples
TPS73525DRBT ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR Purchase Samples
TPS73525DRBTG4 ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR Purchase Samples
TPS73525DRVR ACTIVE SON DRV 6 3000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM Request Free Samples
TPS73525DRVT ACTIVE SON DRV 6 250 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM Purchase Samples
TPS73533DRBR ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR Purchase Samples
TPS73533DRBT ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR Request Free Samples
TPS73533DRVR ACTIVE SON DRV 6 3000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM Purchase Samples
TPS73533DRVT ACTIVE SON DRV 6 250 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM Request Free Samples
TPS73534DRBR ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR Request Free Samples
TPS73534DRBT ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR Purchase Samples
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PACKAGE OPTION ADDENDUM
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Addendum-Page 2
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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PACKAGE MATERIALS INFORMATION
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TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type
TPS73501DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS73501DRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS73512DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS73512DRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS73525DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS73525DRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS73533DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS73533DRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS73533DRVR SON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
TPS73533DRVT SON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
TPS73534DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS73534DRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
Package Drawing
Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm)B0(mm)K0(mm)P1(mm)W(mm)
Pin1
Quadrant
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
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*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length(mm) Width (mm) Height (mm)
TPS73501DRBR SON DRB 8 3000 346.0 346.0 29.0
TPS73501DRBT SON DRB 8 250 190.5 212.7 31.8
TPS73512DRBR SON DRB 8 3000 346.0 346.0 29.0
TPS73512DRBT SON DRB 8 250 190.5 212.7 31.8
TPS73525DRBR SON DRB 8 3000 346.0 346.0 29.0
TPS73525DRBT SON DRB 8 250 190.5 212.7 31.8
TPS73533DRBR SON DRB 8 3000 346.0 346.0 29.0
TPS73533DRBT SON DRB 8 250 190.5 212.7 31.8
TPS73533DRVR SON DRV 6 3000 203.0 203.0 35.0
TPS73533DRVT SON DRV 6 250 203.0 203.0 35.0
TPS73534DRBR SON DRB 8 3000 346.0 346.0 29.0
TPS73534DRBT SON DRB 8 250 190.5 212.7 31.8
Pack Materials-Page 2
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