500mA, Low Quiescent Current, Ultra-Low Noise, High PSRR
Low Dropout Linear Regulator
1
FEATURES
2
•500mA Low Dropout Regulator with EN
•Low IQ: 46μA
•Multiple Output Voltage Versions Available:
– Fixed Outputs of 1.0V to 4.3V Using
Innovative Factory EEPROM Programming
– Adjustable Outputs from 1.25V to 6.0V
•High PSRR: 60dB at 1kHz
•Ultra-low Noise: 28μV
•Fast Start-Up Time: 45μs
•Stable with a Low-ESR, 2.0μF Typical Output
Capacitance
•Excellent Load/Line Transient Response
•2% Overall Accuracy (Load/Line/Temp,
V
> 2.2V)
OUT
•Very Low Dropout: 280mV at 500mA
•2mm × 2mm SON-6 and 3mm × 3mm SON-8
Packages
RMS
SBVS087H –JUNE 2008–REVISED NOVEMBER 2009
DESCRIPTION
TheTPS735xxfamilyoflow-dropout(LDO),
low-powerlinearregulatorsoffersexcellentac
performance with very low ground current. High
power-supply rejection ratio (PSRR), low noise, fast
start-up, and excellentline and loadtransient
response are provided while consuming a very low
46μA (typical) ground current. The TPS735xx is
stable with ceramic capacitors and uses an advanced
BiCMOS fabrication process to yield a typical dropout
voltage of 250mV at 500mA output. The TPS735xx
uses a precision voltage reference and feedback loop
to achieve overall accuracy of 2% (V
all load, line, process, and temperature variations. It
is fully specified from TJ= –40°C to +125°C and is
offered in low-profile, 2mm x 2mm SON and 3mm ×
3mm SON packages that are ideal for wireless
handsets, printers, and WLAN cards.
> 2.2V) over
OUT
APPLICATIONS
•WiFi, WiMax
•Printers
•Cellular Phones, SmartPhones
•Handheld Organizers, PDAs
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
PRODUCTV
(1)
OUT
(2)
TPS735xx yyy zXX is nominal output voltage (for example, 28 = 2.8V, 285 = 2.85V, 01 = Adjustable).
YYY is package designator.
Z is package quantity.
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) Output voltages from 1.0V to 3.6V in 50mV increments are available through the use of innovative factory EEPROM programming;
minimum order quantities may apply. Contact factory for details and availability.
ABSOLUTE MAXIMUM RATINGS
Over operating temperature range (unless otherwise noted).
PARAMETERTPS735xxUNIT
VINrange–0.3 to +7.0V
VENrange–0.3 to VIN+0.3V
V
range–0.3 to VIN+0.3V
OUT
VFBrange–0.3 to VFB(TYP) +0.3V
Peak output currentInternally limited
Continuous total power dissipationSee Dissipation Ratings Table
Junction temperature range, T
Storage temperature range , T
ESD rating, HBM2kV
ESD rating, CDM500V
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into
shutdown mode. EN can be connected to IN if not used.
Fixed voltage versions only; connecting an external capacitor to this pin bypasses noise
generated by the internal bandgap. This allows output noise to be reduced to very low levels.
Adjustable version only; this is the input to the control loop error amplifier, and is used to set the
output voltage of the device.
Output of the regulator. A small capacitor (total typical capacitance ≥ 2.0μF ceramic) is needed
from this pin to ground to assure stability.
0.5
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
-
-
-
-
-
ChangeinV(%)
OUT
3.03.54.04.55.05.56.06.5
V (V)
IN
TJ= 40 C- °
TJ=0 C°
TJ=+125 C°
TJ=+85 C°
TJ=+25 C°
I=100mA
OUT
0.5
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
-
-
-
-
-
ChangeinV(%)
OUT
3.03.54.04.55.05.56.06.5
V (V)
IN
TJ= 40 C- °
TJ=0 C°
TJ=+125 C°
TJ=+85 C°
TJ=+25 C°
I=100mA
OUT
2.86
2.85
2.84
2.83
2.82
2.81
2.80
2.79
2.78
2.77
2.76
2.75
2.74
V(V)
OUT
050 100 150 200 250 300 350 400 450 500
Load(mA)
TJ= 40 C- °
TJ=+125 C°
TJ=+85 C°
Y-axisrangeis 2%of2.8V±
2.55
2.54
2.53
2.52
2.51
2.50
2.49
2.48
2.47
2.46
2.45
V(V)
OUT
050 100 150 200 250 300 350 400 450 500
Load(mA)
TJ= 40 C- °
TJ=+125 C°
TJ=+85 C°
TJ=0 C°
TJ=+25 C°
Y-axisrangeis 2%of2.5V±
500
450
400
350
300
250
200
150
100
50
0
I(na)
GND
-40 -25 -10 520 35 50 65 80 95 110 125
T ( )JC
°
VIN=6.5V
VEN=0.4V
VIN=5.0V
VIN=3.3V
60
50
40
30
20
10
0
I( A)m
GND
050 100 150 200 250 300 350 400 450 500
I(mA)
OUT
TJ= 40 C- °
TJ=+125 C°
TJ=+85 C°
TJ=0 C°
TJ=+25 C°
TPS735xx
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TYPICAL CHARACTERISTICS
Over operating temperature range (TJ= –40°C to +125°C), VIN= V
VEN= VIN,C
= 2.2μF, CNR= 0.01μF, unless otherwise noted. For TPS73501, V
OUT
+25°C.
TPS73501 LINE REGULATIONTPS73525 LINE REGULATION
Figure 3.Figure 4.
TPS73501 LOAD REGULATIONTPS73525 LOAD REGULATION
OUT(TYP)
SBVS087H –JUNE 2008–REVISED NOVEMBER 2009
+ 0.5V or 2.7V, whichever is greater; I
= 2.8V. Typical values are at TJ=
OUT
OUT
= 1mA,
Figure 5.Figure 6.
TPS73525 GROUND PIN CURRENT vsTPS73525 GROUND PIN CURRENT (DISABLE) vs
The TPS735xx family of LDO regulators combines
the high performance required of many RF andAlthough an input capacitor is not required for
precision analog applications with ultra-low currentstability, it is good analog design practice to connect
consumption. High PSRR is provided by a high gain,a 0.1μF to 1μF low equivalent series resistance
high bandwidth error loop with good supply rejection(ESR) capacitor across the input supply near the
at very low headroom (VIN– V
). Fixed voltageregulator. The ground of this capacitor should be
OUT
versions provide a noise reduction pin to bypassconnected as close as the ground of output capacitor;
noise generated by the bandgap reference and toa capacitor value of 0.1μF is enough in this condition.
improve PSRR while a quick-start circuit fast-chargesWhen it is difficult to place these two ground points
this capacitor at startup. The combination of highclose together, a 1μF capacitor is recommended.
performance and low ground current also make theThis capacitor counteracts reactive input sources and
TPS735xxanexcellentchoiceforportableimproves transient response, noise rejection, and
applications.Allversionshavethermalandripple rejection. A higher-value capacitor may be
over-current protection and are fully specified fromnecessary if large, fast rise-time load transients are
–40°C to +125°C.anticipated, or if the device is located several inches
Figure 20 shows the basic circuit connections for
fixed voltage models. Figure 21 gives the connections
for the adjustable output version (TPS73501). R1and
R2can be calculated for any output voltage using theThe TPS735xx is designed to be stable with standard
formula in Figure 21.ceramic output capacitors of values 2.2μF or larger.
Input and Output Capacitor Requirements
from the power source. If source impedance is not
sufficiently low, a 0.1μF input capacitor may be
necessary to ensure stability.
X5R and X7R type capacitors are best because they
have minimal variation in value and ESR over
temperature. Maximum ESR of the output capacitor
should be < 1.0Ω, so output capacitor type should be
either ceramic or conductive polymer electrolytic.
The feedback capacitor, CFB, shown in Figure 21 is
required for stability. For a parallel combination of R
1
and R2equal to 250kΩ, any value from 3pF to 1nF
can be used. Fixed voltage versions have an internal
30pF feedback capacitor that is quick-charged at
start-up. The adjustable version does not have this
quick-charge circuit, so values below 5pF should be
used to ensure fast startup; values above 47pF can
be used to implement an output voltage soft-start.
Larger value capacitors also improve noise slightly.
The TPS73501 is stable in unity-gain configuration
(OUT tied to FB) without CFB.
Output Noise
In most LDOs, the bandgap is the dominant noise
source. If a noise reduction capacitor (CNR) is used
with the TPS735xx, the bandgap does not contribute
significantly to noise. Instead, noise is dominated by
the output resistor divider and the error amplifier
input. To minimize noise in a given application, use a
0.01μF noise reduction capacitor; for the adjustable
version, smaller value resistors in the output resistor
divider reduce noise. A parallel combination that
gives 2μA of divider current has the same noise
performance as a fixed voltage version. To further
V =xV
NOUT
11VmV
RMS
TPS735xx
SBVS087H –JUNE 2008–REVISED NOVEMBER 2009
查询"TPS73512"供应商
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optimize noise, equivalent series resistance of theAs with any linear regulator, PSRR and transient
output capacitor can be set to approximately 0.2Ω.response are degraded as (VIN– V
) approaches
OUT
This configuration maximizes phase margin in thedropout.Thiseffectisshown intheTypical
control loop, reducing total output noise by up toCharacteristics section.
10%.
Noise can be referred to the feedback point (FB pin)
such that with CNR= 0.01μF, total noise is given
approximately by Equation 1:
Startup and Noise Reduction Capacitor
Fixed voltage versions of the TPS735xx use a
quick-start circuit to fast-charge the noise reduction
capacitor, CNR, if present (see the Functional Block
(1)
The TPS73501 adjustable version does not have the
noise-reduction pin available, so ultra-low noise
operation is not possible. Noise can be minimized
according to the above recommendations.
Board Layout Recommendations to Improve
PSRR and Noise Performance
Diagrams). This architecture allows the combination
of very low output noise and fast start-up times. The
NR pin is high impedance so a low leakage C
NR
capacitor must be used; most ceramic capacitors are
appropriate in this configuration.
Note that for fastest startup, VINshould be applied
first, then the enable pin (EN) driven high. If EN is
tied to IN, startup is somewhat slower. Refer to the
Typical Characteristics section. The quick-start switch
To improve ac performance such as PSRR, outputis closed for approximately 135μs. To ensure that
noise, and transient response, it is recommended thatCNRis fully charged during the quick-start time, a
the board be designed with separate ground planes0.01μF or smaller capacitor should be used.
for VINand V
only at the GND pin of the device. In addition, the
ground connection for the bypass capacitor should
connect directly to the GND pin of the device.
but increases duration of the transient response. In
the adjustable version, adding CFBbetween OUT and
The TPS735xx internal current limit helps protect theFB improves stability and transient response. The
regulator during fault conditions. During current limit,transient response of the TPS735xx is enhanced by
the output sources a fixed amount of current that isan active pull-down that engages when the output
largely independent of output voltage. For reliableovershoots by approximately 5% or more when the
operation, the device should not be operated indevice is enabled. When enabled, the pull-down
current limit for extended periods of time.device behaves like a 400Ω resistor to ground.
The PMOS pass element in the TPS735xx has a
built-in body diode that conducts current when the
voltage at OUT exceeds the voltage at IN. This
current is not limited, so if extended reverse voltage
operation is anticipated, external limiting may be
appropriate.
Undervoltage Lock-Out (UVLO)
The TPS735xx utilizes an undervoltage lock-out
circuit to keep the output shut off until internal
circuitry is operating properly. The UVLO circuit has a
de-glitchfeaturesothatittypicallyignores
undershoot transients on the input if they are less
Shutdownthan 50μs duration.
The enable pin (EN) is active high and is compatible
with standard and low voltage TTL-CMOS levels.
When shutdown capability is not required, EN can be
connected to IN.
Minimum Load
The TPS735xx is stable and well-behaved with no
output load. To meet the specified accuracy, a
minimum load of 500μA is required. Below 500μA at
Dropout Voltagejunction temperatures near +125°C, the output can
The TPS735xx uses a PMOS pass transistor to
achieve low dropout. When (VIN– V
) is less than
OUT
the dropout voltage (VDO), the PMOS pass device is
in its linear region of operation and the input-to-output
resistance is the R
of the PMOS pass element.
DS, ON
Because the PMOS device behaves like a resistor in
dropout, V
approximately scaleswithoutput
DO
current.
drift up enough to cause the output pull-down to turn
on. The output pull-down limits voltage drift to 5%
typically but ground current could increase by
approximately 50μA. In typical applications, the
junction cannot reach high temperatures at light loads
because there is no appreciable dissipated power.
The specified ground current would then be valid at
Thermal protection disables the output when theThe ability to remove heat from the die is different for
junction temperature rises to approximately +165°C,eachpackagetype,presentingdifferent
allowing the device to cool. When the junctionconsiderations in the PCB layout. The PCB area
temperature cools to approximately +145°C thearound the device that is free of other components
output circuitry is again enabled. Depending on powermoves the heat from the device to the ambient air.
dissipation,thermalresistance,andambientPerformance data for JEDEC low- and high-K boards
temperature, the thermal protection circuit may cycleare given in the Dissipation Ratings table. Using
on and off. This cycling limits the dissipation of theheaviercopperincreasestheeffectivenessin
regulator, protecting it from damage as a result ofremoving heat from the device. The addition of plated
overheating.through-holestoheat-dissipatinglayersalso
Any tendency to activate the thermal protection circuit
indicatesexcessivepowerdissipationoranPower dissipation depends on input voltage and load
inadequate heatsink. For reliable operation, junctionconditions. Power dissipation is equal to the product
temperature should be limited to +125°C maximum.of the output current time the voltage drop across the
To estimate the margin of safety in a complete designoutput pass element, as shown in Equation 2:
(includingheatsink),increasetheambient
temperature until the thermal protection is triggered;
use worst-case loads and signal conditions. For good
reliability, thermal protection should trigger at least
+35°Cabovethemaximumexpectedambient
conditionofyourparticularapplication.This
configurationproducesaworst-casejunction
temperature of +125°C at the highest expected
ambient temperature and worst-case load.
The internal protection circuitry of the TPS735xx has
been designed to protect against overload conditions.
It was not intended to replace proper heatsinking.
Continuously running the TPS735xx into thermal
shutdown degrades device reliability.
improves the heatsink effectiveness.
(2)
Note: When the device is used in a condition of
higher input and lower output voltages with the DRV
and DRB packages, PDexceeds the package rating
at room temperature. This equation shows an
example of the DRB package:
PD= (6.5V – 1.0V) × 500mA = 2.75W, which is
greater than 2.5W at +25°C.
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (March, 2009) to Revision HPage
•Revised bullet point in Features list to show very low dropout of 280mV ............................................................................ 1
•Changed dropout voltage typical specification from 250mV to 280mV ................................................................................ 3
TPS73515DRBRPREVIEWSONDRB83000TBDCall TICall TISamples Not Available
TPS73515DRBTPREVIEWSONDRB8250TBDCall TICall TISamples Not Available
TPS73525DRBRACTIVESONDRB83000Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEARRequest Free Samples
TPS73525DRBRG4ACTIVESONDRB83000Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEARRequest Free Samples
TPS73525DRBTACTIVESONDRB8250Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEARPurchase Samples
TPS73525DRBTG4ACTIVESONDRB8250Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEARPurchase Samples
TPS73525DRVRACTIVESONDRV63000Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIMRequest Free Samples
TPS73525DRVTACTIVESONDRV6250Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIMPurchase Samples
TPS73533DRBRACTIVESONDRB83000Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEARPurchase Samples
TPS73533DRBTACTIVESONDRB8250Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEARRequest Free Samples
TPS73533DRVRACTIVESONDRV63000Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIMPurchase Samples
TPS73533DRVTACTIVESONDRV6250Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIMRequest Free Samples
TPS73534DRBRACTIVESONDRB83000Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEARRequest Free Samples
TPS73534DRBTACTIVESONDRB8250Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEARPurchase Samples
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PACKAGE OPTION ADDENDUM
www.ti.com
Addendum-Page 2
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances,including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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