Texas Instruments TPS7325QD, TPS7301QPWR, TPS7301QPWLE, TPS7301QP, TPS7301QDR Datasheet
...
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUAR Y 1999
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Available in 2.5-V, 3-V, 3.3-V, 4.85-V, and 5-V
Fixed-Output and Adjustable Versions
D
Integrated Precision Supply-Voltage
Supervisor Monitoring Regulator Output
Voltage
D
Active-Low Reset Signal with 200-ms Pulse
Width
D
Very Low Dropout Voltage ...Maximum of
35 mV at IO = 100 mA (TPS7350)
D
Low Quiescent Current – Independent of
Load . . . 340 µA Typ
D
Extremely Low Sleep-State Current,
0.5 µA Max
D
2% Tolerance Over Full Range of Load,
Line, and Temperature for Fixed-Output
Versions
§
D
Output Current Range of 0 mA to 500 mA
D
TSSOP Package Option Offers Reduced
Component Height For Critical Applications
description
The TPS73xx devices are members of a family of
micropower low-dropout (LDO) voltage regulators.
They are di ffere ntiate d from the TP S71xx an d TPS72xx LDOs by their integrated delayed microprocessor-reset
function. If the precision delayed reset is not required, the TPS71xx and TPS72xx should be considered.
¶
AVAILABLE OPTIONS
OUTPUT VOLTAGE
(V)
NEGATIVE-GOING RESET
THRESHOLD VOLTAGE (V)
PACKAGED DEVICES
T
J
MIN TYP MAX MIN TYP MAX
SMALL
OUTLINE
(D)
PLASTIC DIP
(P)
TSSOP
(PW)
CHIP FORM
(Y)
4.9 5 5.1 4.55 4.65 4.75 TPS7350QD TPS7350QP TPS7350QPW TPS7350Y
4.75 4.85 4.95 4.5 4.6 4.7 TPS7348QD TPS7348QP TPS7348QPW TPS7348Y
°
3.23 3.3 3.37 2.868 2.934 3 TPS7333QD TPS7333QP TPS7333QPW TPS7333Y
–
40°C to
125°C
2.94 3 3.06 2.58 2.64 2.7 TPS7330QD TPS7330QP TPS7330QPW TPS7330Y
125 C
2.425 2.5 2.575 2.23 2.32 2.39 TPS7325QD TPS7325QP TPS7325QPW TPS7325Y
Adjustable
1.2 V to 9.75 V
1.101 1.123 1.145 TPS7301QD TPS7301QP TPS7301QPW TPS7301Y
The D and PW packages are available taped and reeled. Add an R suffix to device type (e.g., TPS7350QDR). The TPS7301Q is programmable
using an external resistor divider (see application information). The chip form is tested at 25°C.
§
The TPS7325 has a tolerance of ±3% over the full temperature range.
¶
The TPS71xx and the TPS72xx are 500-mA and 250-mA output regulators respectively, of fering performance similar to that of the TPS73xx but
without the delayed-reset function. The TPS72xx devices are further differentiated by availability in 8-pin thin-shrink small-outline packages
(TSSOP) for applications requiring minimum package size.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
GND
GND
GND
NC
NC
EN
NC
IN
IN
IN
RESET
NC
NC
FB
‡
NC
SENSE
†
OUT
OUT
NC
NC
PW PACKAGE
(TOP VIEW)
NC – No internal connection
†
SENSE – Fixed voltage options only
(TPS7325, TPS7330, TPS7333, TPS7348, and TPS7350)
‡
FB – Adjustable version only (TPS7301)
1
2
3
4
8
7
6
5
GND
EN
IN
IN
RESET
SENSE†/FB
‡
OUT
OUT
D OR P PACKAGE
(TOP VIEW)
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUAR Y 1999
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
The RESET output of the TPS73xx initiates a reset in microcomputer and microprocessor systems in the event
of an undervoltage condition. An internal comparator in the TPS73xx monitors the output voltage of the regulator
to detect an undervoltage condition on the regulated output voltage.
If that occurs, the RESET output (open-drain NMOS) turns on, taking the RESET signal low . RESET stays low
for the duration of the undervoltage condition. Once the undervoltage condition ceases, a 200-ms (typ) time-out
begins. At the completion of the 200-ms delay, RESET
goes high.
An order of magnitude reduction in dropout voltage and quiescent current over conventional LDO performance
is achieved by replacing the typical pnp pass transistor with a PMOS device.
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (maximum of 35 mV
at an output current of 100 mA for the TPS7350) and is directly proportional to the output current (see Figure 1).
Additionally , since the PMOS pass element is a voltage-driven device, the quiescent current is low and remains
constant, independent of output loading (typically 340 µA over the full range of output current, 0 mA to 500 mA).
These two key specifications yield a significant improvement in operating life for battery-powered systems.
The LDO family also features a sleep mode; applying a logic high signal to EN (enable) shuts down the regulator,
reducing the quiescent current to 0.5 µA maximum at TJ = 25°C.
The TPS73xx is offered in 2.5-V , 3-V , 3.3-V , 4.85-V, and 5-V fixed-voltage versions and in an adjustable version
(programmable over the range of 1.2 V to 9.75 V). Output voltage tolerance is specified as a maximum of 2%
over line, load, and temperature ranges (3% for the 2.5 V and the adjustable version). The TPS73xx family is
available in PDIP (8 pin), SO (8 pin) and TSSOP (20 pin) packages. The TSSOP has a maximum height of
1.2 mm.
Figure 1. Dropout Voltage Versus Output Current
0.25
0.2
0.1
0.05
0
0.15
0 50 100 150 200 250 300
0.3
350 400 450 500
TA = 25°C
TPS7348
TPS7350
Dropout Voltage – V
IO – Output Current – mA
TPS7333
TPS7330
TPS7325
Figure 2. Typical Application Configuration
†
TPS7325, TPS7330, TPS7333, TPS7348, TPS7350 (fixed-voltage
options)
‡
Capacitor selection is nontrivial. See application information
section for details.
SENSE
RESET
OUT
OUT
9
8
6
10
IN
IN
IN
EN
GND
321
20
15
14
13
V
I
0.1 µF
To System
Reset
CSR = 1 Ω
V
O
10 µF
+
TPS73xxPW
†
C
O
‡
250 kΩ
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUAR Y 1999
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS73xxY chip information
These chips, when properly assembled, display characteristics similar to those of the TPS73xxQ. Thermal
compression or ultrasonic bonding may be used on the doped aluminum bonding pads. Chips may be mounted
with conductive epoxy or a gold-silicon preform.
(6)
(4)
(3)
(7)
(2)
(1)
GND
FB
‡
OUT
RESET
IN
EN
TPS73xx
80
92
CHIP THICKNESS: 15 TYPICAL
BONDING PADS: 4 × 4 MINIMUM
TJmax = 150°C
TOLERANCES ARE ±10%.
ALL DIMENSIONS ARE IN MILS.
†
SENSE – Fixed voltage options only (TPS7325, TPS7330,
TPS7333, TPS7348, and TPS7350)
‡
FB – Adjustable version only (TPS7301)
BONDING PAD ASSIGNMENTS
SENSE
†
(5)
NOTE A. For most applications, OUT and SENSE should
be tied together as close as possible to the device;
for other implementations, refer to SENSE-pin
connection discussion in the applications
information section of this data sheet.
(3)
(4)
(5)
(6)
(7)
(2)
(1)
functional block diagram
¶
_
+
V
ref
OUT
SENSE§/FB
EN
IN
GND
R1
R2
RESET
_
+
TPS7301
TPS7325
TPS7330
TPS7333
TPS7348
TPS7350
DEVICE
UNITR1 R2
0
260
358
420
726
756
∞
233
233
233
233
233
Ω
kΩ
kΩ
kΩ
kΩ
kΩ
RESISTOR DIVIDER OPTIONS
§
For most applications, SENSE should be externally connected to OUT as close as possible to the device. For other implementations, refer to
SENSE-pin connection discussion in applications information section.
¶
Switch positions are shown with EN
low (active).
NOTE A. Resistors are nominal values only.
Delayed
Reset
¶¶
MOS transistors
Bilpolar transistors
Diodes
Capacitors
Resistors
COMPONENT COUNT
464
41
4
17
76
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUAR Y 1999
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing diagram
†
V
res
is the minimum input voltage for a valid RESET . The symbol V
res
is not currently listed within EIA or JEDEC standards
for semiconductor symbology.
V
I
V
res
†
V
res
t
t
t
V
O
Threshold
Voltage
RESET
Output
200 ms
Delay
200 ms
Delay
Output
Undefined
Output
Undefined
V
IT+
V
IT–
V
IT–
V
IT+
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
‡
Input voltage range
§
, VI, RESET, SENSE, EN –0.3 V to 11 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current, IO 2 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Tables 1 and 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature range, TJ –55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
§
All voltage values are with respect to network terminal ground.
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUAR Y 1999
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DISSIPATION RATING TABLE 1 – FREE-AIR TEMPERATURE (SEE FIGURE 3)
T
≤ 25°C DERATING FACTOR T
= 70°C T
= 125°C
PACKAGE
A
POWER RATING ABOVE TA = 25°CAPOWER RATINGAPOWER RATING
D 725 mW 5.8 mW/°C 464 mW 145 mW
P 1 175 mW 9.4 mW/°C 752 mW 235 mW
PW
†
700 mW 5.6 mW/°C 448 mW 140 mW
DISSIPATION RA TING TABLE 2 – CASE TEMPERATURE (SEE FIGURE 4)
T
≤ 25°C DERATING FACTOR T
= 70°C T
= 125°C
PACKAGE
C
POWER RATING ABOVE TC = 25°CCPOWER RATINGCPOWER RATING
D 2188 mW 9.4 mW/°C 1765 mW 1248 mW
P 2738 mW 21.9 mW/°C 1752 mW 548 mW
PW
†
4025 mW 32.2 mW/°C 2576 mW 805 mW
†
Refer to Thermal Information section for detailed power dissipation considerations when using the
TSSOP package.
Figure 3
PW Package
R
θJA
= 178°C/W
1200
800
400
0
25 50 75 100
– Maximum Continuous Dissipation – mW
MAXIMUM CONTINUOUS DISSIPATION
vs
FREE-AIR TEMPERATURE
125 150
1400
1000
600
200
P
D
TA – Free-Air Temperature – °C
D Package
R
θJA
= 172°C/W
P Package
R
θJA
= 106°C/W
Figure 4
2400
1600
800
0
25 50 75 100
– Maximum Continuous Dissipation – mW
3200
4000
MAXIMUM CONTINUOUS DISSIPATION
vs
CASE TEMPERATURE
4800
125 150
4400
3600
2800
2000
1200
400
P
D
TC – Case Temperature – °C
D Package
R
θJC
= 57°C/W
P Package
R
θJC
= 46°C/W
PW Package
R
θJC
= 37°C/W
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUAR Y 1999
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions
MIN MAX UNIT
TPS7301Q 2.47 10
TPS7325Q 3.1 10
V
p
TPS7330Q 3.5 10 V
Input voltage, V
I
†
TPS7333Q 3.77 10
TPS7348Q 5.2 10
V
TPS7350Q 5.33 10
High-level input voltage at EN, V
IH
2 V
Low-level input voltage at EN, V
IL
0.5 V
Output current range, I
O
0 500 mA
Operating virtual junction temperature range, T
J
–40 125 °C
†
Minimum input voltage defined in the recommended operating conditions is the maximum specified output voltage plus dropout voltage, VDO,
at the maximum specified load range. Since dropout voltage is a function of output current, the usable range can be extended for lighter loads.
To calculate the minimum input voltage for the maximum load current used in a given application, use the following equation:
V
I(min)
+
V
O(max)
)
V
DO(max load)
Because the TPS7301 is programmable, r
DS(on)
should be used to calculate VDO before applying the above equation. The equation for calculating
VDO from r
DS(on)
is given in Note 2 in the TPS7301 electrical characteristics table. The minimum value of 2.97 V is the absolute lower limit for
the recommended input voltage range for the TPS7301.
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUAR Y 1999
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at IO = 10 mA, EN = 0 V, Co = 4.7 µF (CSR‡ = 1 Ω), SENSE/FB shorted to
OUT (unless otherwise noted)
PARAMETER
TEST CONDITIONS
§
T
J
MIN TYP MAX
UNIT
EN ≤ 0.5 V, V
= V
+ 1 V
,
25°C 340 400
Ground current (active mode)
EN ≤ 0.5 V,
V
I
V
O
+ 1
V,
0 mA ≤ IO ≤ 500 mA
–40°C to 125°C 550
µ
A
p
25°C 0.01 0.5
Input current (standby mode)
EN
=
V
I
,
2.7 V ≤ V
I
≤ 10
V
–40°C to 125°C 2
µ
A
p
25°C 1.2 2
Output current limit
V
O
= 0 V,
V
I
= 10
V
–40°C to 125°C 2
A
Pass-element leakage current in standby
25°C 0.01 0.5
gy
mode
EN
=
V
I
,
2.7 V ≤ V
I
≤ 10 V
–40°C to 125°C 1
µ
A
25°C 0.02 0.5
RESET leak
age curren
t
N
ormal operation,V at
RESET
= 10
V
–40°C to 125°C 0.5
µ
A
Output voltage temperature coefficient –40°C to 125°C 61 75 ppm/°C
Thermal shutdown junction temperature 165 °C
2.5 V ≤ VI ≤ 6 V
°
°
2
EN logic high (standb
y mode
)
6 V ≤ VI ≤ 10 V
–
40°C to 125°C
2.7
V
25°C 0.5
EN logic l
ow (active mode
)
2.7 V ≤ V
I
≤ 10 V
–40°C to 125°C 0.5
V
EN hysteresis voltage 25°C 50 mV
25°C –0.5 0.001 0.5
EN i
nput curren
t
0 V ≤ V
I
≤ 10 V
–40°C to 125°C –0.5 0.5
µ
A
p
25°C 2.05 2.5
Minimum V
I
for active pass element
–40°C to 125°C 2.5
V
25°C 1 1.5
Mini
mum
V
I
f
or va
lid RESET
I
O(RESET)
= –
300 µA
–40°C to 125°C 1.9
V
‡
CSR (compensation series resistance) refers to the total series resistance, including the equivalent series resistance (ESR) of the capacitor, any
series resistance added externally , and PWB trace resistance to Co.
§
Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUAR Y 1999
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7301Q electrical characteristics at IO = 10 mA, V
I
= 3.5 V , EN = 0 V, Co = 4.7 µF (CSR† = 1 Ω), FB
shorted to OUT at device leads (unless otherwise noted)
PARAMETER
TEST CONDITIONS
‡
T
J
MIN TYP MAX
UNIT
25°C 1.182 V
Reference voltage (measured at FB)
2.5 V ≤ VI ≤ 10 V,
See Note 1
5 mA ≤ IO ≤ 500 mA,
–40°C to 125°C 1.147 1.217 V
Reference voltage temperature
coefficient
–40°C to 125°C 61 75 ppm/°C
25°C 0.7 1
V
I
= 2.4 V,
50 µA ≤ I
O
≤
150 mA
–40°C to 125°C 1
25°C 0.83 1.3
Pass-element series resistance
V
I
=
2.4 V
,
150 mA ≤ I
O
≤ 500 mA
–40°C to 125°C 1.3
(See Note 2)
25°C 0.52 0.85
Ω
V
I
= 2.9 V,
50 µA ≤ I
O
≤
500 mA
–40°C to 125°C 0.85
VI = 3.9 V, 50 µA ≤ IO ≤ 500 mA 25 °C 0.32
VI = 5.9 V, 50 µA ≤ IO ≤ 500 mA 25 °C 0.23
p
V
= 2.5 V to 10 V, 50 µA ≤ I
≤ 500 mA,
25°C 3 18
Input regulation
I
,
See Note 1
µ
O
,
–40°C to 125°C 25
mV
2.5 V ≤ V
≤ 10 V, I
= 5 mA to 500 mA,
25°C 5 14
p
I
,
See Note 1
O
,
–40°C to 125°C 25
mV
Output regulation
2.5 V ≤ V
≤ 10 V, I
= 50 µA to 500 mA,
25°C 7 22
I
,
See Note 1
O
µ ,
–40°C to 125°C 54
mV
25°C 48 59
pp
I
O
=
50 µA
–40°C to 125°C 44
Ripple rejection
f
=
120 H
z
I
= 500 mA,
25°C 45 54
dB
O
,
See Note 1
–40°C to 125°C 44
Output noise-spectral density f = 120 Hz 25°C 2
µV/√Hz
Co = 4.7 µF 25°C 95
Output noise voltage 10 Hz ≤ f ≤ 100 kHz
Co = 10 µF 25°C 89
µVrms
Co = 100 µF 25°C 74
RESET trip-threshold voltage
§
V
O(FB)
decreasing –40°C to 125°C 1.101 1.145 V
RESET hysteresis voltage
§
Measured at V
O(FB)
25°C 12 mV
p
25°C 0.1 0.4
RESET
output low voltage
§
V
I
= 2.13 V,
I
O(RESET)
=
400 µA
–40°C to 125°C 0.4
V
p
25°C –10 0.1 10
FB input current
–40°C to 125°C –20 20
nA
†
CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally , and PWB trace resistance
to Co.
‡
Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
§
Output voltage programmed to 2.5 V with closed-loop configuration (see application information).
NOTES: 1. When VI < 2.9 V and IO > 150 mA simultaneously, pass element r
DS(on)
increases (see Figure 33) to a point where the resulting
dropout voltage prevents the regulator from maintaining the specified tolerance range.
2. To calculate dropout voltage, use equation: VDO = IO
⋅ r
DS(on)
r
DS(on)
is a function of both output current and input voltage. This parametric table lists r
DS(on)
for VI = 2.4 V, 2.9 V, 3.9 V, and
5.9 V , which corresponds to dropout conditions for programmed output voltages of 2.5 V, 3 V, 4 V, and 6 V respectively . For other
programmed values, refer to Figure 33.
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUAR Y 1999
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7325Q electrical characteristics at IO = 10 mA, V
I
= 3.5 V , EN = 0 V, Co = 10 µF (CSR† = 1 Ω), SENSE
shorted to OUT (unless otherwise noted)
PARAMETER
TEST CONDITIONS
‡
T
J
MIN TYP MAX
UNIT
p
25°C 2.45 2.5 2.55
Output voltage
3.5 V ≤ VI ≤ 10 V, 5 mA ≤ IO ≤ 500 mA –40°C to 125°C 2.425 2.575
V
25°C 5
I
O
= 10 mA,
V
I
= 2.97
V
–40°C to 125°C 14
25°C 50 80
D
ropout voltage
§
I
O
=
100 mA
,
V
I
=
2.97 V
–40°C to 125°C 150
mV
25°C 270 400
I
O
=
500 mA
,
V
I
= 2.97
V
–40°C to 125°C 600
(2.97 V – V
)/I
, V
= 2.97 V ,
25°C 0.5 0.7
Pass-element series resistance
§
(
O)O
,
IO = 500 mA
I
,
–40°C to 125°C 1.4
Ω
p
25°C 6 20
Input regulation
V
I
=
3.5 V to 10 V
,
50 µA ≤ I
O
≤ 500 mA
–40°C to 125°C 25
mV
25°C 20 32
p
I
O
=
5 mA to 500 mA
,3.5 V ≤
V
I
≤ 10 V
–40°C to 125°C 50
mV
Output regulation
25°C 28 60
I
O
= 50 µA to
500 mA
,3.5 V ≤
V
I
≤ 10
V
–40°C to 125°C 100
mV
25°C 50 53
pp
I
O
=
50 µA
–40°C to 125°C 49
Ripple rejection
f
=
120 H
z
25°C 49 53
dB
I
O
=
500 mA
–40°C to 125°C 32
Output noise-spectral density f = 120 Hz 25°C 2
µV/√Hz
Co = 4.7 µF
25°C 274
Output noise voltage 10 Hz ≤ f ≤ 100 kHz
Co = 10 µF
25°C 228
µVrms
Co = 100 µF
25°C 159
RESET trip-threshold voltage
VO decreasing –40°C to 125°C 2.23 2.32 2.39 V
p
25°C 0.14 0.4
RESET output low voltage
V
I
=
2.1 V
,
I
O(RESET)
= –
0.8 mA
–40°C to 125°C 0.4
V
†
CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally , and PWB trace resistance
to Co.
‡
Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
§
Dropout test and pass-element series resistance test are not production tested. Test method requires SENSE terminal to be disconnected from
output voltage.
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUAR Y 1999
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7330Q electrical characteristics at IO = 10 mA, V
I
= 4 V , EN = 0 V , Co = 4.7 µF (CSR† = 1 Ω), SENSE
shorted to OUT (unless otherwise noted)
PARAMETER
TEST CONDITIONS
‡
T
J
MIN TYP MAX
UNIT
p
25°C 3
Output voltage
4 V ≤ VI ≤ 10 V, 5 mA ≤ IO ≤ 500 mA –40°C to 125°C 2.94 3.06
V
25°C 5.2 7
I
O
= 10 mA,
V
I
= 2.94
V
–40°C to 125°C 10
25°C 52 75
D
ropout voltage
I
O
=
100 mA
,
V
I
=
2.94 V
–40°C to 125°C 100
mV
25°C 267 450
I
O
=
500 mA
,
V
I
= 2.94
V
–40°C to 125°C 500
(2.94 V – V
)/I
, V
= 2.94 V ,
25°C 0.5 0.7
Pass-element series resistance
(
O)O
,
IO = 500 mA
I
,
–40°C to 125°C 1
Ω
p
25°C 6 23
Input regulation
V
I
=
4 V to 10 V
,
50 µA ≤ I
O
≤ 500 mA
–40°C to 125°C 29
mV
25°C 20 32
p
I
O
=
5 mA to 500 mA
,4 V ≤
V
I
≤ 10 V
–40°C to 125°C 60
mV
Output regulation
25°C 28 60
I
O
= 50 µA to
500 mA
,4 V ≤
V
I
≤ 10
V
–40°C to 125°C 120
mV
25°C 43 53
pp
I
O
=
50 µA
–40°C to 125°C 40
Ripple rejection
f
=
120 H
z
25°C 39 53
dB
I
O
=
500 mA
–40°C to 125°C 36
Output noise-spectral density f = 120 Hz 25°C 2
µV/√Hz
Co = 4.7 µF
25°C 274
Output noise voltage 10 Hz ≤ f ≤ 100 kHz
Co = 10 µF
25°C 228
µVrms
Co = 100 µF
25°C 159
RESET trip-threshold voltage
VO decreasing –40°C to 125°C 2.58 2.64 2.7 V
p
25°C 0.14 0.4
RESET output low voltage
V
I
=
2.6 V
,
I
O(RESET)
= –
0.8 mA
–40°C to 125°C 0.4
V
†
CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally , and PWB trace resistance
to Co.
‡
Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUAR Y 1999
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7333Q electrical characteristics at IO = 10 mA, V
I
= 4.3 V, EN = 0 V, Co = 4.7 µF (CSR† = 1 Ω),
SENSE shorted to OUT (unless otherwise noted)
PARAMETER
TEST CONDITIONS
‡
T
J
MIN TYP MAX
UNIT
p
25°C 3.3
Output voltage
4.3 V ≤ VI ≤ 10 V, 5 mA ≤ IO ≤ 500 mA –40°C to 125°C 3.23 3.37
V
25°C 4.5 7
I
O
= 10 mA,
V
I
= 3.23
V
–40°C to 125°C 8
25°C 44 60
D
ropout voltage
I
O
=
100 mA
,
V
I
=
3.23 V
–40°C to 125°C 80
mV
25°C 235 300
I
O
=
500 mA
,
V
I
= 3.23
V
–40°C to 125°C 400
(3.23 V – V
)/I
, V
= 3.23 V ,
25°C 0.44 0.6
Pass-element series resistance
(
O)O
,
IO = 500 mA
I
,
–40°C to 125°C 0.8
Ω
p
25°C 6 23
Input regulation
V
I
=
4.3 V to 10 V
,
50 µA ≤ I
O
≤ 500 mA
–40°C to 125°C 29
mV
25°C 21 38
p
I
O
=
5 mA to 500 mA, 4.3 V ≤ V
I
≤ 10 V
–40°C to 125°C 75
mV
Output regulation
25°C 31 60
I
O
= 50 µA to
500 mA, 4.3 V ≤ V
I
≤ 10
V
–40°C to 125°C 120
mV
25°C 43 51
pp
I
O
=
50 µA
–40°C to 125°C 40
Ripple rejection
f
=
120 H
z
25°C 39 49
dB
I
O
=
500 mA
–40°C to 125°C 36
Output noise-spectral density f = 120 Hz 25°C 2
µV/√Hz
Co = 4.7 µF
25°C 274
Output noise voltage 10 Hz ≤ f ≤ 100 kHz
Co = 10 µF
25°C 228
µVrms
Co = 100 µF
25°C 159
RESET trip-threshold voltage
VO decreasing –40°C to 125°C 2.868 V
RESET hysteresis voltage
25°C 18 mV
p
25°C 0.17 0.4
RESET output low voltage
V
I
= 2.8 V,
I
O(RESET)
= –1
mA
–40°C to 125°C 0.4
V
†
CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally , and PWB trace resistance
to Co.
‡
Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUAR Y 1999
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7348Q electrical characteristics at IO = 10 mA, V
I
= 5.85 V, EN = 0 V, Co = 4.7 µF (CSR† = 1 Ω),
SENSE shorted to OUT (unless otherwise noted)
PARAMETER
TEST CONDITIONS
‡
T
J
MIN TYP MAX
UNIT
p
25°C 4.85
Output voltage
5.85 V ≤ VI ≤ 10 V, 5 mA ≤ IO ≤ 500 mA –40°C to 125°C 4.75 4.95
V
25°C 2.9 6
I
O
= 10 mA,
V
I
= 4.75
V
–40°C to 125°C 8
25°C 28 37
D
ropout voltage
I
O
=
100 mA
,
V
I
=
4.75 V
–40°C to 125°C 54
mV
25°C 150 180
I
O
=
500 mA
,
V
I
= 4.75
V
–40°C to 125°C 250
(4.75 V – V
)/I
, V
= 4.75 V ,
25°C 0.28 0.37
Pass-element series resistance
(
O)O
,
IO = 500 mA
I
,
–40°C to 125°C 0.52
Ω
p
25°C 9 35
Input regulation
V
I
=
5.85 V to 10 V
,
50 µA ≤ I
O
≤ 500 mA
–40°C to 125°C 37
mV
25°C 28 42
p
I
O
=
5 mA to 500 mA, 5.85 V ≤ V
I
≤ 10 V
–40°C to 125°C 80
mV
Output regulation
25°C 42 65
I
O
= 50 µA to
500 mA, 5.85 V ≤ V
I
≤ 10
V
–40°C to 125°C 130
mV
25°C 42 53
pp
I
O
=
50 µA
–40°C to 125°C 39
Ripple rejection
f
=
120 H
z
25°C 39 50
dB
I
O
=
500 mA
–40°C to 125°C 35
Output noise-spectral density f = 120 Hz 25°C 2 µV/√Hz
Co = 4.7 µF
25°C 410
Output noise voltage 10 Hz ≤ f ≤ 100 kHz
Co = 10 µF
25°C 328
µVrms
Co = 100 µF
25°C 212
RESET trip-threshold voltage
VO decreasing –40°C to 125°C 4.5 4.7 V
RESET hysteresis voltage
25°C 26 mV
p
25°C 0.2 0.4
RESET output low voltage
I
O(RESET)
= –
1.2 mA,V
I
=
4.12 V
–40°C to 125°C 0.4
V
†
CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally , and PWB trace resistance
to Co.
‡
Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUAR Y 1999
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7350Q electrical characteristics at IO = 10 mA, V
I
= 6 V , EN = 0 V , Co = 4.7 µF (CSR† = 1 Ω), SENSE
shorted to OUT (unless otherwise noted)
PARAMETER
TEST CONDITIONS
‡
T
J
MIN TYP MAX
UNIT
p
25°C 5
Output voltage
6 V ≤ VI ≤ 10 V, 5 mA ≤ IO ≤ 500 mA –40°C to 125°C 4.9 5.1
V
25°C 2.9 6
I
O
= 10 mA,
V
I
= 4.88
V
–40°C to 125°C 8
25°C 27 35
D
ropout voltage
I
O
=
100 mA
,
V
I
=
4.88 V
–40°C to 125°C 50
mV
25°C 146 170
I
O
=
500 mA
,
V
I
= 4.88
V
–40°C to 125°C 230
(4.88 V – V
)/I
, V
= 4.88 V ,
25°C 0.27 0.35
Pass-element series resistance
(
O)O
,
IO = 500 mA
I
,
–40°C to 125°C 0.5
Ω
p
25°C 4 25
Input regulation
V
I
=
6 V to 10 V
,
50 µA ≤ I
O
≤ 500 mA
–40°C to 125°C 45
mV
25°C 30 45
p
I
O
=
5 mA to 500 mA
,6 V ≤
V
I
≤ 10 V
–40°C to 125°C 86
mV
Output regulation
25°C 45 65
I
O
= 50 µA to
500 mA
,6 V ≤
V
I
≤ 10
V
–40°C to 125°C 140
mV
25°C 43 53
pp
I
O
=
50 µA
–40°C to 125°C 38
Ripple rejection
f
=
120 H
z
25°C 41 51
dB
I
O
=
500 mA
–40°C to 125°C 36
Output noise-spectral density f = 120 Hz 25°C 2
µV/√Hz
Co = 4.7 µF
25°C 430
Output noise voltage 10 Hz ≤ f ≤ 100 kHz
Co = 10 µF
25°C 345
µVrms
Co = 100 µF
25°C 220
RESET trip-threshold voltage
VO decreasing –40°C to 125°C 4.55 4.75 V
RESET hysteresis voltage
25°C 28 mV
p
25°C 0.15 0.4
RESET output low voltage
I
O(RESET)
= –1.2 mA,
V
I
= 4.25
V
–40°C to 125°C 0.4
V
†
CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally , and PWB trace resistance
to Co.
‡
Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
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