Texas Instruments TPS73150DBVTG4, TPS73150 Datasheet
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GNDEN NR
IN OUT
V
IN
V
OUT
Optional
Optional Optional
Typical Application Circuit for Fixed-Voltage Versions
DBV PACKAGE
SOT23
(TOP VIEW)
IN
GND
EN NR/FB
OUT1
2
3 4
5
TPS731xx
Cap-Free, NMOS, 150mA Low Dropout Regulator
with Reverse Current Protection
FEATURES DESCRIPTION
• Stable with No Output Capacitor or Any Value
or Type of Capacitor
• Input Voltage Range of 1.7V to 5.5V
• Ultralow Dropout Voltage: 30mV Typ
• Excellent Load Transient Response—with or
without Optional Output Capacitor
• New NMOS Topology Provides Low Reverse
Leakage Current
• Low Noise: 30 µ V
• 0.5% Initial Accuracy
• 1% Overall Accuracy over Line, Load, and
Temperature
• Less Than 1 µ A Max IQin Shutdown Mode
• Thermal Shutdown and Specified Min/Max
Current Limit Protection
• Available in Multiple Output Voltage Versions
– Fixed Outputs of 1.20V to 5.0V
– Adjustable Outputs from 1.20V to 5.5V
– Custom Outputs Available
RMS
Typ (10kHz to 100kHz)
TPS731xx
SBVS034J – SEPTEMBER 2003 – REVISED MAY 2007
The TPS731xx family of low-dropout (LDO) linear
voltage regulators uses a new topology: an NMOS
pass element in a voltage-follower configuration. This
topology is stable using output capacitors with low
ESR, and even allows operation without a capacitor.
It also provides high reverse blockage (low reverse
current) and ground pin current that is nearly
constant over all values of output current.
The TPS731xx uses an advanced BiCMOS process
to yield high precision while delivering very low
dropout voltages and low ground pin current. Current
consumption, when not enabled, is under 1 µ A and
ideal for portable applications. The extremely low
output noise (30 µ V
powering VCOs. These devices are protected by
thermal shutdown and foldback current limit.
RMS
with 0.1 µ F C
) is ideal for
NR
APPLICATIONS
• Portable/Battery-Powered Equipment
• Post-Regulation for Switching Supplies
• Noise-Sensitive Circuitry such as VCOs
• Point of Load Regulation for DSPs, FPGAs,
ASICs, and Microprocessors
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2003–2007, Texas Instruments Incorporated
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TPS731xx
SBVS034J – SEPTEMBER 2003 – REVISED MAY 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
ORDERING INFORMATION
PRODUCT V
TPS731 xxyyyz XX is nominal output voltage (for example, 25 = 2.5V, 01 = Adjustable
(1)
(2)
OUT
(3)
).
YYY is package designator.
Z is package quantity.
(1) For the most current specification and package information, refer to the Package Option Addendum located at the end of this datasheet
or see the TI website at www.ti.com .
(2) Most output voltages of 1.25V and 1.3V to 5.0V in 100mV increments are available through the use of innovative factory EEPROM
programming. Minimum order quantities apply; contact factory for details and availability.
(3) For fixed 1.20V operation, tie FB to OUT.
ABSOLUTE MAXIMUM RATINGS
over operating junction temperature range unless otherwise noted
VINrange –0.3 to 6.0 V
V
range –0.3 to 6.0 V
EN
V
range –0.3 to 5.5 V
OUT
VNR, V
Peak output current Internally limited
Output short-circuit duration Indefinite
Continuous total power dissipation See Dissipation Ratings Table
Junction temperature range, T
Storage temperature range –65 to +150 °C
ESD rating, HBM 2 kV
ESD rating, CDM 500 V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
range –0.3 to 6.0 V
FB
J
only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics
is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
(1)
TPS731xx UNIT
–55 to +150 °C
POWER DISSIPATION RATINGS
BOARD PACKAGE R
(2)
Low-K
(3)
High-K
DBV 64 ° C/W 255 ° C/W 3.9mW/ ° C 390mW 215mW 155mW
DBV 64 ° C/W 180 ° C/W 5.6mW/ ° C 560mW 310mW 225mW
Θ JC
(1)
R
Θ JA
DERATING FACTOR TA≤ 25 ° C TA= 70 ° C TA= 85 ° C
ABOVE TA= 25°C POWER RATING POWER RATING POWER RATING
(1) See Power Dissipation in the Applications section for more information related to thermal design.
(2) The JEDEC Low-K (1s) board design used to derive this data was a 3 inch x 3 inch, two-layer board with 2-ounce copper traces on top
of the board.
(3) The JEDEC High-K (2s2p) board design used to derive this data was a 3 inch x 3 inch, multilayer board with 1-ounce internal power and
ground planes and 2-ounce copper traces on the top and bottom of the board.
2
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TPS731xx
SBVS034J – SEPTEMBER 2003 – REVISED MAY 2007
ELECTRICAL CHARACTERISTICS
Over operating temperature range (T
C
= 0.1 µ F, unless otherwise noted. Typical values are at TJ= +25 ° C.
OUT
= -40 ° C to +125 ° C), V
J
= V
IN
OUT(nom)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
IN
V
FB
Input voltage range
Internal reference (TPS73101) TJ= +25 ° C 1.198 1.20 1.210 V
Output voltage range (TPS73101)
V
OUT
∆ V
%/ ∆ V
OUT
∆ V
%/ ∆ I
OUT
V
DO
Accuracy
Line regulation
IN
Load regulation %/mA
OUT
Dropout voltage
(V
(1) (3)
= V
IN
OUT
ZO(DO) Output impedance in dropout 1.7 V ≤ VIN≤ V
I
CL
I
SC
I
REV
I
GND
I
SHDN
I
FB
PSRR dB
V
N
t
STR
Output current limit V
Short-circuit current V
Reverse leakage current
Ground pin current µ A
Shutdown current (I
FB pin current (TPS73101) 0.1 0.3 µ A
Power-supply rejection ratio
(ripple rejection)
Output noise voltage
BW = 10Hz - 100kHz
Startup time 600 µ s
(1)
(2)
Nominal TJ= +25 ° C –0.5 +0.5
V
+ 0.5V ≤ VIN≤ 5.5V;
OUT
10 mA ≤ I
V
OUT(nom)
1mA ≤ I
10mA ≤ I
I
= 150mA 30 100 mV
OUT
OUT
OUT
≤ 0.5V, 0V ≤ VIN≤ V
EN
I
= 10mA (IQ) 400 550
OUT
I
= 150mA 550 750
OUT
V
≤ 0.5V, V
EN
–40 ° C ≤ TJ≤ +100 ° C
f = 100Hz, I
f = 10kHz, I
C
OUT
C
OUT
V
OUT
C
OUT
≤ 150mA
OUT
+ 0.5V ≤ VIN≤ 5.5V 0.01 %/V
≤ 150mA 0.002
OUT
≤ 150mA 0.0005
OUT
+ V
OUT
DO
= 0.9 × V
OUT(nom)
= 0V 200 mA
OUT
≤ VIN≤ 5.5,
OUT
= 150 mA 58
OUT
= 150 mA 37
OUT
= 10 µ F, No C
= 10 µ F, C
NR
= 0.01 µ F 8.5 × V
NR
= 3V, RL= 30 Ω
= 1 µ F, C
NR
= 0.01 µ F
(nom) – 0.1V)
VIN, I
(1)
(4)
GND
, and T –1.0 ± 0.5 +1.0
OUT
(5)
(–IIN) V
) 0.02 1 µ A
VEN(HI) Enable high (enabled) 1.7 V
VEN(LO) Enable low (shutdown) 0 0.5 V
IEN(HI) Enable pin current (enabled) V
T
SD
T
J
Thermal shutdown temperature ° C
Operating junction temperature –40 +125 ° C
= 5.5V 0.02 0.1 µ A
EN
Shutdown Temp increasing +160
Reset Temp decreasing +140
(1)
+ 0.5V
, I
OUT
= 10mA, V
= 1.7V, and
EN
1.7 5.5 V
V
FB
5.5 – V
DO
0.25 Ω
150 360 500 mA
0.1 10 µA
27 × V
OUT
OUT
IN
V
%
µ V
RMS
V
(1) Minimum VIN= V
(2) TPS73101 is tested at V
(3) Tolerance of external resistors not included in this specification.
(4) V
(5) Fixed-voltage versions only; refer to the Applications section for more information.
is not measured for fixed output versions with V
DO
+ V
OUT
or 1.7V, whichever is greater.
DO
= 2.5V.
OUT
OUT(nom)
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< 1.8V since minimum VIN= 1.7V.
3
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Servo
Error
Amp
Ref
27k
Ω
8k
Ω
Current
Limit
Thermal
Protection
Bandgap
NR
OUT
R
1
R
2
EN
GND
IN
R1+ R2= 80k
Ω
4MHz
Charge Pump
V
O
1.2V
1.5V
1.8V
2.5V
2.8V
3.0V
3.3V
R
1
Short
23.2kΩ
28.0kΩ
39.2kΩ
44.2kΩ
46.4kΩ
52.3kΩ
R
2
Open
95.3kΩ
56.2kΩ
36.5kΩ
33.2kΩ
30.9kΩ
30.1kΩ
Table 1. Standard 1%
Resistor Values for
Common Output Voltages
NOTE: V
OUT
= (R1 + R2)/R2 × 1.204;
R1R2 ≅ 19kΩ for best
accuracy.
Servo
Error
Amp
Ref
Current
Limit
Thermal
Protection
Bandgap
OUT
FB
R
1
R
2
EN
GND
IN
80k
Ω
8k
Ω
27k
Ω
4MHz
Charge Pump
TPS731xx
SBVS034J – SEPTEMBER 2003 – REVISED MAY 2007
FUNCTIONAL BLOCK DIAGRAMS
4
Figure 1. Fixed Voltage Version
Figure 2. Adjustable Voltage Version
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DBV PACKAGE
SOT23
(TOP VIEW)
IN
GND
EN NR/FB
OUT1
2
3 4
5
TPS731xx
SBVS034J – SEPTEMBER 2003 – REVISED MAY 2007
PIN ASSIGNMENTS
TERMINAL FUNCTIONS
TERMINAL
NAME (DBV)
SOT23
PIN NO.
IN 1 Input supply
GND 2 Ground
EN 3 Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into shutdown
mode. Refer to the Shutdown section under Applications Information for more details. EN can be connected to
IN if not used.
NR 4 Fixed voltage versions only—connecting an external capacitor to this pin bypasses noise generated by the
internal bandgap, reducing output noise to very low levels.
FB 4 Adjustable voltage version only—this is the input to the control loop error amplifier, and is used to set the
output voltage of the device.
OUT 5 Output of the regulator. There are no output capacitor requirements for stability.
DESCRIPTION
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0.5
0.4
0.3
0.2
0.1
0
−
0.1
−
0.2
−
0.3
−
0.4
−
0.5
Change in V
OUT
(%)
0 15 30 45 60 75 90 105 120 135 150
I
OUT
(mA)
Referred to I
OUT
= 10mA
0.20
0.15
0.10
0.05
0
−
0.05
−
0.10
−
0.15
−
0.20
Change in V
OUT
(%)
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
V
IN
−
V
OUT
(V)
+125_C
+25_C
−
40_C
Referred to VIN= V
OUT
+ 0.5V at I
OUT
= 10mA
50
40
30
20
10
0
V
DO
(mV)
0 30 60 90 120 150
I
OUT
(mA)
+125_C
TPS73125DBV
+25_C
−
40_C
50
40
30
20
10
0
V
DO
(mV)
−
50−25 0 25 50 75 100 125
Temperature (_C)
TPS73125DBV
I
OUT
= 150mA
30
25
20
15
10
5
0
Percent of Units (%)
−
1.0
−
0.9
−
0.8
−
0.7
−
0.6
−
0.5
−
0.4
−
0.3
−
0.2
−
0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
V
OUT
Error (%)
I
OUT
= 10mA
18
16
14
12
10
8
6
4
2
0
Percent of Units (%)
−
100
−
90
−
80
−
70
−
60
−
50
−
40
−
30
−
20
−
10
0
10
20
30
40
50
60
70
80
90
100
Worst Case dV
OUT
/dT (ppm/_C)
I
OUT
= 10mA
All Voltage Versions
TPS731xx
SBVS034J – SEPTEMBER 2003 – REVISED MAY 2007
For all voltage versions at TJ= +25 ° C, V
LOAD REGULATION LINE REGULATION
Figure 3. Figure 4.
DROPOUT VOLTAGE vs OUTPUT CURRENT DROPOUT VOLTAGE vs TEMPERATURE
TYPICAL CHARACTERISTICS
= V
IN
OUT(nom)
+ 0.5V, I
noted.
OUT
= 10mA, V
= 1.7V, and C
EN
OUT
= 0.1 µ F, unless otherwise
OUTPUT VOLTAGE ACCURACY HISTOGRAM OUTPUT VOLTAGE DRIFT HISTOGRAM
6
Figure 5. Figure 6.
Figure 7. Figure 8.
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700
600
500
400
300
200
100
0
I
GND
(
µ
A)
0 30 60 90 120 150
I
OUT
(mA)
VIN= 5.5V
VIN= 4V
VIN= 2V
700
600
500
400
300
200
100
0
I
GND
(
µ
A)
−
50−25 0 25 50 75 100 125
Temperature (_C)
I
OUT
= 150mA
VIN= 5.5V
VIN= 4V
VIN= 2V
1
0.1
0.01
I
GND
(
µ
A)
−
50−25 0 25 50 75 100 125
Temperature (_C)
V
ENABLE
= 0.5V
VIN= VO+ 0.5V
400
350
300
250
200
150
100
50
0
Current Limit (mA)
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
V
OUT
(V)
TPS73133
I
CL
I
SC
500
450
400
350
300
250
200
150
Current Limit (mA)
1.5 2.5 3.0 3.5 4.0 4.5 5.02.0 5.5
VIN(V)
500
450
400
350
300
250
200
150
Current Limit (mA)
−
50
−
25 0 25 50 75 100 125
Temperature (_C)
For all voltage versions at TJ= +25 ° C, V
noted.
GROUND PIN CURRENT vs OUTPUT CURRENT GROUND PIN CURRENT vs TEMPERATURE
Figure 9. Figure 10.
TYPICAL CHARACTERISTICS (continued)
= V
IN
OUT(nom)
+ 0.5V, I
OUT
= 10mA, V
SBVS034J – SEPTEMBER 2003 – REVISED MAY 2007
= 1.7V, and C
EN
OUT
= 0.1 µ F, unless otherwise
TPS731xx
GROUND PIN CURRENT in SHUTDOWN CURRENT LIMIT vs V
vs TEMPERATURE (FOLDBACK)
Figure 11. Figure 12.
CURRENT LIMIT vs V
IN
CURRENT LIMIT vs TEMPERATURE
OUT
Figure 13. Figure 14.
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