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GNDEN NR
IN OUT
V
IN
V
OUT
Optional
Optional Optional
Typical Application Circuit for Fixed-Voltage Versions
DBV PACKAGE
SOT23
(TOP VIEW)
IN
GND
EN NR/FB
OUT1
2
3 4
5
TPS731xx
Cap-Free, NMOS, 150mA Low Dropout Regulator
with Reverse Current Protection
FEATURES DESCRIPTION
• Stable with No Output Capacitor or Any Value
or Type of Capacitor
• Input Voltage Range of 1.7V to 5.5V
• Ultralow Dropout Voltage: 30mV Typ
• Excellent Load Transient Response—with or
without Optional Output Capacitor
• New NMOS Topology Provides Low Reverse
Leakage Current
• Low Noise: 30 µ V
• 0.5% Initial Accuracy
• 1% Overall Accuracy over Line, Load, and
Temperature
• Less Than 1 µ A Max IQin Shutdown Mode
• Thermal Shutdown and Specified Min/Max
Current Limit Protection
• Available in Multiple Output Voltage Versions
– Fixed Outputs of 1.20V to 5.0V
– Adjustable Outputs from 1.20V to 5.5V
– Custom Outputs Available
RMS
Typ (10kHz to 100kHz)
TPS731xx
SBVS034J – SEPTEMBER 2003 – REVISED MAY 2007
The TPS731xx family of low-dropout (LDO) linear
voltage regulators uses a new topology: an NMOS
pass element in a voltage-follower configuration. This
topology is stable using output capacitors with low
ESR, and even allows operation without a capacitor.
It also provides high reverse blockage (low reverse
current) and ground pin current that is nearly
constant over all values of output current.
The TPS731xx uses an advanced BiCMOS process
to yield high precision while delivering very low
dropout voltages and low ground pin current. Current
consumption, when not enabled, is under 1 µ A and
ideal for portable applications. The extremely low
output noise (30 µ V
powering VCOs. These devices are protected by
thermal shutdown and foldback current limit.
RMS
with 0.1 µ F C
) is ideal for
NR
APPLICATIONS
• Portable/Battery-Powered Equipment
• Post-Regulation for Switching Supplies
• Noise-Sensitive Circuitry such as VCOs
• Point of Load Regulation for DSPs, FPGAs,
ASICs, and Microprocessors
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2003–2007, Texas Instruments Incorporated
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TPS731xx
SBVS034J – SEPTEMBER 2003 – REVISED MAY 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
ORDERING INFORMATION
PRODUCT V
TPS731 xxyyyz XX is nominal output voltage (for example, 25 = 2.5V, 01 = Adjustable
(1)
(2)
OUT
(3)
).
YYY is package designator.
Z is package quantity.
(1) For the most current specification and package information, refer to the Package Option Addendum located at the end of this datasheet
or see the TI website at www.ti.com .
(2) Most output voltages of 1.25V and 1.3V to 5.0V in 100mV increments are available through the use of innovative factory EEPROM
programming. Minimum order quantities apply; contact factory for details and availability.
(3) For fixed 1.20V operation, tie FB to OUT.
ABSOLUTE MAXIMUM RATINGS
over operating junction temperature range unless otherwise noted
VINrange –0.3 to 6.0 V
V
range –0.3 to 6.0 V
EN
V
range –0.3 to 5.5 V
OUT
VNR, V
Peak output current Internally limited
Output short-circuit duration Indefinite
Continuous total power dissipation See Dissipation Ratings Table
Junction temperature range, T
Storage temperature range –65 to +150 °C
ESD rating, HBM 2 kV
ESD rating, CDM 500 V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
range –0.3 to 6.0 V
FB
J
only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics
is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
(1)
TPS731xx UNIT
–55 to +150 °C
POWER DISSIPATION RATINGS
BOARD PACKAGE R
(2)
Low-K
(3)
High-K
DBV 64 ° C/W 255 ° C/W 3.9mW/ ° C 390mW 215mW 155mW
DBV 64 ° C/W 180 ° C/W 5.6mW/ ° C 560mW 310mW 225mW
Θ JC
(1)
R
Θ JA
DERATING FACTOR TA≤ 25 ° C TA= 70 ° C TA= 85 ° C
ABOVE TA= 25°C POWER RATING POWER RATING POWER RATING
(1) See Power Dissipation in the Applications section for more information related to thermal design.
(2) The JEDEC Low-K (1s) board design used to derive this data was a 3 inch x 3 inch, two-layer board with 2-ounce copper traces on top
of the board.
(3) The JEDEC High-K (2s2p) board design used to derive this data was a 3 inch x 3 inch, multilayer board with 1-ounce internal power and
ground planes and 2-ounce copper traces on the top and bottom of the board.
2
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TPS731xx
SBVS034J – SEPTEMBER 2003 – REVISED MAY 2007
ELECTRICAL CHARACTERISTICS
Over operating temperature range (T
C
= 0.1 µ F, unless otherwise noted. Typical values are at TJ= +25 ° C.
OUT
= -40 ° C to +125 ° C), V
J
= V
IN
OUT(nom)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
IN
V
FB
Input voltage range
Internal reference (TPS73101) TJ= +25 ° C 1.198 1.20 1.210 V
Output voltage range (TPS73101)
V
OUT
∆ V
%/ ∆ V
OUT
∆ V
%/ ∆ I
OUT
V
DO
Accuracy
Line regulation
IN
Load regulation %/mA
OUT
Dropout voltage
(V
(1) (3)
= V
IN
OUT
ZO(DO) Output impedance in dropout 1.7 V ≤ VIN≤ V
I
CL
I
SC
I
REV
I
GND
I
SHDN
I
FB
PSRR dB
V
N
t
STR
Output current limit V
Short-circuit current V
Reverse leakage current
Ground pin current µ A
Shutdown current (I
FB pin current (TPS73101) 0.1 0.3 µ A
Power-supply rejection ratio
(ripple rejection)
Output noise voltage
BW = 10Hz - 100kHz
Startup time 600 µ s
(1)
(2)
Nominal TJ= +25 ° C –0.5 +0.5
V
+ 0.5V ≤ VIN≤ 5.5V;
OUT
10 mA ≤ I
V
OUT(nom)
1mA ≤ I
10mA ≤ I
I
= 150mA 30 100 mV
OUT
OUT
OUT
≤ 0.5V, 0V ≤ VIN≤ V
EN
I
= 10mA (IQ) 400 550
OUT
I
= 150mA 550 750
OUT
V
≤ 0.5V, V
EN
–40 ° C ≤ TJ≤ +100 ° C
f = 100Hz, I
f = 10kHz, I
C
OUT
C
OUT
V
OUT
C
OUT
≤ 150mA
OUT
+ 0.5V ≤ VIN≤ 5.5V 0.01 %/V
≤ 150mA 0.002
OUT
≤ 150mA 0.0005
OUT
+ V
OUT
DO
= 0.9 × V
OUT(nom)
= 0V 200 mA
OUT
≤ VIN≤ 5.5,
OUT
= 150 mA 58
OUT
= 150 mA 37
OUT
= 10 µ F, No C
= 10 µ F, C
NR
= 0.01 µ F 8.5 × V
NR
= 3V, RL= 30 Ω
= 1 µ F, C
NR
= 0.01 µ F
(nom) – 0.1V)
VIN, I
(1)
(4)
GND
, and T –1.0 ± 0.5 +1.0
OUT
(5)
(–IIN) V
) 0.02 1 µ A
VEN(HI) Enable high (enabled) 1.7 V
VEN(LO) Enable low (shutdown) 0 0.5 V
IEN(HI) Enable pin current (enabled) V
T
SD
T
J
Thermal shutdown temperature ° C
Operating junction temperature –40 +125 ° C
= 5.5V 0.02 0.1 µ A
EN
Shutdown Temp increasing +160
Reset Temp decreasing +140
(1)
+ 0.5V
, I
OUT
= 10mA, V
= 1.7V, and
EN
1.7 5.5 V
V
FB
5.5 – V
DO
0.25 Ω
150 360 500 mA
0.1 10 µA
27 × V
OUT
OUT
IN
V
%
µ V
RMS
V
(1) Minimum VIN= V
(2) TPS73101 is tested at V
(3) Tolerance of external resistors not included in this specification.
(4) V
(5) Fixed-voltage versions only; refer to the Applications section for more information.
is not measured for fixed output versions with V
DO
+ V
OUT
or 1.7V, whichever is greater.
DO
= 2.5V.
OUT
OUT(nom)
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< 1.8V since minimum VIN= 1.7V.
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Servo
Error
Amp
Ref
27k
Ω
8k
Ω
Current
Limit
Thermal
Protection
Bandgap
NR
OUT
R
1
R
2
EN
GND
IN
R1+ R2= 80k
Ω
4MHz
Charge Pump
V
O
1.2V
1.5V
1.8V
2.5V
2.8V
3.0V
3.3V
R
1
Short
23.2kΩ
28.0kΩ
39.2kΩ
44.2kΩ
46.4kΩ
52.3kΩ
R
2
Open
95.3kΩ
56.2kΩ
36.5kΩ
33.2kΩ
30.9kΩ
30.1kΩ
Table 1. Standard 1%
Resistor Values for
Common Output Voltages
NOTE: V
OUT
= (R1 + R2)/R2 × 1.204;
R1R2 ≅ 19kΩ for best
accuracy.
Servo
Error
Amp
Ref
Current
Limit
Thermal
Protection
Bandgap
OUT
FB
R
1
R
2
EN
GND
IN
80k
Ω
8k
Ω
27k
Ω
4MHz
Charge Pump
TPS731xx
SBVS034J – SEPTEMBER 2003 – REVISED MAY 2007
FUNCTIONAL BLOCK DIAGRAMS
4
Figure 1. Fixed Voltage Version
Figure 2. Adjustable Voltage Version
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DBV PACKAGE
SOT23
(TOP VIEW)
IN
GND
EN NR/FB
OUT1
2
3 4
5
TPS731xx
SBVS034J – SEPTEMBER 2003 – REVISED MAY 2007
PIN ASSIGNMENTS
TERMINAL FUNCTIONS
TERMINAL
NAME (DBV)
SOT23
PIN NO.
IN 1 Input supply
GND 2 Ground
EN 3 Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into shutdown
mode. Refer to the Shutdown section under Applications Information for more details. EN can be connected to
IN if not used.
NR 4 Fixed voltage versions only—connecting an external capacitor to this pin bypasses noise generated by the
internal bandgap, reducing output noise to very low levels.
FB 4 Adjustable voltage version only—this is the input to the control loop error amplifier, and is used to set the
output voltage of the device.
OUT 5 Output of the regulator. There are no output capacitor requirements for stability.
DESCRIPTION
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0.5
0.4
0.3
0.2
0.1
0
−
0.1
−
0.2
−
0.3
−
0.4
−
0.5
Change in V
OUT
(%)
0 15 30 45 60 75 90 105 120 135 150
I
OUT
(mA)
Referred to I
OUT
= 10mA
0.20
0.15
0.10
0.05
0
−
0.05
−
0.10
−
0.15
−
0.20
Change in V
OUT
(%)
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
V
IN
−
V
OUT
(V)
+125_C
+25_C
−
40_C
Referred to VIN= V
OUT
+ 0.5V at I
OUT
= 10mA
50
40
30
20
10
0
V
DO
(mV)
0 30 60 90 120 150
I
OUT
(mA)
+125_C
TPS73125DBV
+25_C
−
40_C
50
40
30
20
10
0
V
DO
(mV)
−
50−25 0 25 50 75 100 125
Temperature (_C)
TPS73125DBV
I
OUT
= 150mA
30
25
20
15
10
5
0
Percent of Units (%)
−
1.0
−
0.9
−
0.8
−
0.7
−
0.6
−
0.5
−
0.4
−
0.3
−
0.2
−
0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
V
OUT
Error (%)
I
OUT
= 10mA
18
16
14
12
10
8
6
4
2
0
Percent of Units (%)
−
100
−
90
−
80
−
70
−
60
−
50
−
40
−
30
−
20
−
10
0
10
20
30
40
50
60
70
80
90
100
Worst Case dV
OUT
/dT (ppm/_C)
I
OUT
= 10mA
All Voltage Versions
TPS731xx
SBVS034J – SEPTEMBER 2003 – REVISED MAY 2007
For all voltage versions at TJ= +25 ° C, V
LOAD REGULATION LINE REGULATION
Figure 3. Figure 4.
DROPOUT VOLTAGE vs OUTPUT CURRENT DROPOUT VOLTAGE vs TEMPERATURE
TYPICAL CHARACTERISTICS
= V
IN
OUT(nom)
+ 0.5V, I
noted.
OUT
= 10mA, V
= 1.7V, and C
EN
OUT
= 0.1 µ F, unless otherwise
OUTPUT VOLTAGE ACCURACY HISTOGRAM OUTPUT VOLTAGE DRIFT HISTOGRAM
6
Figure 5. Figure 6.
Figure 7. Figure 8.
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700
600
500
400
300
200
100
0
I
GND
(
µ
A)
0 30 60 90 120 150
I
OUT
(mA)
VIN= 5.5V
VIN= 4V
VIN= 2V
700
600
500
400
300
200
100
0
I
GND
(
µ
A)
−
50−25 0 25 50 75 100 125
Temperature (_C)
I
OUT
= 150mA
VIN= 5.5V
VIN= 4V
VIN= 2V
1
0.1
0.01
I
GND
(
µ
A)
−
50−25 0 25 50 75 100 125
Temperature (_C)
V
ENABLE
= 0.5V
VIN= VO+ 0.5V
400
350
300
250
200
150
100
50
0
Current Limit (mA)
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
V
OUT
(V)
TPS73133
I
CL
I
SC
500
450
400
350
300
250
200
150
Current Limit (mA)
1.5 2.5 3.0 3.5 4.0 4.5 5.02.0 5.5
VIN(V)
500
450
400
350
300
250
200
150
Current Limit (mA)
−
50
−
25 0 25 50 75 100 125
Temperature (_C)
For all voltage versions at TJ= +25 ° C, V
noted.
GROUND PIN CURRENT vs OUTPUT CURRENT GROUND PIN CURRENT vs TEMPERATURE
Figure 9. Figure 10.
TYPICAL CHARACTERISTICS (continued)
= V
IN
OUT(nom)
+ 0.5V, I
OUT
= 10mA, V
SBVS034J – SEPTEMBER 2003 – REVISED MAY 2007
= 1.7V, and C
EN
OUT
= 0.1 µ F, unless otherwise
TPS731xx
GROUND PIN CURRENT in SHUTDOWN CURRENT LIMIT vs V
vs TEMPERATURE (FOLDBACK)
Figure 11. Figure 12.
CURRENT LIMIT vs V
IN
CURRENT LIMIT vs TEMPERATURE
OUT
Figure 13. Figure 14.
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40
35
30
25
20
15
10
5
0
PSRR(dB)
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
V V- (V)
IN OUT
Frequency=10kHz
C =10 F
V =2.5V
I =100mA
m
OUT
OUT
OUT
10k10
90
80
70
60
50
40
30
20
10
0
RippleRejection(dB)
100 1k 100k 1M 10M
Frequency(Hz)
I =1mA
OUT
C =1 Fm
OUT
I =Any
OUT
C =0 Fm
OUT
V =V +1V
IN OUT
I =1mA
OUT
C =Any
OUT
I =1mA
OUT
C =10 Fm
OUT
I =100mA
OUT
C =Any
OUT
I =100mA
OUT
C =10 Fm
OUT
I =100mA
O
C =1 Fm
O
1
0.1
0.01
e
N
(
µ
V/
√
Hz)
10 100 1k 10k 100k
Frequency (Hz)
C
OUT
= 1µF
C
OUT
= 0µF
C
OUT
= 10µF
I
OUT
= 150mA
1
0.1
0.01
e
N
(
µ
V/
√
Hz)
10 100 1k 10k 100k
Frequency (Hz)
I
OUT
= 150mA
C
OUT
= 1µF
C
OUT
= 0µF
C
OUT
= 10µF
60
50
40
30
20
10
0
V
N
(RMS)
C
OUT
(µF)
0.1 1 10
V
OUT
= 5.0V
V
OUT
= 3.3V
V
OUT
= 1.5V
CNR= 0.01µF
10Hz < Frequency < 100kHz
140
120
100
80
60
40
20
0
V
N
(RMS)
CNR(F)
1p 10p 100p 1n 10n
V
OUT
= 5.0V
V
OUT
= 3.3V
V
OUT
= 1.5V
C
OUT
= 0µF
10Hz < Frequency < 100kHz
TPS731xx
SBVS034J – SEPTEMBER 2003 – REVISED MAY 2007
For all voltage versions at TJ= +25 ° C, V
noted.
TYPICAL CHARACTERISTICS (continued)
= V
IN
OUT(nom)
+ 0.5V, I
OUT
= 10mA, V
= 1.7V, and C
EN
OUT
= 0.1 µ F, unless otherwise
PSRR (RIPPLE REJECTION) vs FREQUENCY PSRR (RIPPLE REJECTION) vs VIN– V
Figure 15. Figure 16.
NOISE SPECTRAL DENSITY NOISE SPECTRAL DENSITY
C
= 0µF C
NR
NR
= 0.01µF
OUT
Figure 17. Figure 18.
RMS NOISE VOLTAGE vs C
8
Figure 19. Figure 20.
OUT
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RMS NOISE VOLTAGE vs C
NR
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10µs/div
40mV/tick
40mV/tick
40mV/tick
25mA/tick
V
IN
= 3.8V C
OUT
= 0µF
C
OUT
= 1µF
C
OUT
= 10µF
10mA
150mA
V
OUT
V
OUT
V
OUT
I
OUT
10µs/div
50mV/div
50mV/div
1V/div
V
OUT
V
OUT
V
IN
I
OUT
= 150mA
5.5V
4.5V
dV
IN
dt
= 0.5V/µs
C
OUT
= 0µF
C
OUT
= 100µF
100µs/div
1V/div
1V/div
RL= 20
Ω
C
OUT
= 10µF
2V
0V
RL= 1kΩ
C
OUT
= 0µF
RL= 20
Ω
C
OUT
= 1µF
V
OUT
V
EN
100µs/div
1V/div
1V/div
RL= 20Ω
C
OUT
= 10µF
2V
0V
RL= 1k
Ω
C
OUT
= 0µF
RL= 20
Ω
C
OUT
= 1µF
V
OUT
V
EN
6
5
4
3
2
1
0
−
1
−
2
Volts
50ms/div
V
IN
V
OUT
10
1
0.1
0.01
I
ENABLE
(nA)
−
50−25 0 25 50 75 100 125
Temperature (_C)
For all voltage versions at TJ= +25 ° C, V
noted.
TYPICAL CHARACTERISTICS (continued)
= V
IN
OUT(nom)
+ 0.5V, I
OUT
= 10mA, V
SBVS034J – SEPTEMBER 2003 – REVISED MAY 2007
= 1.7V, and C
EN
OUT
= 0.1 µ F, unless otherwise
TPS731xx
LOAD TRANSIENT RESPONSE LINE TRANSIENT RESPONSE
TPS73133 TPS73133
Figure 21. Figure 22.
TPS73133 TPS73133
TURN-ON RESPONSE TURN-OFF RESPONSE
POWER UP / POWER DOWN I
Figure 23. Figure 24.
TPS73133
ENABLE
Figure 25. Figure 26.
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vs TEMPERATURE
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60
55
50
45
40
35
30
25
20
V
N
(rms)
CFB(F)
10p 100p 1n 10n
V
OUT
= 2.5V
C
OUT
= 0µF
R1= 39.2k
Ω
10Hz < Frequency < 100kHz
160
140
120
100
80
60
40
20
0
I
FB
(nA)
−
50−25 0 25 50 75 100 125
Temperature (_C)
5µs/div
100mV/div
100mV/div
V
OUT
V
OUT
V
IN
4.5V
3.5V
C
OUT
= 0µF
V
OUT
= 2.5V
CFB= 10nF
C
OUT
= 10µF
25µs/div
50mV/div
50mV/div
V
OUT
V
OUT
I
OUT
150mA
10mA
C
OUT
= 0µF
CFB= 10nF
R1= 39.2k
Ω
C
OUT
= 10µF
TPS731xx
SBVS034J – SEPTEMBER 2003 – REVISED MAY 2007
For all voltage versions at TJ= +25 ° C, V
noted.
TYPICAL CHARACTERISTICS (continued)
= V
IN
OUT(nom)
+ 0.5V, I
OUT
= 10mA, V
= 1.7V, and C
EN
OUT
= 0.1 µ F, unless otherwise
RMS NOISE VOLTAGE vs C
FB
IFBvs TEMPERATURE
Figure 27. Figure 28.
TPS73101 TPS73101
LOAD TRANSIENT, ADJUSTABLE VERSION LINE TRANSIENT, ADJUSTABLE VERSION
TPS73101 TPS73101
10
Figure 29. Figure 30.
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TPS731xx
GNDEN NR
IN OUT
V
IN
V
OUT
Optional input capacitor.
May improve source
impedance, noise, or PSRR.
Optional output capacitor.
May improve load transient,
noise, or PSRR.
Optional bypass
capacitor to reduce
output noise.
VN+ 32mV
RMS
(R
1
) R2)
R
2
+ 32mV
RMS
V
OUT
V
REF
TPS73101
GNDEN FB
IN OUT
V
IN
V
OU
T
V
OUT
= x1.204
(R
1
+ R
2
)
R
2
R
1
C
FB
R
2
Optionalinputcapacitor.
Mayimprovesource
impedance,noise,orPSRR.
Optionaloutputcapacitor.
Mayimproveloadtransient
noise,orPSRR.
Optionalcapacitor
reducesoutputnoise
andimproves
transientresponse.
VN(mV
RMS
) + 27
ǒ
mV
RMS
V
Ǔ
V
OUT
(V)
TPS731xx
SBVS034J – SEPTEMBER 2003 – REVISED MAY 2007
APPLICATION INFORMATION
The TPS731xx belongs to a family of new generation For best accuracy, make the parallel combination of
LDO regulators that use an NMOS pass transistor to R
achieve ultra-low-dropout performance, reverse in addition to the internal 8k Ω resistor, presents the
current blockage, and freedom from output capacitor same impedance to the error amp as the 27k Ω
constraints. These features, combined with low noise bandgap reference output. This impedance helps
and an enable input, make the TPS731xx ideal for compensate for leakages into the error amp
portable applications. This regulator family offers a terminals.
wide selection of fixed output voltage versions and
an adjustable output version. All versions have
thermal and over-current protection, including
foldback current limit.
Figure 31 shows the basic circuit connections for the
fixed voltage models. Figure 32 gives the
connections for the adjustable output version
(TPS73101).
Figure 31. Typical Application Circuit for
Fixed-Voltage Versions
and R
1
approximately euqal to 19k Ω . This 19k Ω ,
2
INPUT AND OUTPUT CAPACITOR REQUIREMENTS
Although an input capacitor is not required for
stability, it is good analog design practice to connect
a 0.1µF to 1µF low ESR capacitor across the input
supply near the regulator. This counteracts reactive
input sources and improves transient response,
noise rejection, and ripple rejection. A higher-value
capacitor may be necessary if large, fast rise-time
load transients are anticipated or the device is
located several inches from the power source.
The TPS731xx does not require an output capacitor
for stability and has maximum phase margin with no
capacitor. It is designed to be stable for all available
types and values of capacitors. In applications where
V
– V
IN
are in parallel, ringing may occur when the product of
C
OUT
includes all parasitic resistances, including capacitor
ESR and board, socket, and solder joint resistance.
In most applications, the sum of capacitor ESR and
trace resistance will meet this requirement.
< 0.5V and multiple low ESR capacitors
OUT
and total ESR drops below 50n Ω F. Total ESR
R
1
using the formula shown in Figure 32 . Sample
resistor values for common output voltages are
shown in Figure 2 .
Figure 32. Typical Application Circuit for
Adjustable-Voltage Version
and R
can be calculated for any output voltage
2
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OUTPUT NOISE
A precision band-gap reference is used to generate
the internal reference voltage, V
the dominant noise source within the TPS731xx and
it generates approximately 32 µ V
100kHz) at the reference output (NR). The regulator
control loop gains up the reference noise with the
same gain as the reference voltage, so that the noise
voltage of the regulator is approximately given by:
Since the value of V
is 1.2V, this relationship
REF
reduces to:
for the case of no C
.
NR
. This reference is
REF
RMS
(10Hz to
(1)
(2)
11
www.ti.com
VN(mV
RMS
) + 8.5
ǒ
mV
RMS
V
Ǔ
V
OUT
(V)
TPS731xx
SBVS034J – SEPTEMBER 2003 – REVISED MAY 2007
An internal 27k Ω resistor in series with the noise
reduction pin (NR) forms a low-pass filter for the
voltage reference when an external noise reduction
capacitor, C
C
= 10nF, the total noise in the 10Hz to 100kHz
NR
, is connected from NR to ground. For
NR
bandwidth is reduced by a factor of ~3.2, giving the
approximate relationship:
for C
= 10nF.
NR
This noise reduction effect is shown as RMS Noise
Voltage vs C
in the Typical Characteristics section.
NR
The TPS73101 adjustable version does not have the
noise-reduction pin available. However, connecting a
feedback capacitor, C
, from the output to the FB
FB
pin reduces output noise and improves load transient
performance.
The TPS731xx uses an internal charge pump to
develop an internal supply voltage sufficient to drive
the gate of the NMOS pass element above V
The charge pump generates ~250µV of switching
noise at ~4MHz; however, charge-pump noise
contribution is negligible at the output of the regulator
for most values of I
and C
OUT
.
OUT
BOARD LAYOUT RECOMMENDATION TO IMPROVE PSRR AND NOISE PERFORMANCE
To improve ac performance such as PSRR, output
noise, and transient response, it is recommended
that the PCB be designed with separate ground
planes for V
and V
IN
, with each ground plane
OUT
connected only at the GND pin of the device. In
addition, the ground connection for the bypass
capacitor should connect directly to the GND pin of
the device.
INTERNAL CURRENT LIMIT
The TPS731xx internal current limit helps protect the
regulator during fault conditions. Foldback current
limit helps to protect the regulator from damage
during output short-circuit conditions by reducing
current limit when V
Figure 11 in the Typical Characteristics section.
drops below 0.5V. See
OUT
SHUTDOWN
The Enable pin is active high and is compatible with
standard TTL-CMOS levels. V
EN
below 0.5V (max)
turns the regulator off and drops the ground pin
current to approximately 10nA. When shutdown
capability is not required, the Enable pin can be
connected to V
. When a pull-up resistor is used,
IN
and operation down to 1.8V is required, use pull-up
(3)
resistor values below 50 k Ω .
DROPOUT VOLTAGE
The TPS731xx uses an NMOS pass transistor to
achieve extremely low dropout. When (V
less than the dropout voltage (V
DO
), the NMOS pass
– V
IN
) is
OUT
device is in its linear region of operation and the
input-to-output resistance is the R
of the NMOS
DS-ON
pass element.
For large step changes in load current, the
TPS731xx requires a larger voltage drop from V
V
to avoid degraded transient response. The
OUT
boundary of this transient dropout region is
.
OUT
approximately twice the dc dropout. Values of V
V
above this line insure normal transient
OUT
to
IN
–
IN
response.
Operating in the transient dropout region can cause
an increase in recovery time. The time required to
recover from a load transient is a function of the
magnitude of the change in load current rate, the
rate of change in load current, and the available
headroom (V
to V
IN
OUT
voltage drop). Under
worst-case conditions [full-scale instantaneous load
change with (V
– V
IN
) close to dc dropout levels],
OUT
the TPS731xx can take a couple of hundred
microseconds to return to the specified regulation
accuracy.
TRANSIENT RESPONSE
The low open-loop output impedance provided by the
NMOS pass element in a voltage follower
configuration allows operation without an output
capacitor for many applications. As with any
regulator, the addition of a capacitor (nominal value
1 µ F) from the output pin to ground will reduce
undershoot magnitude but increase its duration. In
the adjustable version, the addition of a capacitor,
C
, from the output to the adjust pin will also
FB
improve the transient response.
12
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dVńdt +
V
OUT
C
OUT
80kW ø R
LOAD
dVńdt +
V
OUT
C
OUT
80kW ø(R1) R
2
)
ø R
LOAD
PD+ (VIN* V
OUT
) I
OUT
TPS731xx
SBVS034J – SEPTEMBER 2003 – REVISED MAY 2007
The TPS731xx does not have active pull-down when temperature should be limited to +125 ° C maximum.
the output is over-voltage. This allows applications To estimate the margin of safety in a complete
that connect higher voltage sources, such as design (including heatsink), increase the ambient
alternate power supplies, to the output. This also temperature until the thermal protection is triggered;
results in an output overshoot of several percent if use worst-case loads and signal conditions. For good
the load current quickly drops to zero when a reliability, thermal protection should trigger at least
capacitor is connected to the output. The duration of +35 ° C above the maximum expected ambient
overshoot can be reduced by adding a load resistor. condition of your application. This produces a
The overshoot decays at a rate determined by output worst-case junction temperature of +125 ° C at the
capacitor C
resistance. The rate of decay is given by: worst-case load.
(Fixed voltage version) The internal protection circuitry of the TPS731xx has
(Adjustable voltage version)
REVERSE CURRENT
The NMOS pass element of the TPS731xx provides
inherent protection against current flow from the
output of the regulator to the input when the gate of
the pass device is pulled low. To ensure that all
charge is removed from the gate of the pass
element, the enable pin must be driven low before
the input voltage is removed. If this is not done, the
pass element may be left on due to stored charge on
the gate.
After the enable pin is driven low, no bias voltage is
needed on any pin for reverse current blocking. Note
that reverse current is specified as the current
flowing out of the IN pin due to voltage applied on
the OUT pin. There will be additional current flowing
into the OUT pin due to the 80k Ω internal resistor
divider to ground (see Figure 1 and Figure 2 ).
For the TPS73101, reverse current may flow when
V
is more than 1.0V above V
FB
THERMAL PROTECTION
Thermal protection disables the output when the
junction temperature rises to approximately +160 ° C,
allowing the device to cool. When the junction
temperature cools to approximately +140 ° C, the
output circuitry is again enabled. Depending on
power dissipation, thermal resistance, and ambient
temperature, the thermal protection circuit may cycle
on and off. This limits the dissipation of the regulator,
protecting it from damage due to overheating.
Any tendency to activate the thermal protection
circuit indicates excessive power dissipation or an
inadequate heatsink. For reliable operation, junction
and the internal/external load highest expected ambient temperature and
OUT
been designed to protect against overload
(4)
conditions. It was not intended to replace proper
heatsinking. Continuously running the TPS731xx into
thermal shutdown degrades device reliability.
POWER DISSIPATION
(5)
.
IN
The ability to remove heat from the die is different for
each package type, presenting different
considerations in the PCB layout. The PCB area
around the device that is free of other components
moves the heat from the device to the ambient air.
Performance data for JEDEC low- and high-K boards
are shown in the Power Dissipation Ratings table.
Using heavier copper will increase the effectiveness
in removing heat from the device. The addition of
plated through-holes to heat-dissipating layers also
improves the heat-sink effectiveness.
Power dissipation depends on input voltage and load
conditions. Power dissipation (P
product of the output current times the voltage drop
across the output pass element (V
Power dissipation can be minimized by using the
lowest possible input voltage necessary to assure
the required output voltage.
Package Mounting
Solder pad footprint recommendations for the
TPS731xx are presented in Application Bulletin
Solder Pad Recommendations for Surface-Mount
Devices (SBFA015 ), available from the Texas
Instruments web site at www.ti.com .
) is equal to the
D
to V
IN
OUT
):
(6)
Submit Documentation Feedback
13
PACKAGE OPTION ADDENDUM
www.ti.com
PACKAGING INFORMATION
Orderable Device Status
TPS73101DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
TPS73101DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
TPS73101DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS &
TPS73101DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS &
TPS731125DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
TPS731125DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
TPS731125DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS &
TPS731125DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS &
TPS73115DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
TPS73115DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
TPS73115DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS &
TPS73115DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS &
TPS73118DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
TPS73118DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
TPS73118DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS &
TPS73118DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS &
TPS73125DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
TPS73125DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
TPS73125DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS &
TPS73125DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS &
TPS73130DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
TPS73130DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
TPS73130DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS &
TPS73130DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS &
TPS73131DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
(2)
Lead/Ball Finish MSL Peak Temp
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
Call TI Level-1-260C-UNLIM
Call TI Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
17-May-2007
(3)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
TPS73131DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
Lead/Ball Finish MSL Peak Temp
CU NIPDAU Level-1-260C-UNLIM
17-May-2007
(3)
no Sb/Br)
TPS73131DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS73131DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS73132DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS73132DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS73132DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS73132DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS73133DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS73133DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS73133DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS73133DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS73150DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS73150DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS73150DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS73150DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
17-May-2007
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Jun-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
Device Package Pins Site Reel
Diameter
(mm)
TPS73101DBVR DBV 5 NSE 179 8 3.2 3.2 1.4 4 8 NONE
TPS73101DBVT DBV 5 NSE 179 8 3.2 3.2 1.4 4 8 NONE
TPS731125DBVR DBV 5 NSE 179 8 3.2 3.2 1.4 4 8 NONE
TPS731125DBVT DBV 5 NSE 179 8 3.2 3.2 1.4 4 8 NONE
TPS73115DBVR DBV 5 NSE 179 8 3.2 3.2 1.4 4 8 NONE
TPS73115DBVT DBV 5 NSE 179 8 3.2 3.2 1.4 4 8 NONE
TPS73118DBVR DBV 5 NSE 179 8 3.2 3.2 1.4 4 8 NONE
TPS73118DBVT DBV 5 NSE 179 8 3.2 3.2 1.4 4 8 NONE
TPS73125DBVR DBV 5 NSE 179 8 3.2 3.2 1.4 4 8 NONE
TPS73125DBVT DBV 5 NSE 179 8 3.2 3.2 1.4 4 8 NONE
TPS73130DBVR DBV 5 NSE 179 8 3.2 3.2 1.4 4 8 NONE
TPS73130DBVT DBV 5 NSE 179 8 3.2 3.2 1.4 4 8 NONE
TPS73131DBVR DBV 5 NSE 179 8 3.2 3.2 1.4 4 8 NONE
TPS73131DBVT DBV 5 NSE 179 8 3.2 3.2 1.4 4 8 NONE
TPS73132DBVR DBV 5 NSE 179 8 3.2 3.2 1.4 4 8 NONE
TPS73132DBVT DBV 5 NSE 179 8 3.2 3.2 1.4 4 8 NONE
TPS73133DBVR DBV 5 NSE 179 8 3.2 3.2 1.4 4 8 NONE
TPS73133DBVT DBV 5 NSE 179 8 3.2 3.2 1.4 4 8 NONE
TPS73150DBVR DBV 5 NSE 179 8 3.2 3.2 1.4 4 8 NONE
TPS73150DBVT DBV 5 NSE 179 8 3.2 3.2 1.4 4 8 NONE
Reel
Width
(mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm)W(mm)
6-Jun-2007
Pin1
Quadrant
TAPE AND REEL BOX INFORMATION
Device Package Pins Site Length (mm) Width (mm) Height (mm)
TPS73101DBVR DBV 5 NSE 195.0 200.0 45.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
Device Package Pins Site Length (mm) Width (mm) Height (mm)
TPS73101DBVT DBV 5 NSE 195.0 200.0 45.0
TPS731125DBVR DBV 5 NSE 195.0 200.0 45.0
TPS731125DBVT DBV 5 NSE 195.0 200.0 45.0
TPS73115DBVR DBV 5 NSE 195.0 200.0 45.0
TPS73115DBVT DBV 5 NSE 195.0 200.0 45.0
TPS73118DBVR DBV 5 NSE 195.0 200.0 45.0
TPS73118DBVT DBV 5 NSE 195.0 200.0 45.0
TPS73125DBVR DBV 5 NSE 195.0 200.0 45.0
TPS73125DBVT DBV 5 NSE 195.0 200.0 45.0
TPS73130DBVR DBV 5 NSE 195.0 200.0 45.0
TPS73130DBVT DBV 5 NSE 195.0 200.0 45.0
TPS73131DBVR DBV 5 NSE 195.0 200.0 45.0
TPS73131DBVT DBV 5 NSE 195.0 200.0 45.0
TPS73132DBVR DBV 5 NSE 195.0 200.0 45.0
TPS73132DBVT DBV 5 NSE 195.0 200.0 45.0
TPS73133DBVR DBV 5 NSE 195.0 200.0 45.0
TPS73133DBVT DBV 5 NSE 195.0 200.0 45.0
TPS73150DBVR DBV 5 NSE 195.0 200.0 45.0
TPS73150DBVT DBV 5 NSE 195.0 200.0 45.0
6-Jun-2007
Pack Materials-Page 3
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Logic logic.ti.com Military www.ti.com/military
Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork
Microcontrollers microcontroller.ti.com Security www.ti.com/security
RFID www.ti-rfid.com Telephony www.ti.com/telephony
Low Power www.ti.com/lpw Video & Imaging www.ti.com/video
Wireless
Wireless www.ti.com/wireless
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