TEXAS INSTRUMENTS TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q Technical data

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CHIP FORM

40°C to

125 C

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q

LOW-DROPOUT VOLTAGE REGULATORS

WITH INTEGRATED DELAYED RESET FUNCTION

SLVS124F – JUNE 1995 – REVISED JANUARY 1999

Available in 2.5-V, 3-V, 3.3-V, 4.85-V, and 5-V Fixed-Output and Adjustable Versions

Integrated Precision Supply-Voltage Supervisor Monitoring Regulator Output Voltage

Active-Low Reset Signal with 200-ms Pulse

D OR P PACKAGE

(TOP VIEW)

GND

IN IN

1 2 3 4

RESET

SENSE†/FB

OUT

6 5

OUT

Width

Very Low Dropout Voltage ...Maximum of 35 mV at IO = 100 mA (TPS7350)

Low Quiescent Current – Independent of Load . . . 340 µA Typ

Extremely Low Sleep-State Current,

0.5 µA Max

2% Tolerance Over Full Range of Load, Line, and Temperature for Fixed-Output Versions

Output Current Range of 0 mA to 500 mA

TSSOP Package Option Offers Reduced Component Height For Critical Applications

description

The TPS73xx devices are members of a family of micropower low-dropout (LDO) voltage regulators.

NC – No internal connection †

SENSE – Fixed voltage options only (TPS7325, TPS7330, TPS7333, TPS7348, and TPS7350)

‡

FB – Adjustable version only (TPS7301)

PW PACKAGE

GND GND GND

NC NC EN NC

IN IN IN

(TOP VIEW)

RESET NC NC

‡

FB NC SENSE OUT OUT NC NC

†

They are di ffere ntiate d from the TP S71xx an d TPS72xx LDOs by their integrated delayed microprocessor-reset function. If the precision delayed reset is not required, the TPS71xx and TPS72xx should be considered.

‡

AVAILABLE OPTIONS

OUTPUT VOLTAGE

–

125°C

2.425 2.5 2.575 2.23 2.32 2.39 TPS7325QD TPS7325QP TPS7325QPW TPS7325Y

The D and PW packages are available taped and reeled. Add an R suffix to device type (e.g., TPS7350QDR). The TPS7301Q is programmable using an external resistor divider (see application information). The chip form is tested at 25°C.

The TPS7325 has a tolerance of ±3% over the full temperature range.

The TPS71xx and the TPS72xx are 500-mA and 250-mA output regulators respectively, of fering performance similar to that of the TPS73xx but without the delayed-reset function. The TPS72xx devices are further differentiated by availability in 8-pin thin-shrink small-outline packages (TSSOP) for applications requiring minimum package size.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

(V)

MIN TYP MAX MIN TYP MAX

4.9 5 5.1 4.55 4.65 4.75 TPS7350QD TPS7350QP TPS7350QPW TPS7350Y

4.75 4.85 4.95 4.5 4.6 4.7 TPS7348QD TPS7348QP TPS7348QPW TPS7348Y

3.23 3.3 3.37 2.868 2.934 3 TPS7333QD TPS7333QP TPS7333QPW TPS7333Y

2.94 3 3.06 2.58 2.64 2.7 TPS7330QD TPS7330QP TPS7330QPW TPS7330Y

Adjustable

1.2 V to 9.75 V

NEGATIVE-GOING RESET

THRESHOLD VOLTAGE (V)

SMALL

OUTLINE

(D)

1.101 1.123 1.145 TPS7301QD TPS7301QP TPS7301QPW TPS7301Y

PACKAGED DEVICES

PLASTIC DIP

(P)

TSSOP

(PW)

(Y)

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION

SLVS124F – JUNE 1995 – REVISED JANUARY 1999

description (continued)

The RESET output of the TPS73xx initiates a reset in microcomputer and microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS73xx monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage.

If that occurs, the RESET output (open-drain NMOS) turns on, taking the RESET signal low . RESET stays low for the duration of the undervoltage condition. Once the undervoltage condition ceases, a 200-ms (typ) time-out begins. At the completion of the 200-ms delay, RESET

An order of magnitude reduction in dropout voltage and quiescent current over conventional LDO performance is achieved by replacing the typical pnp pass transistor with a PMOS device.

Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (maximum of 35 mV at an output current of 100 mA for the TPS7350) and is directly proportional to the output current (see Figure 1). Additionally , since the PMOS pass element is a voltage-driven device, the quiescent current is low and remains constant, independent of output loading (typically 340 µA over the full range of output current, 0 mA to 500 mA). These two key specifications yield a significant improvement in operating life for battery-powered systems.

The LDO family also features a sleep mode; applying a logic high signal to EN (enable) shuts down the regulator, reducing the quiescent current to 0.5 µA maximum at TJ = 25°C.

The TPS73xx is offered in 2.5-V , 3-V , 3.3-V , 4.85-V, and 5-V fixed-voltage versions and in an adjustable version (programmable over the range of 1.2 V to 9.75 V). Output voltage tolerance is specified as a maximum of 2% over line, load, and temperature ranges (3% for the 2.5 V and the adjustable version). The TPS73xx family is available in PDIP (8 pin), SO (8 pin) and TSSOP (20 pin) packages. The TSSOP has a maximum height of

1.2 mm.

goes high.

0.3 TA = 25°C

0.25

0.2

0.15

Dropout Voltage – V

0.1

0.05

0 50 100 150 200 250 300

IO – Output Current – mA

TPS7325

TPS7330

TPS7333

TPS7348

TPS7350

350 400 450 500

Figure 1. Dropout Voltage Versus Output Current

RESET SENSE

OUT OUT

†

20 15 14 13

321

To System Reset

250 kΩ

10 µF

CSR = 1 Ω

‡

TPS73xxPW

IN IN

GND

0.1 µF

†

TPS7325, TPS7330, TPS7333, TPS7348, TPS7350 (fixed-voltage options)

‡

Capacitor selection is nontrivial. See application information section for details.

Figure 2. Typical Application Configuration

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q

LOW-DROPOUT VOLTAGE REGULATORS

WITH INTEGRATED DELAYED RESET FUNCTION

SLVS124F – JUNE 1995 – REVISED JANUARY 1999

TPS73xxY chip information

These chips, when properly assembled, display characteristics similar to those of the TPS73xxQ. Thermal compression or ultrasonic bonding may be used on the doped aluminum bonding pads. Chips may be mounted with conductive epoxy or a gold-silicon preform.

BONDING PAD ASSIGNMENTS

(6)

(7)

(2)

(1)

functional block diagram

(5)

(4)

(3)

(5)

(3)

(2)

CHIP THICKNESS: 15 TYPICAL BONDING PADS: 4 × 4 MINIMUM TJmax = 150°C TOLERANCES ARE ±10%. ALL DIMENSIONS ARE IN MILS.

†

SENSE – Fixed voltage options only (TPS7325, TPS7330, TPS7333, TPS7348, and TPS7350)

‡

FB – Adjustable version only (TPS7301)

NOTE A. For most applications, OUT and SENSE should

be tied together as close as possible to the device; for other implementations, refer to SENSE-pin connection discussion in the applications information section of this data sheet.

TPS73xx

(1)

GND

(6) (4) (7)

SENSE

‡

FB OUT RESET

†

ref

For most applications, SENSE should be externally connected to OUT as close as possible to the device. For other implementations, refer to SENSE-pin connection discussion in applications information section.

Switch positions are shown with EN

¶¶

_ +

+ _

GND

low (active).

Delayed

Reset

RESET

OUT

SENSE§/FB

RESISTOR DIVIDER OPTIONS

DEVICE

TPS7301 TPS7325 TPS7330 TPS7333 TPS7348 TPS7350

NOTE A. Resistors are nominal values only.

0 260 358 420 726 756

COMPONENT COUNT

MOS transistors Bilpolar transistors Diodes Capacitors Resistors

∞

233 233 233 233 233

UNITR1 R2

Ω

kΩ kΩ kΩ kΩ kΩ

464

4 17 76

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION

SLVS124F – JUNE 1995 – REVISED JANUARY 1999

timing diagram

†

res

Threshold

Voltage

RESET Output

Output

Undefined

†

is the minimum input voltage for a valid RESET . The symbol V

res

for semiconductor symbology.

IT+

200 ms Delay

IT–

IT+

IT–

200 ms Delay

is not currently listed within EIA or JEDEC standards

res

Output Undefined

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Input voltage range

Output current, IO 2 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total power dissipation See Dissipation Rating Tables 1 and 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating virtual junction temperature range, TJ –55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

‡

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

All voltage values are with respect to network terminal ground.

, VI, RESET, SENSE, EN –0.3 V to 11 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

‡

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q

LOW-DROPOUT VOLTAGE REGULATORS

WITH INTEGRATED DELAYED RESET FUNCTION

SLVS124F – JUNE 1995 – REVISED JANUARY 1999

DISSIPATION RATING TABLE 1 – FREE-AIR TEMPERATURE (SEE FIGURE 3)

≤ 25°C DERATING FACTOR T

POWER RATING ABOVE TA = 25°CAPOWER RATINGAPOWER RATING

D 725 mW 5.8 mW/°C 464 mW 145 mW P 1 175 mW 9.4 mW/°C 752 mW 235 mW

†

D 2188 mW 9.4 mW/°C 1765 mW 1248 mW P 2738 mW 21.9 mW/°C 1752 mW 548 mW

†

Refer to Thermal Information section for detailed power dissipation considerations when using the TSSOP package.

700 mW 5.6 mW/°C 448 mW 140 mW

DISSIPATION RA TING TABLE 2 – CASE TEMPERATURE (SEE FIGURE 4)

≤ 25°C DERATING FACTOR T

POWER RATING ABOVE TC = 25°CCPOWER RATINGCPOWER RATING

4025 mW 32.2 mW/°C 2576 mW 805 mW

= 70°C T

= 125°C

MAXIMUM CONTINUOUS DISSIPATION

FREE-AIR TEMPERATURE

1400

1200

1000

800

600

400

200

– Maximum Continuous Dissipation – mW

PW Package R

θJA

25 50 75 100

P Package R

= 106°C/W

θJA

= 178°C/W

TA – Free-Air Temperature – °C

Figure 3

D Package R

= 172°C/W

θJA

125 150

MAXIMUM CONTINUOUS DISSIPATION

CASE TEMPERATURE

4800 4400

4000 3600 3200 2800 2400 2000 1600 1200

800

– Maximum Continuous Dissipation – mW

400

25 50 75 100

PW Package R

= 37°C/W

θJC

P Package R

θJC

D Package R

= 57°C/W

θJC

TC – Case Temperature – °C

Figure 4

= 46°C/W

125 150

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q

Input voltage, V

†

LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION

SLVS124F – JUNE 1995 – REVISED JANUARY 1999

recommended operating conditions

MIN MAX UNIT

TPS7301Q 2.47 10 TPS7325Q 3.1 10

High-level input voltage at EN, V Low-level input voltage at EN, V Output current range, I Operating virtual junction temperature range, T

†

Minimum input voltage defined in the recommended operating conditions is the maximum specified output voltage plus dropout voltage, VDO, at the maximum specified load range. Since dropout voltage is a function of output current, the usable range can be extended for lighter loads. To calculate the minimum input voltage for the maximum load current used in a given application, use the following equation:

Because the TPS7301 is programmable, r VDO from r the recommended input voltage range for the TPS7301.

I(min)

DS(on)

)

O(max)

is given in Note 2 in the TPS7301 electrical characteristics table. The minimum value of 2.97 V is the absolute lower limit for

DO(max load)

TPS7330Q 3.5 10 V TPS7333Q 3.77 10 TPS7348Q 5.2 10 TPS7350Q 5.33 10

should be used to calculate VDO before applying the above equation. The equation for calculating

DS(on)

–40 125 °C

2 V

0.5 V

0 500 mA

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Ground current (active mode)

EN ≤ 0.5 V,

Input current (standby mode)

2.7 V ≤ V

Output current limit

2.7 V ≤ V

≤ 10 V

RESET leak

RESET

EN logic high (standb

)

40°C to 125°C

EN logic l

)

2.7 V ≤ V

≤ 10 V

EN i

0 V ≤ V

≤ 10 V

Minimum V

for active pass element

Mini

lid RESET

300 µA

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q

LOW-DROPOUT VOLTAGE REGULATORS

WITH INTEGRATED DELAYED RESET FUNCTION

SLVS124F – JUNE 1995 – REVISED JANUARY 1999

electrical characteristics at IO = 10 mA, EN = 0 V, Co = 4.7 µF (CSR‡ = 1 Ω), SENSE/FB shorted to OUT (unless otherwise noted)

= 10

= V

+ 1 V

+ 1

≤ 10

= 10

25°C 340 400

–40°C to 125°C 550

25°C 0.01 0.5

–40°C to 125°C 2

25°C 1.2 2

–40°C to 125°C 2

25°C 0.01 0.5

–40°C to 125°C 1

25°C 0.02 0.5

–40°C to 125°C 0.5

–

25°C 0.5

–40°C to 125°C 0.5

25°C –0.5 0.001 0.5

–40°C to 125°C –0.5 0.5

25°C 2.05 2.5

–40°C to 125°C 2.5

25°C 1 1.5

–40°C to 125°C 1.9

MIN TYP MAX

2.7

UNIT

PARAMETER

EN ≤ 0.5 V, V 0 mA ≤ IO ≤ 500 mA

Pass-element leakage current in standby mode

age curren

Output voltage temperature coefficient –40°C to 125°C 61 75 ppm/°C Thermal shutdown junction temperature 165 °C

y mode

ow (active mode

EN hysteresis voltage 25°C 50 mV

nput curren

mum

‡

CSR (compensation series resistance) refers to the total series resistance, including the equivalent series resistance (ESR) of the capacitor, any series resistance added externally, and PWB trace resistance to Co.

Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.

or va

2.5 V ≤ VI ≤ 6 V 6 V ≤ VI ≤ 10 V

TEST CONDITIONS

= 0 V,

ormal operation,V at

O(RESET)

= –

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q

50 µA ≤ I

150 mA

2.4 V

150 mA ≤ I

≤ 500 mA

Ω

50 µA ≤ I

500 mA

Input regulation

Output regulation

µ ,

50 µA

Ripple rejection

120 H

RESET

400 µA

FB input current

LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION

SLVS124F – JUNE 1995 – REVISED JANUARY 1999

TPS7301Q electrical characteristics at IO = 10 mA, V

= 3.5 V , EN = 0 V, Co = 4.7 µF (CSR† = 1 Ω), FB

shorted to OUT at device leads (unless otherwise noted)

PARAMETER

Reference voltage (measured at FB)

Reference voltage temperature coefficient

Pass-element series resistance (See Note 2)

Output noise-spectral density f = 120 Hz 25°C 2

Output noise voltage 10 Hz ≤ f ≤ 100 kHz

RESET trip-threshold voltage RESET hysteresis voltage

output low voltage

†

CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to Co.

‡

Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.

Output voltage programmed to 2.5 V with closed-loop configuration (see application information).

NOTES: 1. When VI < 2.9 V and IO > 150 mA simultaneously, pass element r

dropout voltage prevents the regulator from maintaining the specified tolerance range.

2. To calculate dropout voltage, use equation: VDO = IO r

DS(on)

5.9 V , which corresponds to dropout conditions for programmed output voltages of 2.5 V, 3 V, 4 V, and 6 V respectively . For other programmed values, refer to Figure 33.

is a function of both output current and input voltage. This parametric table lists r

2.5 V ≤ VI ≤ 10 V, See Note 1

= 2.4 V,

= 2.9 V,

VI = 3.9 V, 50 µA ≤ IO ≤ 500 mA 25 °C 0.32 VI = 5.9 V, 50 µA ≤ IO ≤ 500 mA 25 °C 0.23

= 2.5 V to 10 V, 50 µA ≤ I

See Note 1

2.5 V ≤ V See Note 1

O(FB)

Measured at V

= 2.13 V,

TEST CONDITIONS

5 mA ≤ IO ≤ 500 mA,

≤ 10 V, I

I See Note 1

Co = 4.7 µF 25°C 95 Co = 10 µF 25°C 89 Co = 100 µF 25°C 74

decreasing –40°C to 125°C 1.101 1.145 V

O(FB)

O(RESET)

‡

≤

≤ 500 mA,

= 5 mA to 500 mA,

= 50 µA to 500 mA,

= 500 mA,

DS(on)

⋅ r

DS(on)

25°C 1.182 V

–40°C to 125°C 1.147 1.217 V

–40°C to 125°C 61 75 ppm/°C

25°C 0.7 1

–40°C to 125°C 1

25°C 0.83 1.3

–40°C to 125°C 1.3

25°C 0.52 0.85

–40°C to 125°C 0.85

25°C 3 18

–40°C to 125°C 25

25°C 5 14

–40°C to 125°C 25

25°C 7 22

–40°C to 125°C 54

25°C 48 59

–40°C to 125°C 44

25°C 45 54

–40°C to 125°C 44

25°C 12 mV 25°C 0.1 0.4

–40°C to 125°C 0.4

25°C –10 0.1 10

–40°C to 125°C –20 20

increases (see Figure 33) to a point where the resulting

MIN TYP MAX

for VI = 2.4 V, 2.9 V, 3.9 V, and

DS(on)

UNIT

µV/√Hz

µVrms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Output voltage

100 mA

2.97 V

500 mA

Pass-element series resistance

(

O)O

Ω

Input regulation

3.5 V to 10 V

50 µA ≤ I

≤ 500 mA

5 mA to 500 mA

≤ 10 V

Output regulation

500 mA

50 µA

Ripple rejection

120 H

500 mA

RESET output low voltage

2.1 V

0.8 mA

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q

LOW-DROPOUT VOLTAGE REGULATORS

WITH INTEGRATED DELAYED RESET FUNCTION

SLVS124F – JUNE 1995 – REVISED JANUARY 1999

TPS7325Q electrical characteristics at IO = 10 mA, V

= 3.5 V , EN = 0 V, Co = 10 µF (CSR† = 1 Ω), SENSE

shorted to OUT (unless otherwise noted)

PARAMETER

ropout voltage

Output noise-spectral density f = 120 Hz 25°C 2

Output noise voltage 10 Hz ≤ f ≤ 100 kHz

RESET trip-threshold voltage

†

CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to Co.

‡

Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.

Dropout test and pass-element series resistance test are not production tested. Test method requires SENSE terminal to be disconnected from output voltage.

3.5 V ≤ VI ≤ 10 V, 5 mA ≤ IO ≤ 500 mA –40°C to 125°C 2.425 2.575

= 10 mA,

(2.97 V – V IO = 500 mA

= 50 µA to

VO decreasing –40°C to 125°C 2.23 2.32 2.39 V

TEST CONDITIONS

)/I

, V

,3.5 V ≤

Co = 4.7 µF Co = 10 µF Co = 100 µF

‡

= 2.97

= 2.97 V,

O(RESET)

≤ 10

= –

25°C 2.45 2.5 2.55

25°C 5

–40°C to 125°C 14

25°C 50 80

–40°C to 125°C 150

25°C 270 400

–40°C to 125°C 600

25°C 0.5 0.7

–40°C to 125°C 1.4

25°C 6 20

–40°C to 125°C 25

25°C 20 32

–40°C to 125°C 50

25°C 28 60

–40°C to 125°C 100

25°C 50 53

–40°C to 125°C 49

25°C 49 53

–40°C to 125°C 32

25°C 274 25°C 228 25°C 159

25°C 0.14 0.4

–40°C to 125°C 0.4

MIN TYP MAX

UNIT

µV/√Hz

µVrms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q

Output voltage

100 mA

2.94 V

500 mA

Pass-element series resistance

(

O)O

Ω

Input regulation

4 V to 10 V

50 µA ≤ I

≤ 500 mA

5 mA to 500 mA

≤ 10 V

Output regulation

500 mA

50 µA

Ripple rejection

120 H

500 mA

RESET output low voltage

2.6 V

0.8 mA

LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION

SLVS124F – JUNE 1995 – REVISED JANUARY 1999

TPS7330Q electrical characteristics at IO = 10 mA, V

= 4 V , EN = 0 V , Co = 4.7 µF (CSR† = 1 Ω), SENSE

shorted to OUT (unless otherwise noted)

PARAMETER

ropout voltage

Output noise-spectral density f = 120 Hz 25°C 2

Output noise voltage 10 Hz ≤ f ≤ 100 kHz

RESET trip-threshold voltage

†

CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to Co.

‡

Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.

4 V ≤ VI ≤ 10 V, 5 mA ≤ IO ≤ 500 mA –40°C to 125°C 2.94 3.06

= 10 mA,

(2.94 V – V IO = 500 mA

= 50 µA to

VO decreasing –40°C to 125°C 2.58 2.64 2.7 V

TEST CONDITIONS

)/I

, V

,4 V ≤

Co = 4.7 µF Co = 10 µF Co = 100 µF

‡

= 2.94

= 2.94 V,

≤ 10

O(RESET)

= –

25°C 3

25°C 5.2 7

–40°C to 125°C 10

25°C 52 75

–40°C to 125°C 100

25°C 267 450

–40°C to 125°C 500

25°C 0.5 0.7

–40°C to 125°C 1

25°C 6 23

–40°C to 125°C 29

25°C 20 32

–40°C to 125°C 60

25°C 28 60

–40°C to 125°C 120

25°C 43 53

–40°C to 125°C 40

25°C 39 53

–40°C to 125°C 36

25°C 274 25°C 228 25°C 159

25°C 0.14 0.4

–40°C to 125°C 0.4

MIN TYP MAX

UNIT

µV/√Hz

µVrms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Output voltage

100 mA

3.23 V

500 mA

Pass-element series resistance

(

O)O

Ω

Input regulation

4.3 V to 10 V

50 µA ≤ I

≤ 500 mA

5 mA to 500 mA, 4.3 V ≤ V

≤ 10 V

Output regulation

500 mA, 4.3 V ≤ V

50 µA

Ripple rejection

120 H

500 mA

RESET output low voltage

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q

LOW-DROPOUT VOLTAGE REGULATORS

WITH INTEGRATED DELAYED RESET FUNCTION

SLVS124F – JUNE 1995 – REVISED JANUARY 1999

TPS7333Q electrical characteristics at IO = 10 mA, V

= 4.3 V, EN = 0 V, Co = 4.7 µF (CSR† = 1 Ω),

SENSE shorted to OUT (unless otherwise noted)

PARAMETER

ropout voltage

Output noise-spectral density f = 120 Hz 25°C 2

Output noise voltage 10 Hz ≤ f ≤ 100 kHz

RESET trip-threshold voltage RESET hysteresis voltage

†

CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to Co.

‡

Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.

4.3 V ≤ VI ≤ 10 V, 5 mA ≤ IO ≤ 500 mA –40°C to 125°C 3.23 3.37

= 10 mA,

(3.23 V – V IO = 500 mA

= 50 µA to

VO decreasing –40°C to 125°C 2.868 V

= 2.8 V,

TEST CONDITIONS

)/I

, V

Co = 4.7 µF Co = 10 µF Co = 100 µF

‡

= 3.23

= 3.23 V,

O(RESET)

≤ 10

= –1

25°C 3.3

25°C 4.5 7

–40°C to 125°C 8

25°C 44 60

–40°C to 125°C 80

25°C 235 300

–40°C to 125°C 400

25°C 0.44 0.6

–40°C to 125°C 0.8

25°C 6 23

–40°C to 125°C 29

25°C 21 38

–40°C to 125°C 75

25°C 31 60

–40°C to 125°C 120

25°C 43 51

–40°C to 125°C 40

25°C 39 49

–40°C to 125°C 36

25°C 274 25°C 228 25°C 159

25°C 18 mV 25°C 0.17 0.4

–40°C to 125°C 0.4

MIN TYP MAX

UNIT

µV/√Hz

µVrms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q

Output voltage

100 mA

4.75 V

500 mA

Pass-element series resistance

(

O)O

Ω

Input regulation

5.85 V to 10 V

50 µA ≤ I

≤ 500 mA

5 mA to 500 mA, 5.85 V ≤ V

≤ 10 V

Output regulation

500 mA, 5.85 V ≤ V

50 µA

Ripple rejection

120 H

500 mA

RESET output low voltage

1.2 mA,V

4.12 V

LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION

SLVS124F – JUNE 1995 – REVISED JANUARY 1999

TPS7348Q electrical characteristics at IO = 10 mA, V

= 5.85 V, EN = 0 V, Co = 4.7 µF (CSR† = 1 Ω),

SENSE shorted to OUT (unless otherwise noted)

= 4.75

= 4.75 V,

‡

≤ 10

25°C 4.85

25°C 2.9 6

–40°C to 125°C 8

25°C 28 37

–40°C to 125°C 54

25°C 150 180

–40°C to 125°C 250

25°C 0.28 0.37

–40°C to 125°C 0.52

25°C 9 35

–40°C to 125°C 37

25°C 28 42

–40°C to 125°C 80

25°C 42 65

–40°C to 125°C 130

25°C 42 53

–40°C to 125°C 39

25°C 39 50

–40°C to 125°C 35

25°C 410 25°C 328 25°C 212

25°C 26 mV 25°C 0.2 0.4

–40°C to 125°C 0.4

MIN TYP MAX

UNIT

µVrms

PARAMETER

ropout voltage

Output noise-spectral density f = 120 Hz 25°C 2 µV/√Hz

Output noise voltage 10 Hz ≤ f ≤ 100 kHz

RESET trip-threshold voltage RESET hysteresis voltage

†

CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to Co.

‡

Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.

5.85 V ≤ VI ≤ 10 V, 5 mA ≤ IO ≤ 500 mA –40°C to 125°C 4.75 4.95

= 10 mA,

(4.75 V – V IO = 500 mA

= 50 µA to

VO decreasing –40°C to 125°C 4.5 4.7 V

O(RESET)

TEST CONDITIONS

)/I

, V

Co = 4.7 µF Co = 10 µF Co = 100 µF

= –

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Output voltage

100 mA

4.88 V

500 mA

Pass-element series resistance

(

O)O

Ω

Input regulation

6 V to 10 V

50 µA ≤ I

≤ 500 mA

5 mA to 500 mA

≤ 10 V

Output regulation

500 mA

50 µA

Ripple rejection

120 H

500 mA

RESET output low voltage

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q

LOW-DROPOUT VOLTAGE REGULATORS

WITH INTEGRATED DELAYED RESET FUNCTION

SLVS124F – JUNE 1995 – REVISED JANUARY 1999

TPS7350Q electrical characteristics at IO = 10 mA, V

= 6 V , EN = 0 V , Co = 4.7 µF (CSR† = 1 Ω), SENSE

shorted to OUT (unless otherwise noted)

PARAMETER

ropout voltage

Output noise-spectral density f = 120 Hz 25°C 2

Output noise voltage 10 Hz ≤ f ≤ 100 kHz

RESET trip-threshold voltage RESET hysteresis voltage

†

CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to Co.

‡

Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.

6 V ≤ VI ≤ 10 V, 5 mA ≤ IO ≤ 500 mA –40°C to 125°C 4.9 5.1

= 10 mA,

(4.88 V – V IO = 500 mA

= 50 µA to

VO decreasing –40°C to 125°C 4.55 4.75 V

O(RESET)

TEST CONDITIONS

)/I

, V

,6 V ≤

= –1.2 mA,

‡

= 4.88

= 4.88 V,

≤ 10

Co = 4.7 µF Co = 10 µF Co = 100 µF

= 4.25

25°C 5

25°C 2.9 6

–40°C to 125°C 8

25°C 27 35

–40°C to 125°C 50

25°C 146 170

–40°C to 125°C 230

25°C 0.27 0.35

–40°C to 125°C 0.5

25°C 4 25

–40°C to 125°C 45

25°C 30 45

–40°C to 125°C 86

25°C 45 65

–40°C to 125°C 140

25°C 43 53

–40°C to 125°C 38

25°C 41 51

–40°C to 125°C 36

25°C 430 25°C 345 25°C 220

25°C 28 mV 25°C 0.15 0.4

–40°C to 125°C 0.4

MIN TYP MAX

UNIT

µV/√Hz

µVrms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q

RESET ti

See Figure 5

‡

LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION

SLVS124F – JUNE 1995 – REVISED JANUARY 1999

switching characteristics

TPS7301Q, TPS7333Q

PARAMETER TEST CONDITIONS

me-out delay

25°C 140 200 260

–40°C to 125°C 100 300

electrical characteristics at IO = 10 mA, EN = 0 V, Co = 4.7 µF (CSR† = 1 Ω), TJ = 25°C, SENSE/FB shorted to OUT (unless otherwise noted)

PARAMETER

Ground current (active mode) Input current (standby mode)

Output current limit VO = 0 V, VI = 10 V 1.2 A Pass-element leakage current in standby mode RESET leakage current Thermal shutdown junction temperature 165 °C EN logic low (active mode) EN hysteresis voltage 50 mV EN input current Minimum VI for active pass element 2.05 V Minimum VI for valid RESET

†

‡

Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.

EN ≤ 0.5 V, 0 mA ≤ IO ≤ 500 mA

EN = VI, 2.7 V ≤ VI ≤ 10 V

EN = VI, 2.7 V ≤ VI ≤ 10 V Normal operation, V at RESET = 10 V

2.7 V ≤ VI ≤ 10 V 0.5 V

0 V ≤ VI ≤ 10 V 0.001 µA

O(RESET)

TEST CONDITIONS

VI = VO + 1 V,

= –300 µA 1 V

TPS7348Q, TPS7350Q

MIN TYP MAX

TPS7301Y, TPS7333Y TPS7348Y, TPS7350Y

MIN TYP MAX

340 µA

0.01 µA

0.02 µA

UNIT

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Output regulation

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q

LOW-DROPOUT VOLTAGE REGULATORS

WITH INTEGRATED DELAYED RESET FUNCTION

SLVS124F – JUNE 1995 – REVISED JANUARY 1999

TPS7301Y electrical characteristics at IO = 10 mA, V

= 25°C, FB shorted to OUT at device leads (unless otherwise noted)

PARAMETER

Reference voltage (measured at FB) 1.182 V

VI = 2.4 V, 50 µA ≤ IO ≤ 150 mA 0.7 VI = 2.4 V, 150 mA ≤ IO ≤ 500 mA 0.83

Pass-element series resistance (See Note 2)

Input regulation

Ripple rejection f = 120 Hz

Output noise-spectral density f = 120 Hz 2

Output noise voltage 10 Hz ≤ f ≤ 100 kHz

RESET hysteresis voltage RESET output low voltage FB input current 0.1 nA

†

CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to Co.

‡

Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.

Output voltage programmed to 2.5 V with closed-loop configuration (see application information).

NOTES: 1. When VI < 2.9 V and IO > 150 mA simultaneously, pass element r

dropout voltage prevents the regulator from maintaining the specified tolerance range.

2. To calculate dropout voltage, use equation: VDO = IO r

DS(on)

5.9 V , which corresponds to dropout conditions for programmed output voltages of 2.5 V, 3 V, 4 V, and 6 V respectively . For other programmed values, refer to Figure 33.

is a function of both output current and input voltage. The parametric table lists r

VI = 2.9 V, 50 µA ≤ IO ≤ 500 mA 0.52 VI = 3.9 V, 50 µA ≤ IO ≤ 500 mA 0.32 VI = 5.9 V, 50 µA ≤ IO ≤ 500 mA 0.23 VI = 2.5 V to 10 V,

See Note 1

2.5 V ≤ VI ≤ 10 V, See Note 1

Measured at V VI = 2.13 V, I

⋅ r

= 3.5 V, EN = 0 V, Co = 4.7 µF (CSR† = 1 Ω),

TEST CONDITIONS

50 µA ≤ IO ≤ 500 mA,

IO = 5 mA to 500 mA,

IO = 50 µA to 500 mA,

IO = 50 µA 59 IO = 500 mA,

See Note 1

Co = 4.7 µF 95 Co = 10 µF 89 Co = 100 µF 74

O(FB)

O(RESET)

increases (see Figure 33) to a point where the resulting

DS(on)

‡

= 400 µA 0.1 V

MIN TYP MAX

3 mV

5 mV

7 mV

12 mV

for VI = 2.4 V, 2.9 V, 3.9 V, and

DS(on)

UNIT

Ω

µV/√Hz

µVrms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q

Output regulation

Ripple rejection

120 H

LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION

SLVS124F – JUNE 1995 – REVISED JANUARY 1999

TPS7325Y electrical characteristics at IO = 10 mA, V

= 25°C, SENSE shorted to OUT (unless otherwise noted)

PARAMETER

Output voltage 2.5 V

IO = 10 mA, VI = 2.97 V 5

Dropout voltage

Pass-element series resistance Input regulation VI = 3.5 V to 10 V, 50 µA ≤ IO ≤ 500 mA 6 mV

Output noise-spectral density f = 120 Hz 2

Output noise voltage 10 Hz ≤ f ≤ 100 kHz

RESET output low voltage

†

CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to Co.

‡

Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.

Dropout test and pass-element series resistance test are not production tested. Test method requires SENSE terminal to be disconnected from output voltage.

IO = 100 mA, VI = 2.97 V 50 IO = 500 mA, VI = 2.97 V 270 (2.97 V – VO)/IO,

IO = 500 mA

IO = 5 mA to 500 mA, 3.5 V ≤ VI ≤ 10 V 20 mV IO = 50 µA to 500 mA, 3.5 V ≤ VI ≤ 10 V 28 mV

VI = 2.1 V, I

= 3.5 V, EN = 0 V, Co = 10 µF (CSR† = 1 Ω),

TEST CONDITIONS

VI = 2.97 V,

IO = 50 µA 53 IO = 500 mA 53

Co = 4.7 µF Co = 10 µF Co = 100 µF

O(RESET)

‡

= –0.8 mA 0.14 V

MIN TYP MAX

0.5 Ω

274 228 159

UNIT

µV/√Hz

µVrms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Output regulation

Ripple rejection

120 H

Output regulation

Ripple rejection

120 H

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q

LOW-DROPOUT VOLTAGE REGULATORS

WITH INTEGRATED DELAYED RESET FUNCTION

SLVS124F – JUNE 1995 – REVISED JANUARY 1999

TPS7330Y electrical characteristics at IO = 10 mA, V

= 25°C, SENSE shorted to OUT (unless otherwise noted)

PARAMETER

Output voltage 3 V

IO = 10 mA, VI = 2.94 V 5.2

Dropout voltage

Pass-element series resistance Input regulation VI = 4 V to 10 V, 50 µA ≤ IO ≤ 500 mA 6 mV

Output noise-spectral density f = 120 Hz 2

Output noise voltage 10 Hz ≤ f ≤ 100 kHz

RESET output low voltage

†

CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to Co.

‡

Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.

IO = 100 mA, VI = 2.94 V 52 IO = 500 mA, VI = 2.94 V 267 (2.94 V – VO)/IO,

IO = 500 mA

IO = 5 mA to 500 mA, 4 V ≤ VI ≤ 10 V 20 mV IO = 50 µA to 500 mA, 4 V ≤ VI ≤ 10 V 28 mV

VI = 2.6 V, I

= 4 V, EN = 0 V, Co = 4.7 µF (CSR† = 1 Ω),

TEST CONDITIONS

VI = 2.94 V,

IO = 50 µA 53 IO = 500 mA 53

Co = 4.7 µF Co = 10 µF Co = 100 µF

O(RESET)

‡

= –0.8 mA 0.14 V

MIN TYP MAX

0.5 Ω

274 228 159

UNIT

µV/√Hz

µVrms

TPS7333Y electrical characteristics at IO = 10 mA, V

= 25°C, SENSE shorted to OUT (unless otherwise noted)

PARAMETER

Output voltage 3.3 V

IO = 10 mA, VI = 3.23 V 4.5

Dropout voltage

Pass-element series resistance Input regulation VI = 4.3 V to 10 V, 50 µA ≤ IO ≤ 500 mA 6 mV

Output noise-spectral density f = 120 Hz 2

Output noise voltage 10 Hz ≤ f ≤ 100 kHz

RESET hysteresis voltage RESET output low voltage

†

CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to Co.

‡

Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.

IO = 100 mA, VI = 3.23 V 44 IO = 500 mA, VI = 3.23 V 235 (3.23 V – VO)/IO,

IO = 500 mA

IO = 5 mA to 500 mA, 4.3 V ≤ VI ≤ 10 V 21 mV IO = 50 µA to 500 mA, 4.3 V ≤ VI ≤ 10 V 31 mV

VI = 2.8 V, I

= 4.3 V, EN = 0 V, C

TEST CONDITIONS

VI = 3.23 V,

IO = 50 µA 51 IO = 500 mA 49

Co = 4.7 µF Co = 10 µF Co = 100 µF

O(RESET)

= 4.7 µF (CSR† = 1 Ω),

‡

= –1 mA 0.17 V

MIN TYP MAX

0.44 Ω

274 228 159

18 mV

UNIT

µV/√Hz

µVrms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q

Output regulation

Ripple rejection

120 H

LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION

SLVS124F – JUNE 1995 – REVISED JANUARY 1999

TPS7348Y electrical characteristics at IO = 10 mA, V

= 25°C, SENSE shorted to OUT (unless otherwise noted)

PARAMETER

Output voltage 4.85 V

IO = 10 mA, VI = 4.75 V 2.9

Dropout voltage

Pass-element series resistance Input regulation VI = 5.85 V to 10 V, 50 µA ≤ IO ≤ 500 mA 9 mV

Output noise-spectral density f = 120 Hz 2 µV/√Hz

Output noise voltage 10 Hz ≤ f ≤ 100 kHz

RESET hysteresis voltage RESET output low voltage

†

CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to Co.

‡

Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.

IO = 100 mA, VI = 4.75 V 28 IO = 500 mA, VI = 4.75 V 150 (4.75 V – VO)/IO,

IO = 500 mA

IO = 5 mA to 500 mA, 5.85 V ≤ VI ≤ 10 V 28 mV IO = 50 µA to 500 mA, 5.85 V ≤ VI ≤ 10 V 42 mV

O(RESET)

= 5.85 V, EN = 0 V, Co = 4.7 µF (CSR† = 1 Ω),

TEST CONDITIONS

= –1.2 mA, VI = 4.12 V 0.2 V

‡

VI = 4.75 V,

IO = 50 µA 53 IO = 500 mA 50

Co = 4.7 µF Co = 10 µF Co = 100 µF

MIN TYP MAX

0.28 Ω

410 328 212

26 mV

UNIT

µVrms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Output regulation

Ripple rejection

120 H

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q

LOW-DROPOUT VOLTAGE REGULATORS

WITH INTEGRATED DELAYED RESET FUNCTION

SLVS124F – JUNE 1995 – REVISED JANUARY 1999

TPS7350Y electrical characteristics at IO = 10 mA, V

= 25°C, SENSE shorted to OUT (unless otherwise noted)

PARAMETER

Output voltage 5 V

IO = 10 mA, VI = 4.88 V 2.9 6

Dropout voltage

Pass-element series resistance Input regulation VI = 6 V to 10 V, 50 µA ≤ IO ≤ 500 mA 4 25 mV

Output noise-spectral density f = 120 Hz 2

Output noise voltage 10 Hz ≤ f ≤ 100 kHz

RESET hysteresis voltage RESET output low voltage

†

CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to Co.

‡

Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.

IO = 100 mA, VI = 4.88 V 27 35 IO = 500 mA, VI = 4.88 V 146 170 (4.88 V – VO)/IO,

IO = 500 mA

IO = 5 mA to 500 mA, 6 V ≤ VI ≤ 10 V 28 75 mV IO = 50 µA to 500 mA, 6 V ≤ VI ≤ 10 V 41 mV

O(RESET)

= 6 V, EN = 0 V, Co = 4.7 µF (CSR† = 1 Ω),

TEST CONDITIONS

= –1.2 mA, VI = 4.25 V 0.15 0.4 V

‡

VI = 4.88 V,

IO = 50 µA 53 IO = 500 mA 51

Co = 4.7 µF Co = 10 µF Co = 100 µF

MIN TYP MAX

0.27 0.35 Ω

430 345 220

28 mV

UNIT

µV/√Hz

µVrms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION

SLVS124F – JUNE 1995 – REVISED JANUARY 1999

PARAMETER MEASUREMENT INFORMATION

IT+

0.1 µF

RESET

SENSE

OUT

GND

TEST CIRCUIT

Reset

10 µF

CSR

RESET

Timeout Delay

VOLTAGE WAVEFORMS

Figure 5. Test Circuit and Voltage Waveforms

CSR

To Load

†

cer

†

Ceramic capacitor

OUT

SENSE

GND

Figure 6. Test Circuit for Typical Regions of Stability (Refer to Figures 29 through 32)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IQQuiescent current

TPS7325

VOOutput voltage

Load transient response

∆V

DS(on)

IT–

OL(RESET)

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q

LOW-DROPOUT VOLTAGE REGULATORS

WITH INTEGRATED DELAYED RESET FUNCTION

SLVS124F – JUNE 1995 – REVISED JANUARY 1999

TYPICAL CHARACTERISTICS

Table of Graphs

vs Output current 7 vs Input voltage 8

Quiescent current TPS7348 vs Free-air temperature 9

vs Input voltage 10

vs Free-air temperature 11 Dropout voltage vs Output current 12 Change in dropout voltage vs Free-air temperature 13 Dropout voltage TPS7301 vs Output current 14 Change in output voltage vs Free-air temperature 15 Output voltage vs Input voltage 16 Output voltage TPS7325 vs Input voltage 17 Line regulation 18

TPS7301 vs Output current 19 TPS7325 vs Output current 20

Output voltage response from enable (EN) 25

Ripple rejection vs Frequency 32 Output spectral noise density vs Frequency 33

Compensation series resistance (CSR)

Pass-element resistance vs Input voltage 38 Minimum input voltage for valid RESET vs Free-air temperature 39 Negative-going reset threshold vs Free-air temperature 40 RESET output current vs Input voltage 41 Reset time delay vs Free-air temperature 42 Distribution for reset delay 43

TPS7330 vs Output current 21 TPS7333 vs Output current 22 TPS7348 vs Output current 23 TPS7350 vs Output current 24

TPS7301 or TPS7333 26 TPS7325 27 TPS7348 or TPS7350 28 TPS7301 29 TPS7333 30 TPS7348 or TPS7350 31

= 4.7 µ

= 10 µ

vs Output current 34

vs Added ceramic capacitance 35

vs Output current 36

vs Added ceramic capacitance 37

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION

SLVS124F – JUNE 1995 – REVISED JANUARY 1999

TYPICAL CHARACTERISTICS

450

TA = 25°C

425

Aµ

400

375

350

325

– Quiescent Current –

TPS7333, VI = 4.3 V

300

275

TPS7325, VI = 3.5 V

0 50 100 150 200 250

QUIESCENT CURRENT

OUTPUT CURRENT

TPS73xx, VI = 10 V

TPS7350, VI = 6 V

TPS7348, VI = 5.85 V

TPS7330, VI = 4 V

IO – Output Current – mA

Figure 7

QUIESCENT CURRENT

INPUT VOLTAGE

500

TA = 25°C IO = 500 mA

450 400

Aµ

350

300 250

200

– Quiescent Current –

150

100

0123456

TPS7333

VI – Input Voltage – V

Figure 8

TPS7348

TPS7350

TPS7301 With V Programmed to 2.5 V

78910

TPS7348

QUIESCENT CURRENT

FREE-AIR TEMPERATURE

500

VI = 5.85 V IO = 500 mA

450

Aµ

400

350

300

– Quiescent Current –

250

200

–50 –25 0 25 50 75 100 125

TA – Free-Air Temperature – °C

Figure 9

TPS7325

QUIESCENT CURRENT

INPUT VOLTAGE

500

450

Aµ

400

350

300

– Quiescent Current –

250

200

3 45678910

TA = 125°C

TA = 85°C

TA = 25°C

TA = 0°C

TA = –40°C

VI – Input Voltage – V

Figure 10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q

LOW-DROPOUT VOLTAGE REGULATORS

WITH INTEGRATED DELAYED RESET FUNCTION

SLVS124F – JUNE 1995 – REVISED JANUARY 1999

TYPICAL CHARACTERISTICS

TPS7325

QUIESCENT CURRENT

FREE-AIR TEMPERATURE

500

IL = 750 mA

450

Aµ

400

VI = 10 V

0.3 TA = 25°C

0.25

0.2

DROPOUT VOLTAGE

OUTPUT CURRENT

TPS7330

TPS7333

TPS7325

350

300

– Quiescent Current –

250

200

–50 –25 0 25 50 75 100 125

TA – Free-Air Temperature – °C

VI = 3.5 V

Figure 11

CHANGE IN DROPOUT VOLTAGE

FREE-AIR TEMPERATURE

IO = 100 mA

8 6

4 2 0

–2 –4

– Change In Dropout Voltage – mV

–6

∆

–8

0.15

Dropout Voltage – V

0.1

0.05

1.6

1.4

1.2

0.8

0.6

– Dropout Voltage – VV

0.4

0.2

0 50 100 150 200 250 300

IO – Output Current – mA

Figure 12

TPS7301

DROPOUT VOLTAGE

OUTPUT CURRENT

TA = 25°C

VI = 2.9 V

VI = 3.2 V VI = 3.9 V

VI = 5.9 V

VI = 9.65 V

TPS7348

TPS7350

350 400 450 500

VI = 2.4 V

VI = 2.6 V

–10

–50 –25 0 25 50 75 100 125

TA – Free-Air Temperature – °C

Figure 13

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

0 50 100 150 200 250

IO – Output Current – mA

Figure 14

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION

SLVS124F – JUNE 1995 – REVISED JANUARY 1999

TYPICAL CHARACTERISTICS

CHANGE IN OUTPUT VOLTAGE

FREE-AIR TEMPERATURE

VI = V IO = 100 mA

–5

–10

– Change in Output Voltage – mV

–15

∆

–20

–50 –25 0 25 50 75 100 125

+ 1 V

O(nom)

TA – Free-Air Temperature – °C

Figure 15

– Output Voltage – V

OUTPUT VOLTAGE

INPUT VOLTAGE

TA = 25°C IO = 500 mA

TPS7333

TPS7301 With V Programmed to 2.5 V and TPS7325

0123456

VI – Input Voltage – V

Figure 16

TPS7350

TPS7348

78910

2.5

1.5

– Output Voltage – V

0.5

TPS7325

OUTPUT VOLTAGE

INPUT VOLTAGE

TA = 25°C

100 mA

500 mA

0123456

VI – Input Voltage – V

Figure 17

78910

LINE REGULATION

TA = 25°C IO = 250 mA

–5

–10

– Change In Output Voltage – mV

∆V

–15

–20

4567

TPS7325

VI – Input Voltage – V

Figure 18

TPS7350

TPS7348

TPS7333

8910

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q

LOW-DROPOUT VOLTAGE REGULATORS

WITH INTEGRATED DELAYED RESET FUNCTION

SLVS124F – JUNE 1995 – REVISED JANUARY 1999

TYPICAL CHARACTERISTICS

2.52

2.515

2.51

2.505

2.5

2.495

– Output Voltage – V

2.49

2.485

2.48

TPS7301

OUTPUT VOLTAGE

OUTPUT CURRENT

TA = 25°C VO Programmed to 2.5 V

VI = 3.5 V

VI = 10 V

0 100 200 300

IO – Output Current – mA

Figure 19

400 500

2.52

2.515

2.51

2.505

2.5

2.495

– Output Voltage – V

2.49

2.485

2.48

TPS7325

OUTPUT VOLTAGE

OUTPUT CURRENT

VI = 10 V

VI = 3.5 V

0 100 200 300 400 500

IO – Output Current – mA

Figure 20

OUTPUT VOLTAGE

OUTPUT CURRENT

3.15

3.12

3.09

3.06

3.03

2.97

– Output Voltage – V

2.94

2.91

2.88

2.85

TA = 25°C

0 100 300

IO – Output Current – mA

TPS7330

200 400

Figure 21

500

OUTPUT VOLTAGE

OUTPUT CURRENT

3.34 TA = 25°C

3.33

3.32

3.31

3.3

3.29

– Output Voltage – V

3.28

3.27

3.26

0 100 200 300

VI = 4.3 V

IO – Output Current – mA

Figure 22

TPS7333

VI = 10 V

400 500

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION

SLVS124F – JUNE 1995 – REVISED JANUARY 1999

TYPICAL CHARACTERISTICS

OUTPUT VOLTAGE

OUTPUT CURRENT

4.92 TA = 25°C

4.91

4.9

4.89

4.88

4.87

4.86

4.85

– Output Voltage – V

4.84

4.83

4.82

4.81

4.8 0 100 300

IO – Output Current – mA

TPS7348

VI = 5.85 V

VI = 10 V

200 400

Figure 23

500

5.06

5.05

5.04

5.03

5.02

5.01 5

4.99

– Output Voltage – V

4.98

4.97

4.96

4.95

4.94

TPS7350

OUTPUT VOLTAGE

OUTPUT CURRENT

TA = 25°C

VI = 6 V

VI = 10 V

0 100 300

200

IO – Output Current – mA

Figure 24

400 500

– Output Voltage – V

OUTPUT VOLTAGE RESPONSE FROM

ENABLE (EN

O(nom)

TA = 25°C RL = 500 Ω Co = 4.7 µF (CSR = 1Ω) No Input Capacitance

0 20 40 60 80 100 120 140

Time – µs

)

Figure 25

–2

EN Voltage – V

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q

LOW-DROPOUT VOLTAGE REGULATORS

WITH INTEGRATED DELAYED RESET FUNCTION

SLVS124F – JUNE 1995 – REVISED JANUARY 1999

TYPICAL CHARACTERISTICS

TPS7301 (WITH VO PROGRAMMED TO 2.5 V) OR TPS7333

LOAD TRANSIENT RESPONSE

200

100

– Change in Output Voltage – mV∆V

–100

–200

150

100

TA = 25°C VI = 6 V CI = 0 Co = 4.7 µF (CSR = 1 Ω)

105

0 100 200 300 400 500

–45

t – Time – µs

– Output Current – mA

Figure 26

TPS7325

LOAD TRANSIENT RESPONSE

–50

–100

– Change in Output Voltage – mV∆V

–150

–200

–250

–200 –100 0 500100 600

–300 200 300 400

t – Time – µs

Figure 27

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

∆IO = 100 mA VI = 6 V CI = 0 Co = 10 µF TA = 25°C

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION

SLVS124F – JUNE 1995 – REVISED JANUARY 1999

TYPICAL CHARACTERISTICS

TPS7348 OR TPS7350

LOAD TRANSIENT RESPONSE

200

100

– Change in Output Voltage – mV∆V

–100

–200

–50

–100

100

0 100 200 300 400 500

t – Time – µs

Figure 28

TPS7301 WITH VO PROGRAMMED TO 2.5 V

LINE TRANSIENT RESPONSE

TA = 25°C CI = 0 Co = 4.7 µF (CSR = 1 Ω)

VI = 6 V CI = 0 Co = 4.7 µF CSR = 1 Ω TA = 25°C

105

–45

6.5

– Output Current – mA

0 100 200 300 400

t – Time – µs

Figure 29

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

6.25

5.75

– Input Voltage – V

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q

LOW-DROPOUT VOLTAGE REGULATORS

WITH INTEGRATED DELAYED RESET FUNCTION

SLVS124F – JUNE 1995 – REVISED JANUARY 1999

TYPICAL CHARACTERISTICS

TPS7333

LINE TRANSIENT RESPONSE

200

100

– Change in Output Voltage – mV∆V

–50

–100

100

–50

–100

TA = 25°C CI = 0 Co = 4.7 µF (CSR = 1 Ω)

6.5

6.25

– Input Voltage – V

5.75

0 100 200 300 400 500

t – Time – µs

Figure 30

TPS7348 OR TPS7350

LINE TRANSIENT RESPONSE

TA = 25°C CI = 0 Co = 4.7 µF (CSR = 1 Ω)

6.5

0 100 200 300 400 500

t – Time – µs

Figure 31

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

6.25

5.75

– Input Voltage – V

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION

SLVS124F – JUNE 1995 – REVISED JANUARY 1999

TYPICAL CHARACTERISTICS

RIPPLE REJECTION

FREQUENCY

TPS7333

TPS7348/

TPS7350

Ripple Rejection – dB

10 100 1 K 10 K 100 K 1 M 10 M

f – Frequency – Hz

TA = 25°C No Input Capacitance Added VI = VO + 1 V IO = 100 mA Co = 4.7 µF (CSR = 1)

TPS7301 With VO Programmed to 2.5 V

Figure 32

TYPICAL REGIONS OF STABILITY

COMPENSATION SERIES RESISTANCE (CSR)

OUTPUT CURRENT

100

Region of Instability

OUTPUT SPECTRAL-NOISE DENSITY

FREQUENCY

Hzµ V/

0.1

Output Spectral-Noise Density –

Co = 100 µF (CSR = 1 Ω)

0.01 10 100 1 k 10 k 100 k

TA = 25°C No Input Capacitance Added VI = VO + 1 V

Co = 4.7 µF (CSR = 1 Ω)

Co = 10 µF (CSR = 1 Ω)

f – Frequency – Hz

Figure 33

†

COMPENSATION SERIES RESISTANCE (CSR)

100

TYPICAL REGIONS OF STABILITY

ADDED CERAMIC CAPACITANCE

Region of Instability

TA = 25°C VI = VO + 1 V IO = 500 mA Co = 4.7 µF No Input Capacitor Added

†

TA = 25°C

0.1

CSR – Compensation Series Resistance – Ω

0.01

Region of Instability

0 50 100 150 200 250

VI = VO + 1 V Co = 4.7 µF No Added Ceramic Capacitance No Input Capacitance Added

IO – Output Current – mA

Figure 34

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

0.1

CSR – Compensation Series Resistance – Ω

0.01

0 0.1 0.2 0.3 0.4 0.5

Added Ceramic Capacitance – µF

Region of Instability

0.6 0.7 0.8 0.9 1

Figure 35

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q

LOW-DROPOUT VOLTAGE REGULATORS

WITH INTEGRATED DELAYED RESET FUNCTION

SLVS124F – JUNE 1995 – REVISED JANUARY 1999

TYPICAL CHARACTERISTICS

TYPICAL REGIONS OF STABILITY

COMPENSATION SERIES RESISTANCE (CSR)

OUTPUT CURRENT

100

Region of Instability

TA = 25°C

0.1

CSR – Compensation Series Resistance – Ω

0.01 0 50 100 150 200 250

VI = VO + 1 V Co = 10 µF No Added Ceramic Capacitance No Input Capacitor Added

Region of Instability

IO – Output Current – mA

Figure 36

†

COMPENSATION SERIES RESISTANCE (CSR)

TYPICAL REGIONS OF STABILITY

†

ADDED CERAMIC CAPACITANCE

100

Region of Instability

0.1

CSR – Compensation Series Resistance – Ω

0.01 0 0.1 0.2 0.3 0.4 0.5

Added Ceramic Capacitance – µF

TA = 25°C VI = VO + 1 V IO = 500 mA Co = 10 µF No Input Capacitor Added

Region of Instability

0.6 0.7 0.8 0.9 1

Figure 37

PASS-ELEMENT RESISTANCE

INPUT VOLTAGE

1.1 1

Ω

0.9

0.8

0.7

0.6

0.5

0.4

– Pass-Element Resistance –

0.3

DS(on)

0.2

0.1

368

2457

IO = 500 mA

IO = 100 mA

VI – Input Voltage – V

Figure 38

TA = 25°C V

= 1.12 V

I(FB)

910

MINIMUM INPUT VOLTAGE FOR VALID RESET

FREE-AIR TEMPERATURE

1.1

1.09

1.08

1.07

1.06

– Minimum Input Voltage For Valid RESET – V

1.05 –50 –25 0 25 50 75 100 125

TA – Free-Air Temperature – °C

Figure 39

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION

SLVS124F – JUNE 1995 – REVISED JANUARY 1999

TYPICAL CHARACTERISTICS

NEGATIVE-GOING RESET THRESHOLD

FREE-AIR TEMPERATURE

–5

– Negative-Going Reset Threshold – mV

–10

IT–

–15

–50 –25 0 25 50 75 100 125

TA – Free-Air Temperature – °C

Figure 40

RESET DELAY TIME

FREE-AIR TEMPERATURE

197

196

RESET OUTPUT CURRENT

INPUT VOLTAGE

IL = 10 mA VOL ≤ 0.4 V

3.5 TA = 25°C

2.5

1.5

– RESET Output Current – mA

0.5

0123456

VI – Input Voltage – V

Figure 41

DISTRIBUTION FOR RESET DELAY

50 45 40

TPS7350

TPS7348

TPS7333

78910

TA = 25°C 197 Devices

– Reset Delay Time – ms

195

194

193

192

191

190

–50 –25 0 25 50 75 100 125

TA – Free-Air Temperature –°C

Figure 42

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

30 25

20 15

Percentage of Units – %

5 0

180 185 190 195

td – Reset Delay Time – ms

200 205 210

Figure 43

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q

LOW-DROPOUT VOLTAGE REGULATORS

WITH INTEGRATED DELAYED RESET FUNCTION

SLVS124F – JUNE 1995 – REVISED JANUARY 1999

THERMAL INFORMATION

In response to system-miniaturization trends, integrated circuits are being offered in low-profile and fine-pitch surface-mount packages. Implementation of many of today’s high-performance devices in these packages requires special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components affect the power-dissipation limits of a given component.

Three basic approaches for enhancing thermal performance are illustrated in this discussion:

Improving the power-dissipation capability of the PWB design

Improving the thermal coupling of the component to the PWB

Introducing airflow in the system

Figure 44 is an example of a thermally enhanced PWB layout for the 20-lead TSSOP package. This layout involves adding copper on the PWB to conduct heat away from the device. The R for this component/board system is illustrated in Figure 45. The family of curves illustrates the effect of increasing the size of the copper-heat-sink surface area. The PWB is a standard FR4 board (L × W × H = 3.2 inch × 3.2 inch × 0.062 inch); the board traces and heat sink area are 1-oz (per square foot) copper.

Figure 46 shows the thermal resistance for the same system with the addition of a thermally-conductive compound between the body of the TSSOP package and the PWB copper routed directly beneath the device. The thermal conductivity for the compound used in this analysis is 0.815 W/m × °C.

(thermal resistance, junction-to-ambient)

θJA

Using these figures to determine the system R the equation:

D(max)

Where

J(max)

maximum recommended operating temperature for specified operation.

This limit should then be applied to the internal power dissipated by the TPS73xx regulator. The equation for calculating total internal power dissipation of the TPS73xx is:

D(total)

Because the quiescent current of the TPS73xx family is very low, the second term is negligible, further simplifying the equation to:

D(total)

For a 20-lead TSSOP/FR4 board system with thermally conductive compound between the board and the device body , where T can be calculated. As indicated in Figure 46, the system R limit is:

J(max)

is the maximum allowable junction temperature; 150°C absolute maximum and 125°C

+ǒVI*

VI*

= 55°C, airflow = 100 ft/min, and copper heat sink area = 1 cm2, the maximum power-dissipation limit

JA(system)

IO)

allows the maximum power-dissipation limit to be calculated with

θJA

is 94°C/W; therefore, the maximum power-dissipation

θJA

D(max)

If the system implements a TPS7348 regulator where VI = 6 V and IO = 150 mA, the internal power dissipation is:

D(total)

J(max)

+ǒVI*

JA(system)

IO+(6*

°°

125 C*55 C

94 CńW

4.85) 0.150+173 mW

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

745 mW

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION

SLVS124F – JUNE 1995 – REVISED JANUARY 1999

THERMAL INFORMATION

Comparing P

D(total)

with P

reveals that the power dissipation in this example does not exceed the maximum

D(max)

limit. When it does, one of two corrective actions can be taken. The power-dissipation limit can be raised by increasing either the airflow or the heat-sink area. Alternatively , the internal power dissipation of the regulator can be lowered by reducing either the input voltage or the load current. In either case, the above calculations should be repeated with the new system parameters.

Copper Heat Sink

1 oz Cu

Figure 44. Thermally Enhanced PWB Layout (not to scale) for the 20-Pin TSSOP

THERMAL RESISTANCE, JUNCTION-TO-AMBIENT

AIR FLOW

190

C/W

170

1 cm

150

130

Component/Board System 20-Lead TSSOP

0 cm

2 cm

THERMAL RESISTANCE, JUNCTION-TO-AMBIENT

AIR FLOW

190

C/W

Component/Board System 20-Lead TSSOP

170

Includes Thermally Conductive Compound Between Body and Board

150

130

0 cm

110

JAθ

0 50 100 150 200 250

R – Thermal Resistance, Junction-to-Ambient –

4 cm

Air Flow – ft/min

8 cm

Figure 45

110

JAθ

300

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

0 50 100 150 200 250

R – Thermal Resistance, Junction-to-Ambient –

8 cm

Air Flow – ft/min

Figure 46

4 cm

2 cm

1 cm

300

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q

LOW-DROPOUT VOLTAGE REGULATORS

WITH INTEGRATED DELAYED RESET FUNCTION

SLVS124F – JUNE 1995 – REVISED JANUARY 1999

APPLICATION INFORMATION

The TPS73xx series of low-dropout (LDO) regulators overcome many of the shortcomings of earlier generation LDOs, while adding features such as a power-saving shutdown mode and a supply-voltage supervisor. The TPS73xx family includes five fixed-output voltage regulators: the TPS7325 (2.5 V), TPS7330 (3 V), TPS7333 (3.3 V), the TPS7348 (4.85 V), and the TPS7350 (5 V). The family also offers an adjustable device, the TPS7301 (adjustable from 1.2 V to 9.75 V).

device operation

The TPS73xx, unlike many other LDOs, features very low quiescent currents that remain virtually constant even with varying loads. Conventional LDO regulators use a pnp-pass element, the base current of which is directly proportional to the load current through the regulator (I that such devices are typically specified under near no-load conditions; actual operating currents are much higher as evidenced by typical quiescent current versus load current curves (see Figure 7). The TPS73xx uses a PMOS transistor to pass current; because the gate of the PMOS element is voltage driven, operating currents are low and invariable over the full load range. The TPS73xx specifications reflect actual performance under load.

Another pitfall associated with the pnp-pass element is its tendency to saturate when the device goes into dropout. The resulting drop in β forces an increase in IB to maintain the load. During power-up, this translates to large start-up currents. Systems with limited supply current may fail to start up. In battery-powered systems, it means rapid battery discharge when the voltage decays below the minimum required for regulation. The TPS73xx quiescent current remains low even when the regulator drops out, thus eliminating both problems.

= IC/β). Close examination of the data sheets reveals

Included in the TPS73xx family is a 4.85-V regulator, the TPS7348. Designed specifically for 5-V cellular systems, its 4.85-V output, regulated to within ± 2%, allows for operation within the low-end limit of 5-V systems specified to ± 5% tolerance; therefore, maximum regulated operating lifetime is obtained from a battery pack before the device drops out, adding crucial talk minutes between charges.

The TPS73xx family also features a shutdown mode that places the output in the high-impedance state (essentially equal to the feedback-divider resistance) and reduces quiescent current to under 0.5 µA. When the shutdown feature is not used, EN output voltage is reestablished in typically 120 µs.

should be tied to ground. Response to an enable transition is quick; regulated

minimum load requirements

The TPS73xx family is stable even at zero load; no minimum load is required for operation.

SENSE connection

The SENSE terminal of fixed-output devices must be connected to the regulator output for proper functioning of the regulator. Normally , this connection should be as short as possible; however , the connection can be made near a critical circuit (remote sense) to improve performance at that point. Internally, SENSE connects to a high-impedance wide-bandwidth amplifier through a resistor-divider network, and noise pickup feeds through to the regulator output. It is essential to route the SENSE connection in such a way as to minimize/avoid noise pickup. Adding an RC network between SENSE and OUT to filter noise is not recommended because it can cause the regulator to oscillate.

external capacitor requirements

An input capacitor is not required; however, a ceramic bypass capacitor (0.047 pF to 0.1 µF) improves load transient response and noise rejection when the TPS73xx is located more than a few inches from the power supply. A higher-capacitance electrolytic capacitor may be necessary if large (hundreds of milliamps) load transients with fast rise times are anticipated.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION

SLVS124F – JUNE 1995 – REVISED JANUARY 1999

APPLICATION INFORMATION

external capacitor requirements (continued)

As with most LDO regulators, the TPS73xx family requires an output capacitor for stability. A low-ESR 10-µF solid-tantalum capacitor connected from the regulator output to ground is sufficient to ensure stability over the full load range (see Figure 42). Adding high-frequency ceramic or film capacitors (such as power-supply bypass capacitors for digital or analog ICs) can cause the regulator to become unstable unless the ESR of the tantalum capacitor is less than 1.2 Ω over temperature. Capacitors with published ESR specifications such as the AVX TPSD106M035R0300 and the Sprague 593D106X0035D2W work well because the maximum ESR at 25°C is 300 mΩ (typically, the ESR in solid-tantalum capacitors increases by a factor of 2 or less when the temperature drops from 25°C to –40°C). Where component height and/or mounting area is a problem, physically smaller, 10-µF devices can be screened for ESR. Figures 29 through 32 show the stable regions of operation using different values of output capacitance with various values of ceramic load capacitance.

In applications with little or no high-frequency bypass capacitance (< 0.2 µF), the output capacitance can be reduced to 4.7 µF, provided ESR is maintained between 0.7 and 2.5 Ω. Because capacitor minimum ESR is seldom if ever specified, it may be necessary to add a 0.5-Ω to 1-Ω resistor in series with the capacitor and limit ESR to 1.5 Ω maximum. As shown in the CSR graphs (Figures 29 through 32), minimum ESR is not a problem when using 10-µF or larger output capacitors.

Below is a partial listing of surface-mount capacitors usable with the TPS73xx family. This information, along with the CSR graphs, is included to assist in selection of suitable capacitance for the user’s application. When necessary to achieve low height requirements along with high output current and/or high ceramic load capacitance, several higher ESR capacitors can be used in parallel to meet the guidelines above.

All load and temperature conditions with up to 1 µF of added ceramic load capacitance:

PART NO. MFR. VALUE MAX ESR

†

SIZE (H × L × W)

†

T421C226M010AS Kemet 22 µF, 10 V 0.5 2.8 × 6 × 3.2 593D156X0025D2W Sprague 15 µF, 25 V 0.3 2.8 × 7.3 × 4.3 593D106X0035D2W Sprague 10 µF, 35 V 0.3 2.8 × 7.3 × 4.3 TPSD106M035R0300 AVX 10 µF, 35 V 0.3 2.8 × 7.3 × 4.3

Load < 200 mA, ceramic load capacitance < 0.2 µF, full temperature range:

PART NO. MFR. VALUE MAX ESR

†

SIZE (H × L × W)

†

592D156X0020R2T Sprague 15 µF, 20 V 1.1 1.2 × 7.2 × 6 595D156X0025C2T Sprague 15 µF, 25 V 1 2.5 × 7.1 × 3.2 595D106X0025C2T Sprague 10 µF, 25 V 1.2 2.5 × 7.1 × 3.2 293D226X0016D2W Sprague 22 µF, 16 V 1.1 2.8 × 7.3 × 4.3

Load < 100 mA, ceramic load capacitance < 0.2 µF, full temperature range:

PART NO. MFR. VALUE MAX ESR

†

SIZE (H × L × W)

†

195D106X06R3V2T Sprague 10 µF, 6.3 V 1.5 1.3 × 3.5 × 2.7 195D106X0016X2T Sprague 10 µF, 16 V 1.5 1.3 × 7 × 2.7 595D156X0016B2T Sprague 15 µF, 16 V 1.8 1.6 × 3.8 × 2.6 695D226X0015F2T Sprague 22 µF, 15 V 1.4 1.8 × 6.5 × 3.4 695D156X0020F2T Sprague 15 µF, 20 V 1.5 1.8 × 6.5 × 3.4 695D106X0035G2T Sprague 10 µF, 35 V 1.3 2.5 × 7.6 × 2.5

†

Size is in mm. ESR is maximum resistance at 100 kHz and TA = 25°C. Listings are sorted by height.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q

APPLICATION INFORMATION

external capacitor requirements (continued)

0.1 µF

†

TPS7333, TPS7348, TPS7350 (fixed-voltage options)

Figure 47. Typical Application Circuit

8 9

LOW-DROPOUT VOLTAGE REGULATORS

WITH INTEGRATED DELAYED RESET FUNCTION

SLVS124F – JUNE 1995 – REVISED JANUARY 1999

RESET

SENSE

OUT OUT

†

20 15 14 13

321

To System Reset

250 kΩ

10 µF

CSR = 1 Ω

TPS73xxPW

IN IN

GND

programming the TPS7301 adjustable LDO regulator

Programming the adjustable regulators is accomplished using an external resistor divider as shown in Figure 43. The equation governing the output voltage is:

VO+

Where

ref

ǒ1

ref

= reference voltage, 1.182 V typ

)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION

SLVS124F – JUNE 1995 – REVISED JANUARY 1999

APPLICATION INFORMATION

Resistors R1 and R2 should be chosen for approximately 7-µA divider current. A recommended value for R2 is 169 kΩ with R1 adjusted for the desired output voltage. Smaller resistors can be used, but offer no inherent advantage and consume more power. Larger values of R1 and R2 should be avoided as leakage currents at FB will introduce an error. Solving for R1 yields a more useful equation for choosing the appropriate resistance:

ref

TPS7301

RESET

GND

OUT

250 kΩ

To System Reset

10 µF

CSR = 1 Ω

OUTPUT VOLTAGE

PROGRAMMING GUIDE

OUTPUT

VOLTAGE

2.5 V

3.3 V

3.6 V 4 V 5 V

6.4 V

R1 R2

191 309 348 402 549 750

169 169 169 169 169 169

>2.7 V

0.1 µF

<0.5 V

UNIT

kΩ kΩ kΩ kΩ kΩ kΩ

Figure 48. TPS7301 Adjustable LDO Regulator Programming

undervoltage supervisor function

The RESET output of the TPS73xx initiates a reset in microcomputer and microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS73xx monitors the output voltage of the regulator to detect the undervoltage condition. When that occurs, the RESET signal low.

On power up, the output voltage tracks the input voltage. The RESET approaches the minimum required for a valid RESET signal (specified at 1.5 V for 25°C and 1.9 V over full recommended operating temperature range). When the output voltage reaches the appropriate positive-going input threshold (V

), a 200-ms (typical) timeout period begins during which the RESET output remains low.

IT+

Once the timeout has expired, the RESET output becomes inactive. Since the RESET output is an open-drain NMOS, a pullup resistor should be used to ensure that a logic-high signal is indicated.

The supply-voltage-supervisor function is also activated during power-down. As the input voltage decays and after the dropout voltage is reached, the output voltage tracks linearly with the decaying input voltage. When the output voltage drops below the specified negative-going input threshold (V characteristics tables), the RESET output becomes active (low). It is important to note that if the input voltage decays below the minimum required for a valid RESET, the RESET is undefined.

Since the circuit is monitoring the regulator output voltage, the RESET output can also be triggered by disabling the regulator or by any fault condition that causes the output to drop below V include a short circuit on the output and a low input voltage. Once the output voltage is reestablished, either by reenabling the regulator or removing the fault condition, then the internal timer is initiated, which holds the RESET

signal active during the 200-ms (typical) timeout period.

output transistor turns on taking the RESET

output becomes active (low) as V

— see electrical

IT–

. Examples of fault conditions

IT–

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q

LOW-DROPOUT VOLTAGE REGULATORS

WITH INTEGRATED DELAYED RESET FUNCTION

SLVS124F – JUNE 1995 – REVISED JANUARY 1999

APPLICATION INFORMATION

undervoltage supervisor function (continued)

Transient loads or line pulses can also cause a reset to occur if proper care is not taken in selecting the input and output capacitors. Load transients that are faster than 5 µs can cause a reset if high-ESR output capacitors (greater than approximately 7 Ω) are used. A 1-µs transient causes a reset when using an output capacitor with greater than 3.5 Ω of ESR. Note that the output-voltage spike during the transient can drop well below the reset threshold and still not trip if the transient duration is short. A 1-µs transient must drop at least 500 mV below the threshold before tripping the reset circuit. A 2-µs transient trips RESET Lower-ESR output capacitors help by reducing the drop in output voltage during a transient and should be used when fast transients are expected.

NOTE:

= V

IT+

+Hysteresis

IT–

output noise

The TPS73xx has very low output noise, with a spectral noise density < 2 µV/√Hz. This is important when noise-susceptible systems, such as audio amplifiers, are powered by the regulator.

at just 400 mV below the threshold.

regulator protection

The TPS73xx PMOS-pass transistor has a built-in back diode that safely conducts reverse currents when the input voltage drops below the output voltage (e.g., during power down). Current is conducted from the output to the input and is not internally limited. If extended reverse voltage is anticipated, external limiting might be appropriate.

The TPS73xx also features internal current limiting and thermal protection. During normal operation, the TPS73xx limits output current to approximately 1 A. When current limiting engages, the output voltage scales back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of the device exceeds 165°C, thermal-protection circuitry shuts it down. Once the device has cooled, regulator operation resumes.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION

SLVS124F – JUNE 1995 – REVISED JANUARY 1999

MECHANICAL DATA

D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PIN SHOWN

0.050 (1,27)

0.069 (1,75) MAX

0.020 (0,51)

0.014 (0,35)

0.010 (0,25)

0.004 (0,10)

DIM

PINS **

0.010 (0,25)

0.157 (4,00)

0.150 (3,81)

0.244 (6,20)

0.228 (5,80)

Seating Plane

0.004 (0,10)

0.008 (0,20) NOM

0°–8°

Gage Plane

0.010 (0,25)

0.044 (1,12)

0.016 (0,40)

A MAX

A MIN

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). D. Falls within JEDEC MS-012

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

0.197

(5,00)

0.189

(4,80)

0.344

(8,75)

0.337

(8,55)

0.394

(10,00)

0.386

(9,80)

4040047/D 10/96

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q

LOW-DROPOUT VOLTAGE REGULATORS

WITH INTEGRATED DELAYED RESET FUNCTION

SLVS124F – JUNE 1995 – REVISED JANUARY 1999

MECHANICAL DATA

P (R-PDIP-T8) PLASTIC DUAL-IN-LINE PACKAGE

0.400 (10,60)

0.355 (9,02)

0.260 (6,60)

0.240 (6,10)

0.070 (1,78) MAX

0.020 (0,51) MIN

0.200 (5,08) MAX

0.125 (3,18) MIN

0.100 (2,54)

0.021 (0,53)

0.015 (0,38)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001

0.010 (0,25)

0.310 (7,87)

0.290 (7,37)

Seating Plane

0°–15°

0.010 (0,25) NOM

4040082/B 03/95

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION

SLVS124F – JUNE 1995 – REVISED JANUARY 1999

MECHANICAL DATA

PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PIN SHOWN

0,65

1,20 MAX

0,30 0,19

6,60

4,50 4,30

6,20

0,15 0,05

0,10

Seating Plane

0,10

0,15 NOM

Gage Plane

0,25

0°–8°

0,75 0,50

PINS **

DIM

A MAX

A MIN

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

3,10

2,90

5,10

4,90

5,10

6,60

6,404,90

7,90

7,70

9,80

9,60

4040064/E 08/96

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

PACKAGING INFORMATION

Orderable Device Status

TPS7301QD ACTIVE SOIC D 8 75 Green (RoHS &

TPS7301QDG4 ACTIVE SOIC D 8 75 Green (RoHS &

TPS7301QDR ACTIVE SOIC D 8 2500 Green (RoHS &

TPS7301QDRG4 ACTIVE SOIC D 8 2500 Green (RoHS &

TPS7301QP ACTIVE PDIP P 8 50 Pb-Free

TPS7301QPE4 ACTIVE PDIP P 8 50 Pb-Free

TPS7301QPW ACTIVE TSSOP PW 20 70 Green (RoHS &

TPS7301QPWLE OBSOLETE TSSOP PW 20 TBD Call TI CallTI

TPS7301QPWR ACTIVE TSSOP PW 20 2000 Green (RoHS &

TPS7301QPWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS &

TPS7325QD ACTIVE SOIC D 8 75 Green (RoHS &

TPS7325QDR ACTIVE SOIC D 8 2500 Green (RoHS &

TPS7325QDRG4 ACTIVE SOIC D 8 2500 Green (RoHS &

TPS7325QP ACTIVE PDIP P 8 50 Pb-Free

TPS7325QPE4 ACTIVE PDIP P 8 50 Pb-Free

TPS7325QPW ACTIVE TSSOP PW 20 70 Green (RoHS &

TPS7325QPWR ACTIVE TSSOP PW 20 2000 Green (RoHS &

TPS7330QD ACTIVE SOIC D 8 75 Green (RoHS &

TPS7330QDR ACTIVE SOIC D 8 2500 Green (RoHS &

TPS7330QP ACTIVE PDIP P 8 50 Pb-Free

TPS7330QPE4 ACTIVE PDIP P 8 50 Pb-Free

TPS7330QPW ACTIVE TSSOP PW 20 70 Green (RoHS &

TPS7330QPWR ACTIVE TSSOP PW 20 2000 Green (RoHS &

TPS7333QD ACTIVE SOIC D 8 75 Green (RoHS &

TPS7333QDG4 ACTIVE SOIC D 8 75 Green (RoHS &

(1)

Package

Type

Package

Drawing

Pins Package

Qty

Eco Plan

no Sb/Br)

(RoHS)

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-NC-NC-NC

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-NC-NC-NC

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-NC-NC-NC

CU NIPDAU Level-1-260C-UNLIM

8-Aug-2005

(3)

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

Orderable Device Status

(1)

Package

Type

Package

Drawing

Pins Package

Qty

Eco Plan

TPS7333QDR ACTIVE SOIC D 8 2500 Green (RoHS &

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TPS7333QDRG4 ACTIVE SOIC D 8 2500 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TPS7333QP ACTIVE PDIP P 8 50 Pb-Free

CU NIPDAU Level-NC-NC-NC

(RoHS)

TPS7333QPE4 ACTIVE PDIP P 8 50 Pb-Free

CU NIPDAU Level-NC-NC-NC

(RoHS)

TPS7333QPW ACTIVE TSSOP PW 20 70 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TPS7333QPWG4 ACTIVE TSSOP PW 20 70 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TPS7333QPWLE OBSOLETE TSSOP PW 20 TBD Call TI CallTI

TPS7333QPWR ACTIVE TSSOP PW 20 2000 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TPS7333QPWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TPS7348QD ACTIVE SOIC D 8 75 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TPS7348QDR ACTIVE SOIC D 8 2500 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TPS7348QDRG4 ACTIVE SOIC D 8 2500 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TPS7348QP ACTIVE PDIP P 8 50 Pb-Free

CU NIPDAU Level-NC-NC-NC

(RoHS)

TPS7348QPE4 ACTIVE PDIP P 8 50 Pb-Free

CU NIPDAU Level-NC-NC-NC

(RoHS)

TPS7348QPW ACTIVE TSSOP PW 20 70 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TPS7348QPWG4 ACTIVE TSSOP PW 20 70 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TPS7348QPWLE OBSOLETE TSSOP PW 20 TBD Call TI CallTI

TPS7348QPWR ACTIVE TSSOP PW 20 2000 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TPS7348QPWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TPS7350QD ACTIVE SOIC D 8 75 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TPS7350QDG4 ACTIVE SOIC D 8 75 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TPS7350QDR ACTIVE SOIC D 8 2500 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TPS7350QDRG4 ACTIVE SOIC D 8 2500 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TPS7350QP ACTIVE PDIP P 8 50 Pb-Free

CU NIPDAU Level-NC-NC-NC

(RoHS)

TPS7350QPE4 ACTIVE PDIP P 8 50 Pb-Free

CU NIPDAU Level-NC-NC-NC

(RoHS)

TPS7350QPW ACTIVE TSSOP PW 20 70 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TPS7350QPWLE OBSOLETE TSSOP PW 20 TBD Call TI CallTI

8-Aug-2005

(3)

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

Orderable Device Status

(1)

Package

Type

Package

Drawing

Pins Package

Qty

Eco Plan

TPS7350QPWR ACTIVE TSSOP PW 20 2000 Green (RoHS &

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-1-260C-UNLIM

8-Aug-2005

(3)

no Sb/Br)

TPS7350QPWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 3

IMPORTANT NOTICE

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TEXAS INSTRUMENTS TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual