Texas Instruments TPS70145, TPS70148, TPS70151, TPS70158, TPS70102 Datasheet

1 2 3 4 5 6 7 8 9 10

20 19 18 17 16 15 14 13 12 11

PWP PACKAGE

(TOP VIEW)

IN1

MR1 MR2

SEQ

GND

IN2

NC V

OUT1

SENSE1

/FB1 PG1 RESET V

SENSE2

/FB2 V

OUT2

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TPS70145, TPS70148 TPS70151, TPS70158

TPS70102

SLVS222I –DECEMBER 1999–REVISED AUGUST 2010

Dual-Output Low Dropout Voltage Regulators

with Power-Up Sequencing for Split-Voltage DSP Systems

Check for Samples: TPS70145, TPS70148, TPS70151, TPS70158, TPS70102

FEATURES

• Dual Output Voltages for Split-Supply Applications

• Selectable Power-Up Sequencing for DSP Applications

• Output Current Range of 500mA on Regulator 1 and 250mA on Regulator 2

• Fast Transient Response

• Voltage Options: 3.3V/2.5V, 3.3V/1.8V,

3.3V/1.5V, 3.3V/1.2V, and Dual Adjustable Outputs

• Open Drain Power-On Reset with 120ms Delay

• Open Drain Power Good for Regulator 1

• Ultra Low 190mA (typ) Quiescent Current

• 1mA Input Current During Standby

• Low Noise: 65mV

Without Bypass Capacitor

RMS

• Quick Output Capacitor Discharge Feature

• Two Manual Reset Inputs

• 2% Accuracy Over Load and Temperature

• Undervoltage Lockout (UVLO) Feature

• 20-Pin PowerPAD™ TSSOP Package

• Thermal Shutdown Protection

DESCRIPTION

TPS701xx family devices are designed to provide a complete power management solution for the TMS320™ DSP family, processor power, ASIC, FPGA, and digital applications where dual output voltage regulators are required. Easy programmability of the sequencing function makes the TPS701xx family ideal for any TMS320 DSP applications with power sequencing requirements. Differentiated features, such as accuracy, fast transient response, SVS supervisory circuit, manual reset inputs, and an enable function, provide a complete system solution.

The TPS701xx family of voltage regulators offer very low dropout voltage and dual outputs with power-up sequence control, which is designed primarily for DSP applications. These devices have extremely low noise output performance without using any added filter bypass capacitors and are designed to have a fast transient response and be stable with 10mF low ESR capacitors.

These devices have fixed 3.3V/2.5V, 3.3V/1.8V,

3.3V/1.5V, 3.3V/1.2V, and adjustable/adjustable voltage options. Regulator 1 can support up to 500mA, and regulator 2 can support up to 250mA. Separate voltage inputs allow the designer to configure the source power.

2PowerPAD, TMS320 are trademarks of Texas Instruments. 3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1.8 V

IN1

IN2

SEQ

OUT1

SENSE1

PG1

MR2

RESET

MR1

SENSE2

OUT2

TPS70151 PWP

5 V

3.3 V

I/O

MR1

Core

0.1 µF

RESET

10 µF

0.1 µF

DSP

MR2

PG1

250 kΩ

>2 V

<0.7 V

250 kΩ

>2 V

<0.7 V

>2 V

<0.7 V

TPS70145, TPS70148 TPS70151, TPS70158 TPS70102

SLVS222I –DECEMBER 1999–REVISED AUGUST 2010

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Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 170mV on regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (maximum of 230mA over the full range of output current). This LDO family also features a sleep mode; applying a high signal to EN (enable) shuts down both regulators, reducing the input current to 1mA at TJ= +25°C.

The device is enabled when the EN pin is connected to a low-level input voltage. The output voltages of the two regulators are sensed at the V

SENSE1

and V

SENSE2

pins, respectively.

The input signal at the SEQ pin controls the power-up sequence of the two regulators. When the device is enabled and the SEQ terminal is pulled high or left open, V reaches approximately 83% of its regulated output voltage. At that time V below 83% (for example, an overload condition), V power-up order and V

is turned on first. The SEQ pin is connected to an internal pull-up current source.

OUT1

is turned off. Pulling the SEQ terminal low reverses the

OUT1

turns on first and V

OUT2

OUT1

is turned on. If V

OUT1

remains off until V

is pulled

OUT2

For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator is turned off (disabled).

The PG1 pin reports the voltage conditions at V

, which can be used to implement an SVS for the circuitry

OUT1

supplied by regulator 1. The TPS701xx features a RESET (SVS, POR, or Power-On Reset). RESET output initiates a reset in DSP

systems and related digital applications in the event of an undervoltage condition. RESET indicates the status of V

and both manual reset pins (MR1 and MR2). When V

OUT2

and MR2 are in the logic high state, RESET goes to a high impedance state after a 120ms delay. RESET goes to the logic low state when the V condition) of its regulated voltage. To monitor V

The device has an undervoltage lockout (UVLO) circuit that prevents the internal regulators from turning on until V

reaches 2.5V.

IN1

regulated output voltage is pulled below 95% (for example, an overload

OUT2

OUT1

, the PG1 output pin can be connected to MR1 or MR2.

reaches 95% of its regulated voltage and MR1

OUT2

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TPS70145, TPS70148 TPS70151, TPS70158

TPS70102

SLVS222I –DECEMBER 1999–REVISED AUGUST 2010

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

(1)

VOLTAGE (V)

ORDERING INFORMATION

(2)

PACKAGE- SPECIFIED

LEAD TEMPERATURE ORDERING TRANSPORT

PRODUCT V

OUT1

TPS70102 Adjustable Adjustable HTSSOP-20 (PWP) -40°C to +125°C

TPS70145 3.3 V 1.2 V HTSSOP-20 (PWP) -40°C to +125°C

TPS70148 3.3 V 1.5 V HTSSOP-20 (PWP) -40°C to +125°C

TPS70151 3.3 V 1.8 V HTSSOP-20 (PWP) -40°C to +125°C

TPS70158 3.3 V 2.5 V HTSSOP-20 (PWP) -40°C to +125°C

OUT2

(DESIGNATOR) RANGE (TJ) NUMBER MEDIA, QUANTITY

TPS70102PWP Tube, 70

TPS70102PWPR Tape and Reel, 2000

TPS70145PWP Tube, 70

TPS70145PWPR Tape and Reel, 2000

TPS70148PWP Tube, 70

TPS70148PWPR Tape and Reel, 2000

TPS70151PWP Tube, 70

TPS70151PWPR Tape and Reel, 2000

TPS70158PWP Tube, 70

TPS70158PWPR Tape and Reel, 2000

(1) For the most current package and ordering information see the Package Option Addendum located at the end of this document, or see

the TI web site at www.ti.com.

(2) For fixed 1.20V operation, tie FB to OUT.

ABSOLUTE MAXIMUM RATINGS

(1)

Over operating free-air temperature range (unless otherwise noted).

TPS701xx UNIT

Input voltage range: V

IN1

Voltage range at EN –0.3 to +7 V Output voltage range (V Output voltage range (V Maximum RESET, PG1 voltage 7 V Maximum MR1, MR2, and SEQ voltage V Peak output current Internally limited — Continuous total power dissipation See Thermal Information Table — Junction temperature range, T Storage temperature range, T ESD rating, HBM 2 kV

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are tied to network ground.

, V

OUT1 OUT2

IN2

, V , V

stg

(2)

) 5.5 V

SENSE1

) 5.5 V

SENSE2

–0.3 to +7 V

IN1

–40 to +150 °C –65 to +150 °C

LineReg. (mV) + (%ń V) V

Imax

*2.7V

100

1000

LineReg. (mV) + (%ń V) V

Imax

VO)1V

ǓǓ

100

1000

TPS70145, TPS70148 TPS70151, TPS70158 TPS70102

SLVS222I –DECEMBER 1999–REVISED AUGUST 2010

THERMAL INFORMATION

(1) (2)

JA JCtop JB

JT JB

JCbot

THERMAL METRIC

Junction-to-ambient thermal resistance 74.1 Junction-to-case (top) thermal resistance 43.1 Junction-to-board thermal resistance 19.7 Junction-to-top characterization parameter 2.9 Junction-to-board characterization parameter 17.3 Junction-to-case (bottom) thermal resistance 1.4

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. (2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.

TPS701xx

PWP (20 PINS)

RECOMMENDED OPERATING CONDITIONS

Over operating temperature range (unless otherwise noted)

MIN MAX UNIT

Input voltage, V Output current, IO(regulator 1) 0 500 mA Output current, IO(regulator 2) 0 250 mA Output voltage range (for adjustable option) 1.22 5.5 V Operating junction temperature, T

(1) To calculate the minimum input voltage for maximum output current, use the following equation: V

(1)

(regulator 1 and 2) 2.7 6 V

–40 +125 °C

I(min)

= V

O(max)

+ V

DO(max load)

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UNITS

°C/W

ELECTRICAL CHARACTERISTICS

Over recommended operating junction temperature range (TJ= –40°C to +125°C), V EN = 0V, CO= 33mF, (unless otherwise noted).

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Reference 2.7V < VI< 6V, voltage TJ= +25°C

1.2V Output 2.7V < VI< 6V, TJ= +25°C 1.2

voltage

(2)

Output

1.5V Output 2.7V < VI< 6V, TJ= +25°C 1.5

(1) ,

1.8V Output 2.7V < VI< 6V, TJ= +25°C 1.8

2.5V Output 2.7V < VI< 6V, TJ= +25°C 2.5

3.3V Output 2.7V < VI< 6V, TJ= +25°C 3.3

Quiescent current (GND current) for regulator 1 and regulator 2, EN = 0V

Output voltage line regulation (∆VO/VO) for regulator 1 and regulator 2

Load regulation for V

OUT 1

and V

(3)

OUT2

2.7V < VI< 6V, FB connected to V

2.7V < VI< 6V, 1.176 1.224

2.7V < VI< 6V, 1.47 1.53

2.7V < VI< 6V, 1.764 1.836

2.7V < VI< 6V, 2.45 2.55

2.7V < VI< 6V, 3.234 3.366

(2)

(1)

(2)

VO+ 1V < VI≤ 6V, TJ= +25°C VO+ 1V < VI≤ 6V TJ= +25°C

FB connected to V

TJ= +25°C 190

(1) (1) (2)

or V

IN2

= V

OUT(nom)

IN1

1.196 1.244

+ 1V, IO= 1mA,

1.22

0.01%

0.1%

1 mV

230

(1) Minimum input operating voltage is 2.7V or V

current = 1mA.

(2) IO= 1mA to 250mA for Regulator 1 and 1mA to 125mA for Regulator 2.

(3) If VO< 1.8V then V

If VO> 2.5V then V

+ 1V, whichever is greater. Maximum input voltage = 6V, minimum output

O(typ)

= 6V, V

Imax

= 6V, V

Imax

Imin

= 2.7V:

= VO+ 1V:

TPS70145, TPS70148 TPS70151, TPS70158

TPS70102

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ELECTRICAL CHARACTERISTICS (continued)

Over recommended operating junction temperature range (TJ= –40°C to +125°C), V EN = 0V, CO= 33mF, (unless otherwise noted).

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Output noise voltage

Output current limit V

Thermal shutdown junction temperature +150 °C

(standby) current

PSRR 60

Standby

Power-supply ripple f = 1kHz, CO= 33mF, TJ= +25°C rejection

RESET Terminal

Minimum input voltage for valid RESET I Trip threshold voltage VOdecreasing 92% 95% 98% V Hysteresis voltage Measured at V t

(RESET)

r (RESET)

Output low voltage VI= 3.5V, I Leakage current V

PG1 Terminal

Minimum input voltage for valid PG1 I Trip threshold voltage VOdecreasing 92% 95% 98% V Hysteresis voltage Measured at V t

r(PG1)

Output low voltage VI= 2.7V, I Leakage current V

EN Terminal

High level EN input voltage 2 V Low level EN input voltage 0.7 V Input current (EN) –1 1 mA Falling edge deglitch Measured at V

SEQ Terminal

High level SEQ input voltage 2 V Low level SEQ input voltage 0.7 V SEQ pull-up current source 6 mA

MR1 / MR2 Terminals

High level input voltage 2 V Low level input voltage 0.7 V Pull-up current source 6 mA

Terminal

OUT2

UV comparator: Positive-going

OUT2

input threshold voltage of V comparator

UV comparator: Hysteresis 0.5% V

OUT2

UV comparator: Falling edge

OUT2

deglitch Peak output current 2ms pulse width 375 mA

Regulator 1 65 Regulator 2 65 Regulator 1 1.6 1.9 Regulator 2 0.750 1

Regulator 1 mA

Regulator 2 mA

BW 300Hz to 50kHz, CO= 33mF, TJ= +25°C mV

= 0V A

OUT

EN = VI, TJ= +25°C 1 EN = V

= 300mA, V

RESET

≤ 0.8V 1.0 1.3 V

(RESET)

RESET pulse duration 80 120 160 ms Rising edge deglitch 30 ms

O(RESET)

= 6V 1 mA

(RESET)

= 300mA, V

(PG1)

= 1mA 0.15 0.4 V

≤ 0.8V 1.0 1.3 V

(PG1)

Rising edge deglitch 30 ms

= 1mA 0.15 0.4 V

O(PG1)

= 6V 1 mA

(PG1)

UV 80% VO83% VO86% V

OUT2

SENSE_2

decreasing below threshold 140 ms

SLVS222I –DECEMBER 1999–REVISED AUGUST 2010

or V

IN2

= V

OUT(nom)

IN1

(1)

+ 1V, IO= 1mA,

0.5% V

140 ms

RMS

OUT OUT

TPS70145, TPS70148 TPS70151, TPS70158 TPS70102

SLVS222I –DECEMBER 1999–REVISED AUGUST 2010

ELECTRICAL CHARACTERISTICS (continued)

Over recommended operating junction temperature range (TJ= –40°C to +125°C), V EN = 0V, CO= 33mF, (unless otherwise noted).

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Discharge transistor current V

Terminal

OUT1

UV comparator: Positive-going

OUT1

input threshold voltage of V comparator

UV comparator: Hysteresis 0.5% V

OUT1

UV comparator: Falling edge

OUT1

deglitch

Terminal, continued

OUT1

Dropout voltage Dropout voltage Peak output current

(4) (4)

(4)

UV 80% VO83% VO86% V

OUT1

Discharge transistor current V V

UVLO threshold 2.4 2.65 V

IN1

FB Terminal

Input current: TPS70102 FB = 1.8V 1 mA

(4) Input voltage (V

The 3.3V regulator input is set to 3.2V to perform this test.

IN1

or V

IN2

) = V

O(typ)

= 1.5V 7.5 mA

OUT2

SENSE_1

IO= 500mA, TJ= +25°C V IO= 500mA, V

decreasing below threshold 140 ms

= 3.2V 170 mV

IN1

= 3.2V 275 mV

IN1

2ms pulse width 750 mA

= 1.5V 7.5 mA

OUT1

– 100mV. For 1.5V, 1.8V and 2.5V regulators, the dropout voltage is limited by input voltage range.

IN1

or V

IN2

= V

OUT(nom)

+ 1V, IO= 1mA,

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UVLO1 Comp

Thermal

Shutdown

2.5V

Current

Sense

Reference

ref

ENA_1

FB1

ENA_1

120ms

Delay

0.95xV

ref

FB2

Current

Sense

ENA_2

ref

IN1

(2Pins)

GND

IN2

(2Pins)

SEQ

(seeNoteB)

PG1

MR2

RESET

IN1

MR1

IN1

RisingEdge

Deglitch

Reset Comp

OUT2

(2Pins)

FallingEdge

Deglitch

0.83 x V

ref

FB2

V UVComp

OUT2

FallingEdge

Deglitch

0.83 x V

ref

FB1

V UVComp

OUT1

Power

Sequence

Logic

ENA_1

ENA_2

IN1

10kW

SENSE1

(seeNoteA)

V (2Pins)

OUT1

SENSE2

(seeNoteA)

10kW

0.95xV

ref

FB1

RisingEdge

Deglitch

PG Comp

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TPS70145, TPS70148 TPS70151, TPS70158

TPS70102

SLVS222I –DECEMBER 1999–REVISED AUGUST 2010

DEVICE INFORMATION

Fixed Voltage Version

A. For most applications, V

SENSE1

and V

should be externally connected to V

SENSE2

as close as possible to the

OUT

device. For other implementations, refer to SENSE terminal connection discussion in the Application Information section.

B. If the SEQ terminal is floating at the input, V

powers up first.

OUT2

UVLO Comp

Thermal

Shutdown

2.5V

Current

Sense

Reference

ref

ENA_1

120ms

Delay

0.95xV

ref

FB1

0.95xV

ref

FB2

RisingEdge

Deglitch

Current

Sense

ENA_2

ref

IN1

(2Pins)

GND

IN2

(2Pins)

SEQ

(seeNoteB)

FB1

(seeNoteA)

PG1

MR2

RESET

FB2

(seeNoteA)

IN1

MR1

IN1

PG Comp

RisingEdge

Deglitch

Reset Comp

OUT1

(2Pins)

OUT2

(2Pins)

FallingEdge

Deglitch

0.83 x V

ref

FB2

V UVComp

OUT2

FallingEdge

Deglitch

0.83 x V

ref

FB1

V UVComp

OUT1

Power

Sequence

Logic

ENA_1

ENA_2

IN1

TPS70145, TPS70148 TPS70151, TPS70158 TPS70102

SLVS222I –DECEMBER 1999–REVISED AUGUST 2010

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Adjustable Voltage Version

A. For most applications, FB1 and FB2 should be externally connected to resistor dividers as close as possible to the

device. For other implementations, refer to FB terminals connection discussion in the Application Information section.

B. If the SEQ terminal is floating at the input, V

powers up first

OUT2

NOTES: A. V

RES

is the minimum input voltage for a valid RESET. The symbol V

RES

is not currently listed within EIA or JEDEC standards

for semiconductor symbology .

IN2

RES

(see Note A)

RES

OUT2

Threshold

Voltage

RESET Output

120 ms Delay

Output Undefined

Output

Undefined

IT+

(see Note B)

IT−

(see Note B)

IT+

(see Note B)

B. VIT −Trip voltage is typically 5% lower than the output voltage (95%VO) V

IT−

to V

IT+

is the hysteresis voltage.

IT−

(see Note B)

NOTES: A. V

PG1

is the minimum input voltage for a valid PG1. The symbol V

PG1

is not currently listed within EIA or JEDEC

standards for semiconductor symbology.

PG1

Threshold

Voltage

PG1

Output

Output Undefined

Output

Undefined

IT+

(see Note B)V

IT+

(see Note B)

B. VIT −Trip voltage is typically 5% lower than the output voltage (95%VO) V

IT−

to V

IT+

is the hysteresis voltage.

IN1

OUT2

PG1

(see Note A)

IT−

(see Note B)

IT−

(see Note B)

UVLO

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TPS70145, TPS70148 TPS70151, TPS70158

TPS70102

SLVS222I –DECEMBER 1999–REVISED AUGUST 2010

RESET Timing Diagram (with V

Powered Up)

IN1

PG1 Timing Diagram

TPS70145, TPS70148 TPS70151, TPS70158 TPS70102

SLVS222I –DECEMBER 1999–REVISED AUGUST 2010

Table 1. TERMINAL FUNCTIONS

TERMINAL

NAME NO.

EN 6 I Active low enable GND 8 — Ground MR1 4 I Manual reset input 1, active low, pulled up internally MR2 5 I Manual reset input 2, active low, pulled up internally NC 1, 11, 20 — No connection

PG1 16 O RESET 15 O Open drain output, SVS (power-on reset) signal, active low SEQ 7 I V

IN1

IN2

OUT1

OUT2

/FB2 14 I Regulator 2 output voltage sense/regulator 2 feedback for adjustable

SENSE2

/FB1 17 I Regulator 1 output voltage sense/regulator 1 feedback for adjustable

SENSE1

2, 3 I Input voltage of regulator 1

9, 10 I Input voltage of regulator 2 18, 19 O Output voltage of regulator 1 12, 13 O Output voltage of regulator 2

I/O DESCRIPTION

Open drain output, low when V voltage

Power-up sequence control: SEQ = High, V SEQ = Low, V

voltage is less than 95% of the nominal regulated

OUT1

powers up first;

powers up first, SEQ terminal pulled up internally.

OUT1

OUT2

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Detailed Description

The TPS701xx low dropout regulator family provides dual regulated output voltages for DSP applications that require high-performance power management solutions. These devices provide fast transient response and high accuracy with small output capacitors, while drawing low quiescent current. Programmable sequencing provides a power solution for DSPs without any external component requirements. This architecture reduces the component cost and board space while increasing total system reliability. The TPS701xx family has an enable feature that puts the device in sleep mode reducing the input currents to less than 3mA. Other features are integrated SVS (Power-On Reset, RESET) and Power Good (PG1) that monitor output voltages and provide logic output to the system. These differentiated features provide a complete DSP power solution.

The TPS701xx, unlike many other LDOs, feature very low quiescent current that remains virtually constant even with varying loads. Conventional LDO regulators use a pnp pass element, the base current of which is directly proportional to the load current through the regulator (IB= IC/b). The TPS701xx uses a PMOS transistor to pass current; because the gate of the PMOS is voltage=driven, operating current is low and stable over the full load range.

Pin Functions

Enable

The EN terminal is an input that enables or shuts down the device. If EN is at a voltage high signal, the device is in shutdown mode. When EN goes to voltage low, the device is enabled.

Sequence

The SEQ terminal is an input that programs which output voltage (V device is enabled and the SEQ terminal is pulled high or left open, V V

reaches approximately 83% of its regulated output voltage. At that time, V

OUT2

pulled below 83% (for example, in an overload condition) V current to V

IN1

is turned off. These terminals have a 6-mA pullup

OUT1

Pulling the SEQ terminal low reverses the power-up order and V diagrams, refer to Figure 40 through Figure 44.

or V

OUT1

turns on first and V

OUT2

is turned on first. For detailed timing

OUT1

) is turned on first. When the

OUT2

is turned on. If V

OUT1

remains off until

OUT1

OUT2

TPS70145, TPS70148 TPS70151, TPS70158

TPS70102

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Power-Good

The PG1 is an open drain, active high output terminal that indicates the status of the V V

reaches 95% of its regulated voltage, PG1 will go to a high impedance state. It will go to a low impedance

OUT1

state when it is pulled below 95% (for example, during an overload condition) of its regulated voltage. The open drain output of the PG1 terminal requires a pull-up resistor.

Manual Reset Pins (MR1 and MR2)

MR1 and MR2 are active low input terminals used to trigger a reset condition. When either MR1 or MR2 is pulled to logic low, a POR (RESET) will occur. These terminals have a 6mA pull-up current to V

SLVS222I –DECEMBER 1999–REVISED AUGUST 2010

regulator. When the

OUT1

IN1

Sense (V

SENSE1

, V

SENSE2

)

The sense terminals of fixed-output options must be connected to the regulator output, and the connection should be as short as possible. Internally, sense connects to high-impedance, wide-bandwidth amplifiers through a resistor-divider network and noise pickup feeds through to the regulator output. It is essential to route the sense connection in such a way to minimize or avoid noise pickup. Adding RC networks between the V terminals and V

terminals to filter noise is not recommended because these networks can cause the

OUT

SENSE

regulators to oscillate.

FB1 and FB2

FB1 and FB2 are input terminals used for adjustable-output devices and must be connected to the external feedback resistor divider. FB1 and FB2 connections should be as short as possible. It is essential to route them in such a way as to minimize or avoid noise pickup. Adding RC networks between the FB terminals and V

OUT

terminals to filter noise is not recommended because these networks cause the regulators to oscillate.

RESET Indicator

The TPS701xx features a RESET (SVS, POR, or Power-On Reset). RESET can be used to drive power-on reset circuitry or a low-battery indicator. RESET is an active low, open drain output that indicates the status of the V

regulator and both manual reset pins (MR1 and MR2). When V

OUT2

exceeds 95% of its regulated voltage,

OUT2

and MR1 and MR2 are in the high impedance state, RESET will go to a high-impedance state after 120ms delay. RESET will go to a low-impedance state when V its regulated voltage. To monitor V

, the PG1 output pin can be connected to MR1 or MR2. The open drain

OUT1

is pulled below 95% (for example, an overload condition) of

OUT2

output of the RESET terminal requires a pullup resistor. If RESET is not used, it can be left floating.

and V

IN1

and V

IN2

are input to the regulators. Internal bias voltages are powered by V

IN2

IN1

and V

OUT1

and V

OUT2

are output terminals of the LDO.

OUT2

IO − Output Current − A

3.296

3.295

3.293

3.292 0 0.1 0.2 0.3

− Output Voltage − V

3.298

3.299

3.300

0.4 0.5 0.6

3.297

3.294

IN1

= 4.3 V TA = 25°C VOUT1

1.799

1.797

1.796

1.795 0 0.05 0.1 0.15

1.800

1.801

1.802

0.2 0.25 0.3

1.798

IO − Output Current − A

− Output Voltage − VV O

IN2

= 2.8V TA = 25°C VOUT2

TPS70145, TPS70148 TPS70151, TPS70158 TPS70102

SLVS222I –DECEMBER 1999–REVISED AUGUST 2010

TYPICAL CHARACTERISTICS

Table 2. Table of Graphs

PSRR Power-supply rejection ratio vs Frequency Figure 9 to Figure 12

Output voltage

Ground current vs Junction temperature Figure 8

Output spectral noise density vs Frequency Figure 13 to Figure 16 Output impedance vs Frequency Figure 17 to Figure 20

Dropout voltage

Load transient response Figure 25 and Figure 26 Line transient response Figure 27 and Figure 28 Output voltage and enable voltage vs Time (start-up) Figure 29 and Figure 30 Equivalent series resistance vs Output current Figure 31 to Figure 38 Test circuit for typical regions of stability (equivalent series resistance) performance Figure 39

vs Output current Figure 1 to Figure 3 vs Temperature Figure 4 to Figure 7

vs Temperature Figure 21 and Figure 22 vs Input voltage Figure 23 and Figure 24

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FIGURE

TPS70151 TPS70151

OUTPUT VOLTAGE OUTPUT VOLTAGE

vs vs

OUTPUT CURRENT OUTPUT CURRENT

Figure 1. Figure 2.

T − Temperature − °C

3.268

3.270

3.272

3.274

3.276

3.278

3.280

3.282

3.284

3.286

− Output Voltage − VV O

−40 −25 −10 5 20 35 50 65 80 95 110 125

IN1

= 4.3 V IO = 1 mA VOUT1

1.198

1.197

1.196

1.195 0 0.05 0.1 0.15

1.199

1.200

1.201

0.2 0.25 0.3

IO − Output Current − A

− Output Voltage − VV O

IN2

= 2.7 V

= 25°C

VOUT2

3.270

3.272

3.274

3.276

3.278

3.280

3.282

3.284

3.286

3.288

T − Temperature − °C

− Output Voltage − VV O

−40 −25 −10 5 20 35 50 65 80 95 110 125

IN1

= 4.3 V IO = 500 mA VOUT1

1.786

1.788

1.790

1.792

1.794

1.796

1.798

1.800

T − Temperature − °C

− Output Voltage − VV O

−40 −25 −10 5 20 35 50 65 80 95 110 125

IN2

= 2.8 V IO = 1 mA VOUT2

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TPS70145, TPS70148 TPS70151, TPS70158

TPS70102

SLVS222I –DECEMBER 1999–REVISED AUGUST 2010

TPS70145 TPS70151

OUTPUT VOLTAGE OUTPUT VOLTAGE

vs vs

OUTPUT CURRENT TEMPERATURE

Figure 3. Figure 4.

TPS70151 TPS70151

OUTPUT VOLTAGE OUTPUT VOLTAGE

vs vs

TEMPERATURE TEMPERATURE

Figure 5. Figure 6.

+ 29 hidden pages

Texas Instruments TPS70145, TPS70148, TPS70151, TPS70158, TPS70102 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

DESCRIPTION

ABSOLUTE MAXIMUM RATINGS

THERMAL INFORMATION

RECOMMENDED OPERATING CONDITIONS

ELECTRICAL CHARACTERISTICS

DEVICE INFORMATION

Detailed Description

Pin Functions

Enable

Sequence

Power-Good

Manual Reset Pins (MR1 and MR2)

FB1 and FB2

RESET Indicator

TYPICAL CHARACTERISTICS