Texas Instruments TPS70158PWPR, TPS70158PWP, TPS70151PWPR, TPS70151EVM-152, TPS70151PWP Datasheet
...
TPS70145, TPS70148, TPS70151, TPS70158, TPS70102
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS222A – DECEMBER 1999 – REVISED MARCH 2000
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Dual Output Voltages for Split-Supply
Applications
D
Selectable Power Up Sequencing for DSP
Applications
D
Output Current Range of 500 mA on
Regulator 1 and 250 mA on Regulator 2
D
Fast Transient Response
D
Voltage Options are 3.3-V/2.5-V, 3.3-V/1.8-V,
3.3-V/1.5-V, 3.3-V/1.2-V, and Dual Adjustable
Outputs
D
Open Drain Power-On Reset With 120-ms
Delay
D
Open Drain Power Good for Regulator 1
D
Ultra Low 190 µA (typ) Quiescent Current
D
1 µA Input Current During Standby
D
Low Noise: 65 µV
RMS
Without Bypass
Capacitor
D
Quick Output Capacitor Discharge Feature
D
Two Manual Reset Inputs
D
2% Accuracy Over Load and Temperature
D
Undervoltage Lockout (UVLO) Feature
D
20-Pin PowerP AD TSSOP Package
D
Thermal Shutdown Protection
description
TPS701xx family devices are designed to provide
a complete power management solution for DSP,
processor power, ASIC, FPGA, and digital
applications where dual output voltage regulators
are required. Easy programmability of the
sequencing function makes this family ideal for
any DSP applications with power sequencing
requirement. Differentiated features, such as
accuracy, fast transient response, SVS supervisory circuit, manual reset inputs, and enable
function, provide a complete system solution.
1.8 V
V
IN1
V
IN2
EN
SEQ
V
OUT1
V
SENSE1
PG1
MR2
RESET
MR1
V
SENSE2
V
OUT2
TPS70151 PWP
5 V
3.3 V
I/O
MR1
Core
0.1 µF
RESET
10 µF
10 µF
0.1 µF
DSP
MR2
PG1
EN
250 kΩ
>2 V
<0.7 V
250 kΩ
>2 V
<0.7 V
>2 V
<0.7 V
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments Incorporated.
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2
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10
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15
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12
11
PWP PACKAGE
(TOP VIEW)
NC
V
IN1
V
IN1
MR1
MR2
EN
SEQ
GND
V
IN2
V
IN2
NC
V
OUT1
V
OUT1
V
SENSE1
/FB1
PG1
RESET
V
SENSE2
/FB2
V
OUT2
V
OUT2
NC
Copyright 2000, Texas Instruments Incorporated
TPS70145, TPS70148, TPS70151, TPS70158, TPS70102
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS222A – DECEMBER 1999 – REVISED MARCH 2000
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
The TPS701xx family of voltage regulators offers very low dropout voltage and dual outputs with power up
sequence control, which is designed primarily for DSP applications. These devices have extremely low noise
output performance without using any added filter bypass capacitors and are designed to have a fast transient
response and be stable with 10 uF low ESR capacitors.
These devices have fixed 3.3-V/2.5-V , 3.3-V/1.8-V , 3.3-V/1.5-V , 3.3-V/1.2-V, and adjustable/adjustable voltage
options. The 3.3-V output regulator (regulator 1) can support up to 500 mA, and the other regulator (regulator
2) can support up to 250 mA. Separate voltage inputs allow the designer to configure the source power.
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 170 mV
on regulator 1) and is directly proportional to the output current. Additionally , since the PMOS pass element is
a voltage-driven device, the quiescent current is very low and independent of output loading (maximum of
225 µA over the full range of output current). This LDO family also features a sleep mode; applying a high signal
to EN
(enable) shuts down both regulators, reducing the input current to 1 µA at TJ = 25°C.
The device is enabled when the EN pin is connected to a low-level input voltage. The output voltages of the two
regulators are sensed at the V
SENSE1
and V
SENSE2
pins respectively . The input signal at the SEQ pin controls
the power-up sequence of the two regulators. When the device is enabled and the SEQ terminal is pulled high
or left open, V
OUT2
will turn on first and V
OUT1
will remain off until V
OUT2
reaches approximately 83% of it’s
regulated output voltage. At that time V
OUT1
will be turned on. If V
OUT2
is pulled below 83% (i.e. over load
condition) V
OUT1
will be turned off. Pulling the SEQ terminal low , reverses the power-up order and V
OUT1
will
be turned on first. The SEQ pin is connected to an internal pullup current source.
For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator
is turned off(disabled).
The PG1 pin reports the voltage conditions at the VOUT1, which can be used to implement a SVS (power on
reset) for the circuitry supplied by regulator 1.
The TPS701xx features a RESET (SVS, POR, or Power On Reset). RESET output initiates a reset in DSP
systems in the event of an undervoltage condition. RESET indicates the status of the V
OUT2
and both manual
reset pins (MR1 and MR2). When V
OUT2
reaches 95% of it’s regulated voltage and MR1 and MR2 are in the
logic high state, RESET will go to a high impedance state after 120 ms delay . RESET will go to logic low state
when V
OUT2
regulated output voltage is pulled below 95% (i.e. over load condition) of it’s regulated voltage. T o
monitor V
OUT1
, the PG1 output pin can be connected to MR1 or MR2.
The device has an undervoltage lockout UVLO circuit which prevents the internal regulators from turning on until
VIN1 reaches 2.5V.
AVAILABLE OPTIONS
T
J
REGULATOR 1
VO (V)
REGULATOR 2
VO (V)
TSSOP
(PWP)
3.3 V 1.2 V TPS70145PWP
3.3 V 1.5 V TPS70148PWP
°
°
3.3 V 1.8 V TPS70151PWP
–
40°C to 125°C
3.3 V 2.5 V TPS70158PWP
Adjustable
(1.22 V to 5.5 V)
Adjustable
(1.22 V to 5.5 V)
TPS70102PWP
NOTE: The TPS70102 is programmable using external resistor dividers (see
application information) The PWP package is available taped and reeled. Add
an R suffix to the device type (e.g., TPS70102PWPR).
TPS70145, TPS70148, TPS70151, TPS70158, TPS70102
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS222A – DECEMBER 1999 – REVISED MARCH 2000
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
detailed block diagram – fixed voltage version
UVLO
Thermal
Shutdown
Shutdown
V_UVLO
+–
Current
Sense
Reference
VREF
VREF
ENA_1
ENA_1
10 kΩ
Rising Edge
Deglitch
0.95 × VREP
FB2
Falling Edge
Delay
V
IN1
PG1 Comp
0.95 × VREF
FB1
Rising Edge
Deglitch
Falling Edge
Deglitch
0.83 × VREF
FB2
UV Comp
Falling Edge
Deglitch
0.83 × VREF
FB1
UV Comp
Power
Sequence
Logic
SHUTDOWN
ENA_!
ENA_2
V
CC
Current
Sense
+–
10 kΩ
ENA_2
ENA_2
FB2
VREF
VIN1 (2 Pins)
GND
EN
SEQ
(see Note B)
VIN2 (2 Pins)
VOUT1 (2 Pin)
VSENSE1
(see Note A)
PG1
MR2
RESET
MR1
VSENSE2
(see Note A)
VOUT2(2 Pin)
FB1
V
CC
NOTES: A. For most applications, V
SENSE1
and V
SENSE2
should be externally connected to V
OUT
as close as possible to the device.
For other implementations, refer to SENSE terminal connection discussion in Application information section.
B. If the SEQ terminal is floating at the input, the V
OUT2
will power-up first.
TPS70145, TPS70148, TPS70151, TPS70158, TPS70102
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS222A – DECEMBER 1999 – REVISED MARCH 2000
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
detailed block diagram – adjustable voltage version
UVLO
Thermal
Shutdown
Shutdown
2.5 V
+–
Current
Sense
Reference
VREF
VREF
ENA_1
ENA_1
Rising Edge
Deglitch
0.95 × VREP
FB2
Falling Edge
Delay
V
IN1
PG1 Comp
0.95 × VREF
FB1
Rising Edge
Deglitch
Falling Edge
Deglitch
0.83 × VREF
FB2
UV Comp
Falling Edge
Deglitch
0.83 × VREF
FB1
UV Comp
Power
Sequence
Logic
SHUTDOWN
ENA_!
ENA_2
V
CC
Current
Sense
+–
ENA_2
ENA_2
VREF
VIN1 (2 Pins)
GND
EN
SEQ
(see Note B)
VIN2 (2 Pins)
VOUT1 (2 Pin)
FB1
(see Note A)
PG1
MR2
RESET
MR1
FB2
(see Note A)
VOUT2 (2 Pin)
V
CC
NOTES: A. For most applications, FB1 and FB2 should be externally connected to resistor dividers as close as possible to the device.
For other implementations, refer to FB terminals connection discussion in Application information section.
B. If the SEQ terminal is floating at the input, the V
OUT2
will power-up first.
TPS70145, TPS70148, TPS70151, TPS70158, TPS70102
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS222A – DECEMBER 1999 – REVISED MARCH 2000
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
RESET timing diagram
NOTES: A. V
res
is the minimum input voltage for a valid RESET . The symbol V
res
is not currently listed within EIA or JEDEC standards
for semiconductor symbology.
V
IN1 and
V
IN2
V
res
(see Note A)
V
res
t
t
t
V
OUT2
Threshold
Voltage
RESET
Output
120 ms
Delay
120 ms
Delay
Output
Undefined
Output
Undefined
V
IT+
(see Note B)
V
IT–
(see Note B)
V
IT+
(see Note B)
B. VIT –Trip voltage is typically 5% lower than the output voltage (95%VO) V
IT–
to V
IT+
is the hysteresis voltage.
V
IT–
(see Note B)
PG timing diagram
NOTES: A. V
res
is the minimum input voltage for a valid PG. The symbol V
res
is not currently listed within EIA or JEDEC
standards for semiconductor symbology.
V
res
t
t
t
Threshold
Voltage
PG
Output
Output
Undefined
Output
Undefined
V
IT+
(see Note B)V
IT+
(see Note B)
B. VIT –Trip voltage is typically 5% lower than the output voltage (95%VO) V
IT–
to V
IT+
is the hysteresis
V
IN1 and
V
IN2
V
OUT2
V
res
(see Note A)
V
IT–
(see Note B)
V
IT–
(see Note B)
TPS70145, TPS70148, TPS70151, TPS70158, TPS70102
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS222A – DECEMBER 1999 – REVISED MARCH 2000
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
EN 6 I Active low enable
GND 8 Ground
MR1 4 I Manual reset input 1, active low, pulled up internally
MR2 5 I Manual reset input 2, active low, pulled up internally
NC 1, 11, 20 No connection
PG1 16 O Open drain output, low when V
OUT1
voltage is less than 55 of the nominal regulated voltage
RESET 15 O Open drain output, SVS (power on reset) signal, active low
SEQ 7 I Power up sequence control: SEQ=High, V
OUT2
powers up first; SEQ=Low, V
OUT1
powers up first, SEQ
terminal pulled up internally .
V
IN1
2, 3 I Input voltage of regulator 1
V
IN2
9, 10 I Input voltage of regulator 2
V
OUT1
18, 19 O Output voltage of regulator 1
V
OUT2
12, 13 O Output voltage of regulator 2
V
SENSE2
/FB2 14 I Regulator 2 output voltage sense/ regulator 2 feedback for adjustable
V
SENSE1
/FB1 17 I Regulator 1 output voltage sense/ regulator 2 feedback for adjustable
absolute maximum ratings over operating junction temperature (unless otherwise noted)
†
Input voltage range‡:V
IN1
–0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V
IN2
–0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range at EN –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range (V
OUT1
, V
SENSE1
) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range (V
OUT2
, V
SENSE2
) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum RESET
, PG1 voltage 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum MR1, MR2, and SEQ voltage V
IN1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peak output current Internally limited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature range, TJ –40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ESD rating, HBM 2 kV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡
All voltages are tied to network ground.
DISSIPATION RATING TABLE
PACKAGE
AIR FLOW
(CFM)
TA ≤ 25°C
DERATING FACTOR TA = 70°C TA = 85°C
0
3.067 W
30.67 mW/°C
1.687 W
1.227 W
PWP
§
250 4.115 W
41.15 mW/°C 2.265 W 1.646 W
§
This parameter is measured with the recommended copper heat sink pattern on a 4-layer PCB, 1 oz. copper on 4-in × 4-in
ground layer. For more information, refer to TI technical brief SLMA002.
TPS70145, TPS70148, TPS70151, TPS70158, TPS70102
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS222A – DECEMBER 1999 – REVISED MARCH 2000
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions
MIN MAX UNIT
Input voltage, V
I
†
2.7 6 V
Output current, IO (regulator 1) 0 500 mA
Output current, IO (regulator 2) 0 250 mA
Output voltage range (for adjustable option) 1.22 5.5 V
Operating virtual junction temperature, T
J
–40 125 °C
†
To calculate the minimum input voltage for maximum output current, use the following equation: V
I(min)
= V
O(max)
+ V
DO(max load)
.
electrical characteristics over recommended operating junction temperature (TJ = –40°C to 125°C)
V
I
= V
O(nom)
+ 1 V, IO = 1 mA, EN = 0, CO = 33 µF(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Adjustable
1.22 V ≤ VO ≤ 5.5 V, 2.7 V < VIN < 6 V,
FB connected to V
O
V
O
j
voltage
1.22 V ≤ VO ≤ 5.5 V, 2.7 V < VIN < 6 V,
FB connected to V
O
0.98 V
O
1.02 V
O
p
2.7 V < VIN < 6 V, TJ = 25°C 1.2
1.2 V Output
2.7 V < VIN < 6 V 1.176 1.224
p
p
2.7 V < VIN < 6 V, TJ = 25°C 1.5
V
O
Out ut voltage
(see Notes 1 and 3)
1.5 V Output
2.7 V < VIN < 6 V 1.47 1.53
()
p
2.8 V < VIN < 6 V, TJ = 25°C 1.8
V
1.8 V Output
2.8 V < VIN < 6 V 1.764 1.836
p
3.5 V < VIN < 6 V, TJ = 25°C 2.5
2.5 V Output
3.5 V < VIN < 6 V 2.45 2.55
p
4.3 V < VIN < 6 V, TJ = 25°C 3.3
3.3 V Output
4.3 V < VIN < 6 V 3.234 3.366
V
Quiescent current (GND current) for regulator 1 and
See Note 3, TJ = 25°C 190
()g
regulator 2, EN = 0 V, (see Note 1)
See Note 3 230
µA
Output voltage line regulation (∆V/V) for
VO + 1 V < VI ≤ 6 V, TJ = 25°C, (see Note 1) 0.01%
gg(
OO
)
regulator 1 and regulator 2 (see Note 2)
VO + 1 V < VI ≤ 6 V, (see Note 1) 0.1%
V
Load regulation for V
OUT1
and V
OUT2
TJ = 25°C 1 mV
p
Regulator 1
°
65
VnOutput noise voltage
Regulator 2
BW
=
300 Hz to 50 kHz
,
C
O
=
33 µF
,
T
J
=
25°C
65
µVrms
p
Regulator 1
1.6 1.9
Output current limit
Regulator 2
V
O
=
0 V
I
0.750 1
A
Thermal shutdown junction temperature TJ = 25°C 150 °C
EN = VI,T
J
= 25°C 1
Regulator 1
EN = V
I
3
µA
I
I(standby)
Standby current
EN = VI,T
J
= 25°C 1
Regulator 2
EN = V
I
3
µA
PSRR Power supply ripple rejection f = 1 kHz, CO = 33 µF, TJ = 25°C, (see Note 1) 60 dB
NOTES: 1. Minimum input operating voltage is 2.7 V or V
O(typ)
+ 1 V, whichever is greater . Maximum input voltage = 6 V , minimum output current
1 mA.
2. If VO < 1.8 V then V
imax
= 6 V, V
imin
= 2.7 V:
Line Regulation (mV)
+ǒ%ńVǓ
V
O
ǒ
V
imax
*
2.7 V
Ǔ
100
1000
If VO > 2.5 V then V
imax
= 6 V, V
imin
= Vo + 1 V :
Line Regulation (mV)
+ǒ%ńVǓ
V
O
ǒ
V
imax
*ǒVO)
1
Ǔ
Ǔ
100
1000
3. IO = 1 mA to 500 mA for Regulator 1 and 1 mA to 250 mA for Regulator 2.
TPS70145, TPS70148, TPS70151, TPS70158, TPS70102
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS222A – DECEMBER 1999 – REVISED MARCH 2000
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating junction temperature (TJ = –40°C to 125°C)
V
I
= V
O(nom)
+ 1 V, IO = 1 mA, EN = 0, CO = 33 µF(unless otherwise noted) (continued)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Minimum input voltage for valid RESET I
(RESET)
= 300 µA, V
(RESET)
≤ 0.8 V 1.0 1.3 V
Trip threshold voltage VO decreasing 92% 98% V
O
Hysteresis voltage Measured at V
O
0.5% V
O
RESET
t
(RESET
)
RESET pulse duration 80 120 160 ms
t
r(RESET)
Rising edge deglitch 30 µs
Output low voltage VI = 3.5 V, I
O(RESET)
= 1 mA 0.15 0.4 V
Leakage current V
(RESET)
= 6 V 1 µA
Minimum input voltage for valid PG I
O(PG)
= 300 µA, V
(PG1
) ≤ 0.8 V 1.0 1.3 V
Trip threshold voltage VO decreasing 92% 98% V
O
Hysteresis voltage Measured at V
O
0.5% V
O
PG
t
r(PG1)
Rising edge deglitch 30 µs
Output low voltage VI = 2.7 V, I
O(PG)
= 1 mA 0.15 0.4 V
Leakage current V
(PG1)
= 6 V 1 µA
High level EN input voltage 2 V
Low level EN input voltage 0.7 V
EN
Input current (EN) –1 1 µA
Falling Edge deglitch Measured at V
O
140 µs
High level SEQ input voltage 2 V
Low level SEQ input voltage 0.7 V
SEQ
Falling edge deglitch Measured at V
O
140 µs
SEQ pull up current source 6 µA
High level input voltage 2 V
Low level input voltage 0.7 V
MR1 / MR2
Falling edge deglitch Measured at V
O
140 µs
Pull up current source 6 µA
V
OUT2
UV comparator – positive-going input
threshold voltage of V
OUT1
UV comparator
80% VO83% VO86% V
O
V
V
OUT2
UV comparator – hysteresis 0.5% V
O
mV
V
OUT2
V
OUT2
UV comparator – falling edge deglitch V
SENSE_2
decreasing below threshold 140 µs
Peak output current 2 ms pulse width 375 mA
Discharge transistor current V
OUT2
= 1.5 V 7.5 mA
V
OUT1
UV comparator – positive-going input
threshold voltage of V
OUT1
UV comparator
80% VO83% VO86% V
O
V
V
OUT1
UV comparator – hysteresis 0.5% V
O
mV
V
OUT1
UV comparator – falling edge deglitch V
SENSE_1
decreasing below threshold 140 µs
V
OUT1
IO = 500 mA, V
IN1
= 3.2 V 170
D
ropout voltage (see Note
4)
IO = 500 mA, V
IN1
= 3.2 V 275
m
V
Peak output current 2 ms pulse width 750 mA
Discharge transistor current V
OUT1
= 1.5 V 7.5 mA
VOUT1 UVLO UVLO threshold 2.4 2.65 V
FB Input current – TPS70102 FB = 1.8 V 2 nA
NOTE 4: Input voltage(V
IN1
or V
IN2
) = VO(Typ) – 100 mV . 1.5 V , 1.8 V and 2.5 V regulators, the dropout voltage is limited by input voltage range.
The 3.3 V regulator input voltage is to 3.2 V to perform this test.
TPS70145, TPS70148, TPS70151, TPS70158, TPS70102
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS222A – DECEMBER 1999 – REVISED MARCH 2000
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Table of Graphs
FIGURE
p
vs Output current 1 – 3
VOOutput voltage
vs Temperature 4 – 7
Ground current vs Temperature 8, 9
PSRR Power supply rejection ratio vs Frequency 10 – 13
Output spectral noise density vs Frequency 14 – 17
Z
o
Output impedance vs Frequency 18 – 21
p
vs Temperature 22, 23
Dropout voltage
vs Input voltage 24, 25
Load transient response 26, 27
Line transient response 28, 29
Output voltage vs. Time (start-up) 30, 31
Stability Equivalent series resistance (ESR) vs Output current 33 – 36
TYPICAL CHARACTERISTICS
Figure 1
IO – Output Current – A
3.296
3.295
3.293
3.292
0 0.1 0.2 0.3
– Output Voltage – V
3.298
3.299
TPS70151
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
3.300
0.4 0.5 0.6
3.297
3.294
V
O
V
IN1
= 4.3 V
TA = 25°C
V
OUT1
Figure 2
1.799
1.797
1.796
1.795
0 0.05 0.1 0.15
1.800
1.801
1.802
0.2 0.25 0.3
1.798
IO – Output Current – A
– Output Voltage – V
TPS70151
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
V
O
V
IN2
= 2.8V
TA = 25°C
V
OUT2
TPS70145, TPS70148, TPS70151, TPS70158, TPS70102
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS222A – DECEMBER 1999 – REVISED MARCH 2000
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
1.198
1.197
1.196
1.195
0 0.05 0.1 0.15
1.199
1.200
1.201
0.2 0.25 0.3
IO – Output Current – A
– Output Voltage – V
TPS70145
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
V
O
V
IN2
= 2.7 V
TA = 25°C
V
OUT2
Figure 3
Figure 4
T – Temperature – °C
3.268
3.270
3.272
3.274
3.276
3.278
3.280
3.282
3.284
3.286
TPS70151
OUTPUT VOLTAGE
vs
TEMPERATURE
– Output Voltage – VV
O
–40 –25 –10 5 20 35 50 65 80 95 110 125
V
IN1
= 4.3 V
IO = 1 mA
V
OUT1
Figure 5
3.270
3.272
3.274
3.276
3.278
3.280
3.282
3.284
3.286
3.288
T – Temperature – °C
TPS70151
OUTPUT VOLTAGE
vs
TEMPERATURE
– Output Voltage – VV
O
–40 –25 –10 5 20 35 50 65 80 95 110 125
V
IN1
= 4.3 V
IO = 500 mA
V
OUT1
TPS70145, TPS70148, TPS70151, TPS70158, TPS70102
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS222A – DECEMBER 1999 – REVISED MARCH 2000
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 6
1.786
1.788
1.790
1.792
1.794
1.796
1.798
1.800
T – Temperature – °C
TPS70151
OUTPUT VOLTAGE
vs
TEMPERATURE
– Output Voltage – VV
O
–40 –25 –10 5 20 35 50 65 80 95 110 125
V
IN2
= 2.8 V
IO = 1 mA
V
OUT2
Figure 7
1.790
1.791
1.792
1.793
1.794
1.795
1.796
1.797
1.798
1.799
T – Temperature – °C
TPS70151
OUTPUT VOLTAGE
vs
TEMPERATURE
– Output Voltage – VV
O
–40 –25 –10 5 20 35 50 65 80 95 110 125
V
IN2
= 2.8 V
IO = 250 mA
V
OUT2
Figure 8
95
100
105
110
115
120
–40 –25 –10 5 20 35 50 65 80
T – Temperature – °C
95 110 125
125
130
135
GROUND CURRENT
vs
TEMPERATURE
IO = 500 mA
IO = 1 mA
Ground Current – Aµ
V
OUT1
Figure 9
50
52
54
56
58
60
–40 –25 –10 5 20 35 50 65 80
T – Temperature – °C
95 110 125
62
64
66
GROUND CURRENT
vs
TEMPERATURE
68
70
IO = 250 mA
IO = 1 mA
Ground Current – Aµ
V
OUT2