The purpose of the TPS65910 device is to
provide the following resources:
•Embedded power controller
•Two efficient step-down dc-dc converters for
processor cores
•One efficient step-down dc-dc converter for I/O
power
•One efficient step-up 5-V dc-dc converter
•SmartReflex™ compliant dynamic voltage
management for processor cores
•8 LDO voltage regulators and one RTC LDO
(internal purpose)
•One high-speed I2C interface for generalpurpose control commands (CTL-I2C)
•One high-speed I2C interface for SmartReflex
Class 3 control and command (SR-I2C)
•Two enable signals multiplexed with SR-I2C,
configurable to control any supply state and
processor cores supply voltage
•Thermal shutdown protection and hot-die
detection
•A real-time clock (RTC) resource with:
– Oscillator for 32.768-kHz crystal or 32-kHz
built-in RC oscillator
– Date, time and calendar
– Alarm capability
•One configurable GPIO
•DC-DC switching synchronization through
internal or external 3-MHz clock
TPS659107, TPS659108, TPS659109
APPLICATIONS
•Portable and handheld systems
•OMAP3 power management
DESCRIPTION
The TPS65910 is an integrated power-management
IC available in 48-QFN package and dedicated to
applications powered by one Li-Ion or Li-Ion polymer
battery cell or 3-series Ni-MH cells, or by a 5-V input;
it requires multiple power rails. The device provides
three step-down converters, one step-up converter,
and eight LDOs and is designed to support the
specificpowerrequirementsofOMAP-based
applications.
Two of the step-down converters provide power for
dual processor cores and are controllable by a
dedicated class-3 SmartReflex interface for optimum
power savings. The third converter provides power for
the I/Os and memory in the system.
The device includes eight general-purpose LDOs
providing a wide range of voltage and current
capabilities; they are fully controllable by the I2C
interface. The use of the LDOs is flexible; they are
intended to be used as follows: Two LDOs are
designated to power the PLL and video DAC supply
rails on the OMAP based processors, four generalpurpose auxiliary LDOs are available to provide
power to other devices in the system, and two LDOs
are provided to power DDR memory supplies in
applications requiring these memories.
In addition to the power resources, the device
contains an embedded power controller (EPC) to
manage the power sequencing requirements of the
OMAP systems and an (RTC).
Figure 1 shows the top-level diagram of the device.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
(1) The RSL package is available in tape and reel. See for details for corresponding part numbers, quantities and ordering information.
(2) Refer to SWCU093 document.
(1)
(2)
SWCS046T –MARCH 2010–REVISED SEPTEMBER 2013
Part Number
TPS65910A31A1RSL
(1)
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
Stresses beyond those listed under below may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated below are not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
The absolute maximum ratings for the TPS65910 device are listed below:
PARAMETERMINMAXUNIT
Voltage range on pins/balls VCC1, VCC2, VCCIO, VCC3, VCC4,
VCC5, VCC6, VCC7
Voltage range on pins/balls VDDIO–0.33.6V
Voltage range on pins/balls OSC32KIN, OSC32KOUT, BOOT1,
BOOT0
Voltage range on pins/balls SDA_SDI, SCL_SCK, SDASR_EN2,
SCLSR_EN1, SLEEP, INT1, CLK32KOUT, NRESPWRON
Voltage range on pins/balls PWRON–0.37V
Voltage range on pins/balls PWRHOLD
Functional junction temperature range–45150°C
Peak output current on all other terminals than power resources–55mA
(1) I/O supplied from VDDIO but which can be driven from to a VBAT voltage level
(2) I/O supplied from VRTC but can be driven to a VBAT voltage level
(1)
GPIO_CKSYNC
(2)
–0.37V
–0.3VRTC
–0.3VDDIO
–0.37V
+ 0.3V
MAX
+ 0.3V
MAX
THERMAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PackageR
RSL 48-QFN372.6371.481
θja
(°C/W)
TA < 25°C PowerFACTOR ABOVETA = 70°C PowerTA = 85°C Power
Rating (W)25 °C(W)Rating (W)
DERATING
(mW/°C)
The thermal resistance R
The value of thermal resistance R
over operating free-air temperature range (unless otherwise noted)
Lists of the recommended operating maximum ratings for the TPS65910 device are given below.
Note1: VCC7 should be connected to the highest supply that is connected to the device VCCx pin. The exception is that
VCC2 and VCC4 can be higher than VCC7.
Note2: VCC2 and VCC4 must be connected together (to the same voltage).
Note3: If VDD3 boost is used, VAUX33 must be set to 2.8 V or higher and enabled before VDD3.
PARAMETERTEST CONDITIONSMINNOMMAXUNIT
VCC: Input voltage range on pins/balls VCC1, VCC2, VCCIO, VCC3, VCC4, VCC5,
VCC7
V
: Input voltage range on pins/balls VCC61.73.65.5V
CCP
Input voltage range on pins/balls VDDIO1.651.8/3.33.45V
Input voltage range on pins/balls PWRON03.65.5V
Input voltage range on pins/balls SDA_SDI, SCL_SCK, SDASR_EN2, SCLSR_EN1,
SLEEP
Input voltage range on pins/balls PWRHOLD, GPIO_CKSYNC1.65VDDIO5.5V
Input voltage range on balls BOOT1, BOOT0, OSC32KIN1.65VRTC1.95V
Operating free-air temperature, T
Junction temperature T
J
A
Storage temperature range–6527150°C
Lead temperature (soldering, 10 s)260°C
Power References
VREF filtering capacitor C
O(VREF)
Connected from VREF to REFGND100nF
VDD1 SMPS
Input capacitor C
Filter capacitor C
I(VCC1)
O(VDD1)
X5R or X7R dielectric10µF
X5R or X7R dielectric41012µF
COfilter capacitor ESRf = 3 MHz10300mΩ
Inductor L
LOinductor dc resistor DCR
O(VDD1)
L
VDD2 SMPS
Input capacitor C
Filter capacitor C
I(VCC2)
O(VDD2)
X5R or X7R dielectric10µF
X5R or X7R dielectric41012µF
COfilter capacitor ESRf = 3 MHz10300mΩ
Inductor L
LOinductor dc resistor DCR
O(VDD2)
L
VIO SMPS
Input capacitor C
Filter capacitor C
I(VIO)
O(VIO)
X5R or X7R dielectric10µF
X5R or X7R dielectric41012µF
COfilter capacitor ESRf = 3 MHz10300mΩ
Inductor L
LOinductor dc resistor DCR
over operating free-air temperature range (unless otherwise noted)
Lists of the recommended operating maximum ratings for the TPS65910 device are given below.
Note1: VCC7 should be connected to the highest supply that is connected to the device VCCx pin. The exception is that
VCC2 and VCC4 can be higher than VCC7.
Note2: VCC2 and VCC4 must be connected together (to the same voltage).
Note3: If VDD3 boost is used, VAUX33 must be set to 2.8 V or higher and enabled before VDD3.
PARAMETERTEST CONDITIONSMINNOMMAXUNIT
COfiltering capacitor ESR0500mΩ
VDAC LDO
Filtering capacitor C
COfiltering capacitor ESR0500mΩ
Input capacitor C
Filtering capacitor C
COfiltering capacitor ESR0500mΩ
Filtering capacitor C
COfiltering capacitor ESR0500mΩ
Input capacitor C
Filtering capacitor C
COfiltering capacitor ESR0500mΩ
Filtering capacitor C
COfiltering capacitor ESR0500mΩ
Input capacitor C
Filtering capacitor C
COfiltering capacitor ESR0500mΩ
Input capacitor C
Filter capacitor C
COfilter capacitor ESRf = 1 MHz10300mΩ
Inductor L
over operating free-air temperature range (unless otherwise noted)
Lists of the recommended operating maximum ratings for the TPS65910 device are given below.
Note1: VCC7 should be connected to the highest supply that is connected to the device VCCx pin. The exception is that
VCC2 and VCC4 can be higher than VCC7.
Note2: VCC2 and VCC4 must be connected together (to the same voltage).
Note3: If VDD3 boost is used, VAUX33 must be set to 2.8 V or higher and enabled before VDD3.
PARAMETERTEST CONDITIONSMINNOMMAXUNIT
Max crystal series resistor@ Fundamental frequency90kΩ
Crystal load capacitorAccording to crystal data sheet612.5pF
Load crystal oscillator Coscin
,Coscout
Quality factor800080000
parallel mode Including parasitic PCB capacitor1225pF
ESD SPECIFICATIONS
over operating free-air temperature range (unless otherwise noted)
ESD METHODSTANDARD REFERENCEPERFORMANCE
Human body model (HBM)EIA/JESD22-A114D2000 V2000 V
Charge device model (CDM)EIA/JESD22-C101C500 V500 V
(1) The internal pullups on the CTL-I2C and SR-I2C balls are used for test purposes or when the SR-I2C interface is not used. Discrete
pullups to the VIO supply must be mounted on the board in order to use the I2C interfaces. The internal I2C pullups must not be used for
functional applications
over operating free-air temperature range (unless otherwise noted)
All current consumption measurements are relative to the FULL chip, all VCC inputs set to VBAT voltage.
over operating free-air temperature range (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
Input voltage V
DC output voltage (V
Rated output current I
N-channel MOSFETVIN= 3.6 V500mΩ
On-resistance R
N-channel MOSFET leakage
current I
N-channel MOSFET DC current
limit
Turn-on inrush currentVIN= V
Ripple voltage20mV
DC load regulationOn mode, I
DC line regulationOn mode, VIN= V
Turn-on timeI
Overshoot3%
Switching frequency1MHz
VFB3 internal resistance088MΩ
Ground current (IQ)Off1
over operating free-air temperature range (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
VIN= 2.5 V, I
DC load regulationOn mode, I
DC line regulationOn mode, VIN= V
Transient load regulation9mV
On mode, VIN= 3.8 V, I
I
in 5 µs
OUTmax
And I
OUT
Transient line regulationOn mode, VIN= V
And VIN= V
I
/2
OUTmax
Turn-on timeI
OUT
= 0, @ V
Turn-on inrush current300mA
VIN= V
Ripple rejection
I
OUTmax
INDC
/2
f = 217 Hz70
f = 50 kHz40
VPLL internal resistanceLDO off535kΩ
Ground currentOn mode, I
On mode, I
Low-power mode12
Off mode1
= I
OUT
= I
OUT
INmin
= 0.9 × I
OUTmax
INmin
to V
INmin
OUT
+ 100 mVpptone, V
= 060
OUT
= I
OUT
, T = 25°C
OUTmax
to 010mV
OUTmax
to V
OUT
+ 0.5 V to V
INmin
= 0.1 V up to V
OUTmax
@ I
INmax
to 0.1 × I
= 0.1 × I
OUT
OUTmax
OUTmax
in 30 µs0.5mV
INmin
+ 0.5 V in 30 µs, I
OUTmin
= 3.8 V, I
INDC+
= I
OUTmax
to 0.9 ×
in 5 µs
OUT
SWCS046T –MARCH 2010–REVISED SEPTEMBER 2013
1mV
=
100µs
=
OUT
1600
dB
µA
SWITCH-ON/-OFF SEQUENCES AND TIMING
Time slot length can be selected to be 0.5 ms or 2 ms through the EEPROM for an OFF-to-ACTIVE transition or
through the value programmed in the register DEVCTRL2_REG for a SLEEP-to-ACTIVE transition.
BOOT1 = 0, BOOT0 = 0
Table 2 provides details about the EEPROM setting for the BOOT modes. The power-up sequence for this boot
mode is provided in Figure 2.
Table 2. Fixed Boot Mode: 00
RegisterBitDescription
VDD1_OP_REGSELVDD1 voltage level selection for boot1.2 V
VDD1_REGVGAIN_SELVDD1 Gain selection, x1 or x2x1
EEPROMVDD1 time slot selection3
DCDCCTRL_REGVDD1_PSKIPVDD1 pulse skip mode enableskip enabled
VDD2_OP_REG/VDD2_SR_REGSELVDD2 voltage level selection for boot1.1 V
VDD2_REGVGAIN_SELVDD2 Gain selection, x1 or x3x3
EEPROMVDD2 time slot selection2
DCDCCTRL_REGVDD2_PSKIPVDD2 pulse skip mode enableskip enabled
VIO_REGSELVIO voltage selection1.8 V
EEPROMVIO time slot selection1
DCDCCTRL_REGVIO_PSKIPVIO pulse skip mode enableskip enabled
EEPROMVDD3 time slotOFF
VDIG1_REGSELLDO voltage selection1.2 V
EEPROMLDO time slotOFF
VDIG2_REGSELLDO voltage selection1.0 V
EEPROMLDO time slotOFF
VDAC_REGSELLDO voltage selection1.8 V
EEPROMLDO time slot5
VPLL_REGSELLDO voltage selection1.8 V
EEPROMLDO time slot4
VAUX1_REGSELLDO voltage selection1.8 V
EEPROMLDO time slot1
VMMC_REGSELLDO voltage selection3.3 V
EEPROMLDO time slot6
VAUX33_REGSELLDO voltage selection1.8 V
EEPROMLDO time slotOFF
VAUX2_REGSELLDO voltage selection1.8 V
EEPROMLDO time slot5
CLK32KOUT pinCLK32KOUT time slot7
NRESPWRON pinNRESPWRON time slot7 + 1
VRTC_REGLow-power mode
DEVCTRL_REGRTC_PWDN1
DEVCTRL_REGCK32K_CTRLRC
DEVCTRL2_REG0: 0.5 ms2 ms
DEVCTRL2_REGIT_POLActive-low
INT_MSK_REGVMBHI_IT_MSKswitch-on from
VMBCH_REGVMBCH_SEL[1:0]3 V
VRTC_OFFMAS
K
TSLOT_LENGTH
[0]
0: VRTC LDO will be in low-power mode during OFF state
1: VRC LDO will be in full-power mode during OFF state
0: RTC in normal power mode
1: Clock gating of RTC register and logic, low-power mode
0: Clock source is crystal/external clock
1: Clock source is internal RC oscillator
Boot sequence time slot duration:
1: 2 ms
0: INT1 signal will be active-low
1: INT1 signal will be active-high
0: Device will automatically switch-on at NOSUPPLY to
OFF or BACKUP to OFF transition
1: Startup reason required before switch-on
Select threshold for main battery comparator threshold
PWRHOLD rising edge to VIO, VAUX1 enable delay66 × t
VIO to VDD2 enable delay64 × t
VDD2 to VDD1 enable delay64 × t
VDD1 to VPLL enable delay64 × t
VPLL to VDAC,VAUX2 enable delay64 × t
VDAC to VMMC enable delay64 × t
VMMC to CLK32KOUT rising edge delay64 × t
CLK32KOUT to NRESPWRON rising edge delay64 × t
Total switch-on delay16ms
PWRHOLD falling edge to NRESPWRON falling edge
delay
2 × t
NRESPWRON falling edge to CLK32KOUT low delay3 × t
PWRHOLD falling edge to supplies and reference
disable delay
5 × t
= 2060µs
CK32k
= 2000µs
CK32k
= 2000µs
CK32k
= 2000µs
CK32k
= 2000µs
CK32k
= 2000µs
CK32k
= 2000µs
CK32k
= 2000µs
CK32k
= 62.5µs
CK32k
= 92µs
CK32k
= 154µs
CK32k
Registers default setting: CK32K_CTRL = 1 (32-kHz RC oscillator is used), RTC_PWDN = 1 (RTC domain off),
IT_POL = 0 (INt2 interrupt flag active low), VMBHI_IT_MSK = 0 (automatic switch-on on Battery plug),
VMBCH_SEL = 11.
BOOT1 = 0, BOOT0 = 1
Table 4 provides details about the EEPROM setting for the BOOT modes. The power-up sequence for this boot
VDD1_OP_REGSELVDD1 voltage level selection for boot1.2 V
VDD1_REGVGAIN_SELVDD1 Gain selection, x1 or x2x1
EEPROMVDD1 time slot selection3
DCDCCTRL_REGVDD1_PSKIPVDD1 pulse skip mode enableSkip enabled
VDD2_OP_REG/VDD2_SR_REGSELVDD2 voltage level selection for boot1.2 V
VDD2_REGVGAIN_SELVDD2 Gain selection, x1 or x3x1
EEPROMVDD2 time slot selection4
DCDCCTRL_REGVDD2_PSKIPVDD2 pulse skip mode enableSkip enabled
VIO_REGSELVIO voltage selection1.8 V
EEPROMVIO time slot selection1
DCDCCTRL_REGVIO_PSKIPVIO pulse skip mode enableSkip enabled
EEPROMVDD3 time slotOFF
VDIG1_REGSELLDO voltage selection1.2 V
EEPROMLDO time slotOFF
VDIG2_REGSELLDO voltage selection1.0 V
EEPROMLDO time slotOFF
VDAC_REGSELLDO voltage selection1.8 V
EEPROMLDO time slotOFF
VPLL_REGSELLDO voltage selection1.8 V
EEPROMLDO time slot2
VAUX1_REGSELLDO voltage selection1.8 V
EEPROMLDO time slotOFF
VMMC_REGSELLDO voltage selection1.8 V
EEPROMLDO time slotOFF
VAUX33_REGSELLDO voltage selection3.3 V
EEPROMLDO time slot6
VAUX2_REGSELLDO voltage selection1.8 V
EEPROMLDO time slot5
CLK32KOUT pinCLK32KOUT time slot7
NRESPWRON pinNRESPWRON time slot7+1
VRTC_REGlow-power mode
DEVCTRL_REGRTC_PWDN1
DEVCTRL_REGCK32K_CTRLCrystal
DEVCTRL2_REG0: 0.5 ms2 ms
DEVCTRL2_REGIT_POLActive-low
INT_MSK_REGVMBHI_IT_MSKswitch-on from
VMBCH_REGVMBCH_SEL[1:0]3 V
VRTC_OFFMAS
K
TSLOT_LENGTH
[0]
0: VRTC LDO will be in low-power mode during OFF state
1: VRC LDO will be in full-power mode during OFF state
0: RTC in normal power mode
1: Clock gating of RTC register and logic, low-power mode
0: Clock source is crystal/external clock
1: Clock source is internal RC oscillator
Boot sequence time slot duration:
1: 2 ms
0: INT1 signal will be active-low
1: INT1 signal will be active-high
0: Device will automatically switch-on at NOSUPPLY to
OFF or BACKUP to OFF transition
1: Startup reason required before switch-on
Select threshold for main battery comparator threshold
Registers default setting: CK32K_CTRL = 0 (32-kHz quartz or external bypass clock is used), RTC_PWDN = 1
PWRHOLD rising edge to VIO enable delay66 × t
VIO to VPLL enable delay64 × t
VPLL to VDD1 enable delay64 × t
VDD1 to VDD2 enable delay64 × t
VDD2 to VAUX2 enable delay64 × t
VAUX2 to VAUX33 enable delay64 × t
VAUX33 to CLK32KOUT enable delay64 × t
CLK32KOUT to NRESPWRON enable delay64 × t
= 2060µs
CK32k
= 2000µs
CK32k
= 2000µs
CK32k
= 2000µs
CK32k
= 2000µs
CK32k
= 2000µs
CK32k
= 2000µs
CK32k
= 2000µs
CK32k
Total switch-on delay16ms
PWRHOLD falling edge to NRESPWRON falling edge2 × t
NRESPWRON falling edge to CLK32KOUT low delay3 × t
PWRHOLD falling edge to supplies disable delay5 × t
= 62.5µs
CK32k
= 92µs
CK32k
= 154µs
CK32k
(RTC domain off), IT_POL = 0 (INt2 interrupt flag active low), VMBHI_IT_MSK = 0 (automatic switch-on on
battery plug), VMBCH_SEL = 11.
POWER CONTROL TIMING
Device Turn-On/Off With Rising/Falling Input Voltage
Figure 4 shows the device turn-on/-off with rising/falling input voltage.
The bandgap voltage reference is filtered by using an external capacitor connected across the VREF output and
the analog ground REFGND (see RECOMMENDED OPERATING CONDITIONS, Recommended Operating
Conditions). The VREF voltage is distributed and buffered inside the device.
POWER SOURCES
The power resources provided by the TPS65910 device include inductor-based switched mode power supplies
(SMPS) and linear low drop-out voltage regulators (LDOs). These supply resources provide the required power
to the external processor cores and external components, and to modules embedded in the TPS65910 device.
Two of these SMPS have DVS capability SmartReflex Class 3 compatible. These SMPS provide independent
core voltage domains to the host processor. The remaining SMPS provides supply voltage for the host processor
I/Os.
Table 12 lists the power sources provided by the TPS65910 device.
Table 12. Power Sources
RESOURCETYPEVOLTAGESPOWER
VIOSMPS1.5 V / 1.8 V / 2.5 V / 3.3 V1000 mA
VDD1SMPS0.6 ... 1.5 in 12.5-mV steps1500 mA
Programmable multiplication factor: x2, x3
VDD2SMPS0.6 ... 1.5 in 12.5-mV steps1500 mA
Programmable multiplication factor: x2, x3
VDD3SMPS5 V100 mA
VDIG1LDO1.2 V, 1.5 V, 1.8 V, 2.7 V300 mA
VDIG2LDO1 V, 1.1 V, 1.2 V, 1.8 V300 mA
VPLLLDO1.0 V, 1.1 V, 1.8 V, 2.5 V50 mA
VDACLDO1.8 V, 2.6 V, 2.8 V, 2.85 V150 mA
VAUX1LDO1.8 V, 2.5 V, 2.8 V, 2.85 V300 mA
VAUX2LDO1.8 V, 2.8 V, 2.9 V, 3.3 V150 mA
VAUX33LDO1.8 V, 2.0 V, 2.8 V, 3.3 V150 mA
VMMCLDO1.8 V, 2.8 V, 3.0 V, 3.3 V300 mA
SWCS046T –MARCH 2010–REVISED SEPTEMBER 2013
EMBEDED POWER CONTROLLER
The embedded power controller manages the state of the device and controls the power-up sequence.
STATE-MACHINE
The EPC supports the following states:
No supply: The main battery supply voltage is not high enough to power the VRTC regulator. A global reset is
asserted in this case. Everything on the device is off.
Backup: The main battery supply voltage is high enough to enable the VRTC domain but not enough to switch
on all the resources. In this state, the VRTC regulator is in backup mode and only the 32-K oscillator and RTC
module are operating (if enabled). All other resources are off or under reset.
Off: The main battery supply voltage is high enough to start the power-up sequence but device power on is not
enabled. All power supplies are in OFF state except VRTC.
Active: Device power-on enable conditions are met and regulated power supplies are on or can be enabled with
full current capability.
Sleep: Device SLEEP enable conditions are met and some selected regulated power supplies are in low-power
mode.
Figure 13 shows the transitions of the state-machine.
www.ti.com
Device power-on enable conditions:
If none of the device power-on disable conditions is met, the following conditions are available to turn on
and/or maintain the ON state of the device:
•PWRON signal low level.
•Or PWRHOLD signal high level.
•Or DEV_ON control bit set to 1 (default inactive).
•Or interrupt flag active (default INT1 low) while the device is off (NRESPWRON = 0) generates a poweron enable condition during a fixed delay (T
pulse duration defined in POWER CONTROL TIMING,
DOINT1
Power Control Timing).
The power-on enable condition pulse occurs only if the interrupt status bit is initially low (no previous
identical interrupt pending in the status register).
The Interrupt sources expected when the device is off are:
•PWRON low-level interrupt (PWRON_IT = 1 in INT_STS_REG register)
•PWRHOLD rising-edge interrupt (PWRHOLD_IT = 1 in INT_STS_REG register)
The Interrupt sources expected if enabled when the device is off are:
•RTC Alarm interrupt (RTC_ALARM_IT = 1 or RTC_PERIOD_IT = 1 in INT_STS_REG register)
•First-time input voltage rising above VMBHI threshold (Boot mode or EEPROM dependent) and input
voltage > VMBCH threshold (VMBCH_IT = 1 in INT_STS_REG register).
GPIO_CKSYNC cannot be used to turn on the device (OFF-to-ACTIVE state transition), even if its associated
interrupt is not masked, but can be used as an interrupt source to wake up the device from SLEEP-to-ACTIVE
state.
Device power-on disable conditions:
•PWRON signal low level during more than the long-press delay: t
programming). The interrupt corresponding to this condtion is PWRON_LP_IT in the INT_STS_REG register.
•Or Die temperature has reached the thermal shutdown threshold.
•Or DEV_OFF or DEV_OFF_RST control bit set to 1 (value of DEV_OFF is cleared when the device is in OFF
state).
Device SLEEP enable conditions:
•SLEEP signal low level (default, or high level depending on the programmed polarity)
•And DEV_SLP control bit set to 1
•And interrupt flag inactive (default INT1 high): no nonmasked interrupt pending
The SLEEP state can be controlled by programming DEV_SLP and keeping the SLEEP signal in the active
polarity state, or it can be controlled through the SLEEP signal setting the DEV_SLP bit to 1 once, after device
turn-on.
SWCS046T –MARCH 2010–REVISED SEPTEMBER 2013
dPWRONLP
(can be disabled though register
SWITCH-ON/-OFF SEQUENCES
The power sequence is the automated switching on of the device resources when an off-to-active transition takes
place.
The device supports three embedded power sequences selectable by the device BOOT pins.
Details of the boot sequence timing are given in SWITCH-ON/-OFF SEQUENCES AND TIMING. EEPROM
sequences can be used for specific power up sequence for corresponding application processor. For details of
EEPROMsequencerefertotheuserguidesontheproductfolder:
When none of the device sleep-disable conditions are met, a falling edge (default, or rising edge, depending on
the programmed polarity) of this signal causes an ACTIVE-to-SLEEP state transition of the device. A rising edge
(default, or falling edge, depending on the programmed polarity) causes a transition back to ACTIVE state. This
input signal is level sensitive and no debouncing is applied.
While the device is in SLEEP state, predefined resources are automatically set in their low-power mode or off.
Resources can be kept in their active mode: (full-load capability), programming the SLEEP_KEEP_LDO_ON and
the SLEEP_KEEP_RES_ON registers. These registers contain 1 bit per power resource. If the bit is set to 1,
then that resource stays in active mode when the device is in SLEEP state. 32KCLKOUT is also included in the
SLEEP_KEEP_RES_ON register and the 32-kHz clock output is maintained in SLEEP state if the corresponding
mask bit is set.
PWRHOLD
When none of the device power-on disable conditions are met, a rising edge of this signal causes an OFF-toACTIVE state transition of the device and a falling edge causes a transition back to OFF state. Typically, this
signal is used to control the device in a slave configuration. It can be connected to the SYSEN output signal from
other TPS659xx devices, or the NRESPWRON signal of another TPS65910 device. This input signal is level
sensitive and no debouncing is applied.
A rising edge of PWRHOLD is highlighted though an associated interrupt.
BOOT0/BOOT1
These signals determine which processor the device is working with and hence which power-up sequence is
needed. See SWITCH-ON/-OFF SEQUENCES AND TIMING for more details. There is no debouncing on this
input signal.
NRESPWRON
This signal is used as the reset to the processor. It is held low until the ACTIVE state is reached. See POWER
CONTROL TIMING to get detailed timing.
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CLK32KOUT
This signal is the output of the 32K oscillator, which can be enabled or not during the power-on sequence,
depending on the Boot mode. It can be enabled and disabled by register bit, during ACTIVE state of the device.
CLK32KOUT output can also be enabled or not during SLEEP state of the device depending on the
SLEEPMASK register programming.
PWRON
A falling edge on this signal causes after t
dbPWRONF
debouncing delay (defined in Figure 5 and Table 6) an OFFto-ACTIVE state or SLEEP-to-ACTIVE state transition of the device and makes the corresponding interrupt
(PWRON_IT) active. The PWRON input is connected to an external push-button. The built-in debouncing time
defines a minimum button press duration that is required for button press detection. Any button press duration
which is lower than this value is ignored, considered an accidental touch.
After an OFF-to-ACTIVE state transition, the PMIC maintains ACTIVE during t
delay, if the button is
dOINT
released. After this delay if none of the device enabling conditions is set by the processor supplied, the PMIC
automatically turns off. If the button is not released, the PMIC maintains ACTIVE up to t
dPWRONLPTO
, because
PWRON low is a device enabling condition. After a SLEEP-to-ACTIVE state transition, the PMIC maintains
ACTIVE as long as an interrupt is pending.
If the device is already in ACTIVE state, a PWRON low level makes the corresponding interrupt (PWRON_IT)
active.
When the PMIC is in ACTIVE mode, if the button is pressed for longer time than t
dPWRONLP
, the PMIC generates
the PWON_LP_IT interrupt. If the processor does not acknowledge the long press interrupt within a period of
t
dPWRONLPTO
– t
dPWRONLP
, the PMIC goes to OFF mode and shuts down the DCDCs and LDOs.
INT1
INT1 signal (default active low) warns the host processor of any event that occurred on the TPS65910 device.
The host processor can then poll the interrupt from the interrupt status register through I2C to identify the
interrupt source. A low level (default setting) indicates an active interrupt, highlighted in the INT_STS_REG
register. The polarity of INT1 can be set by programming the IT_POL control bit.
Any (not masked or masked) interrupt detection causes a POWER ON enable condition during a fixed delay
t
(only) when the device is in OFF state (when NRESPWON signal is low). Any (not masked) interrupt
DOINT1
detection is causing a device wakeup from SLEEP state up to acknowledge of the pending interrupt. Any of the
interrupt sources can be masked by programming the INT_MSK_REG register. When an interrupt is masked, its
corresponding interrupt status bit is still updated, but the INT1 flag is not activated.
Interrupt source masking can be used to mask a device switch-on event. Because interrupt flag active is a
POWER ON enable condition during t
the device after the t
DOINT1
POWER ON enable pulse duration.. See section: Interrupts, for interrupt sources
delay, any interrupt not masked must be cleared to allow turn off of
DOINT1
definition.
SDASR_EN2 and SCLSR_EN1
SDASR_EN2 and SCLSR_EN1 are the data and clock signals of the serial control interface (SR-I2C) dedicated
to SmartReflex applications. These signals can also be programmed to be used as enable signals of one or
several supplies, when the device is on (NRESPWRON high). A resource assigned to SDASR_EN2 or
SCLSR_EN1 control automatically disables the serial control interface.
ProgrammingEN1_LDO_ASS_REG,EN2_LDO_REG,andSLEEP_KEEP_LDO_ON_REGregisters:
SCLSR_EN1 and SDASR_EN2 signals can be used to control the turn on/off or sleep state of any LDO type
supplies.
ProgrammingEN1_SMPS_ASS_REG,EN2_SMPS_ASS_REG,andSLEEP_KEEP_RES_ONregisters:
SCLSR_EN1 and SDASR_EN2 signals can be used to control the turn on/off or low-power state (PFM mode) of
SMPS type supplies.
SDASR_EN2 and SCLSR_EN1 can be used to set output voltage of VDD1 and VDD2 SMPS from a roof to a
floor value, preprogrammed in the VDD1_OP_REG, VDD2_OP_REG, and teh VDD1_SR_REG, VDD2_SR_REG
registers. Tun-off of VDD1 and VDD2 can also be programmed either in VDD1_OP_REG, VDD2_OP_REG or in
VDD1_SR_REG, VDD2_SR_REG registers.
When a supply is controlled through SCLSR_EN1 or SCLSR_EN2 signals, its state is no longer driven by the
device SLEEP state.
SWCS046T –MARCH 2010–REVISED SEPTEMBER 2013
GPIO_CKSYNC
GPIO_CKSYNC is a configurable open-drain digital I/O: directivity, debouncing delay and internal pullup can be
programmed in the GPIO0_REG register. GPIO_CKSYNC cannot be used to turn on the device (OFF-to-ACTIVE
state transition), even if its associated interrupt is not masked, but can be used as an interrupt source to wake up
the device from SLEEP-to-ACTIVE state.
Programming DCDCCKEXT = 1, VDD1, VDD2, VIO, and VDD3 dc-dc switching can be synchronized using a 3MHz clock set though the GPIO_CKSYNC pin.
DYNAMIC VOLTAGE FREQUENCY SCALING AND ADAPTIVE VOLTAGE SCALING OPERATION
Dynamic voltage frequency scaling (DVFS) operation: a supply voltage value corresponding to a targeted
frequency of the digital core supplied is programmed in VDD1_OP_REG or VDD2_OP_REG registers.
The slew rate of the voltage supply reaching a new VDD1_OP_REG or VDD2_OP_REG programmed value is
limited to 12.5 mV/µs, fixed value. Adaptative voltage scaling (AVS) operation: a supply voltage value
corresponding to a supply voltage adjustment is programmed in VDD1_SR_REG or VDD2_SR_REG registers.
The supply voltage is then intended to be tuned by the digital core supplied, based its performance selfevaluation. The slew rate of VDD1 or VDD2 voltage supply reaching a new programmed value is programmable
though the VDD1_REG or VDD2_REG register, respectively.
A serial control interface (SR-I2C) is dedicated to SmartReflex applications such as DVFS and class 3 AVS, and
thus gives access to the VDD1_OP_REG, VDD1_SR_REG, and VDD2_OP_REG, VDD2_SR_REG register.
A general-purpose serial control interface (CTL-I2C) also gives access to these registers, if SR_CTL_I2C_SEL
control bit is set to 1 in the DEVCTRL_REG register (default inactive).
Both control interfaces are compliant with HS-I2C specification (100 kbps, 400 kbps, or 3.4 Mbps).
Figure 14 shows an example of a SmartReflex operation. To optimize power efficiency, the voltage domains of
the host processor uses the DVFS and AVS features provided by SmartReflex.
(1) TSR: Time used by the SmartReflex controller
(2) T
(3) T
: Time used for data transfer through the I2C interface
I2C
: Time required by the SMPS to converge to new voltage value
SMPS
Figure 14. SmartReflex Operation Example
32-kHz RTC CLOCK
The TPS65910 device can provide a 32-kHz clock to the platform through the CLK32KOUT output, the source of
this 32-kHz clock can be:
•32-kHz crystal connected from OSC32IN to OSC32KOUT pins
•A square-wave 32-kHz clock signal applied to OSC32IN input (OSC32KOUT kept floating).
•Internal 32-kHz RC oscillator, to reduce the BOM, if an accurate clock is not needed by the system.
Default selection of a 32-kHz RC oscillator versus 32-kHz crystal oscillator or external square-wave 32-kHz clock
depends on the Boot mode or device version (EEPROM programming):
The RTC, which is driven by the 32-kHz clock, provides the alarm and timekeeping functions. The RTC is kept
supplied when the device is in the OFF or the BACKUP state.
The main functionalities of the RTC block are:
•Time information (seconds/minutes/hours) directly in binary-coded decimal (BCD) format
•Calendar information (Day/Month/Year/Day of the week) directly in BCD code up to year 2099
RTC_PERIOD_IT periodically (1s/1m/1h/1d period) and an alarm interrupt RTC_ALARM_IT at a precise time
of the day (alarm function). These interrupts are enabled using IT_ALARM and IT_TIMER control bits.
Periodically interrupts can be masked during the SLEEP period to avoid host interruption and are
automatically unmasked after SLEEP wakeup (using the IT_SLEEP_MASK_EN control bit).
•Oscillator frequency calibration and time correction
INT_ALARM can generate a wakeup of the platform.
INT_TIMER cannot generate a wakeup of the platform.
TIME CALENDAR REGISTERS
All the time and calendar information are available in these dedicated registers, called TC registers. Values of the
TC registers are written in BCD format.
1. Year data ranges from 00 to 99
– Leap year = Year divisible by four (2000, 2004, 2008, 2012...)
– Common year = other years
2. Month data ranges from 01 to 12
3. Day value ranges from:
– 1 to 31 when months are 1, 3, 5, 7, 8, 10, 12
– 1 to 30 when months are 4, 6, 9, 11
– 1 to 29 when month is 2 and year is a leap year
– 1 to 28 when month is 2 and year is a common year
4. Week value ranges from 0 to 6
5. Hour value ranges from 00 to 23 in 24-hour mode and ranges from 1 to 12 in AM/PM mode
6. Minutes value ranges from 0 to 59
7. Seconds value ranges from 0 to 59
To modify the current time, software writes the new time into TC registers to fix the time/calendar information.
The DBB can write into TC registers without stopping the RTC. In addition, software can stop the RTC by
clearing the STOP_RTC bit of the control register and check the RUN bit of the status to be sure that the RTC is
frozen. Then update TC values, and then restart the RTC by setting the STOP_RTC bit.
Example: Time is 10H54M36S PM (PM_AM mode set), 2008 September 5, previous register values are:
The user can round to the closest minute, by setting the ROUND_30S register bit. TC values are set to the
closest minute value at the next second. The ROUND_30S bit is automatically cleared when the rounding time is
performed.
Example:
•If current time is 10H59M45S, a round operation changes time to 11H00M00S.
•if current time is 10H59M29S, a round operation changes time to 10H59M00S.
GENERAL REGISTERS
Software can access the RTC_STATUS_REG and RTC_CTRL_REG registers at any time (except for the
RTC_CTRL_REG[5] bit, which must be changed only when the RTC is stopped).
COMPENSATION REGISTERS
The RTC_COMP_MSB_REG and RTC_COMP_LSB_REG registers must respect the available access period.
These registers must be updated before each compensation process. For example, software can load the
compensation value into these registers after each hour event, during an available access period.
This drift can be balanced to compensate for any inaccuracy of the 32-kHz oscillator. Software must calibrate the
oscillator frequency, calculate the drift compensation versus one time hour period; and then load the
compensation registers with the drift compensation value. Indeed, if the AUTO_COMP_EN bit in the
RTC_CTRL_REG is enabled, the value of COMP_REG (in twos-complement) is added to the RTC 32-kHz
counter at each hour and one second. When COMP_REG is added to the RTC 32-kHz counter, the duration of
the current second becomes (32768 - COMP_REG)/32768s; so, the RTC can be compensated with a 1/32768
s/hour time unit accuracy.
NOTE
The compensation is considered once written into the registers.
BACKUP BATTERY MANAGEMENT
The device includes a back-up battery switch connecting the VRTC regulator input to a main battery (VCC7) or to
a back-up battery (VBACKUP), depending on the batteries voltage value.
The VRTC supply can then be maintained during a BACKUP state as far as the input voltage is high enough
(>VBNPR threshold). Below the VBNPR voltage threshold the digital core of the device is set under reset by
internal signal POR (PowerOnReset).
The back-up domain functions which are always supplied from VRTC comprehend:
•The internal 32-kHz oscillator
•Backup registers
The back-up battery can be charged from the main battery through an embedded charger. The back-up battery
charge voltage and enable is controlled through BBCH_REG register programming. This register content is
maintained during the device Backup state.
Hence enabled the back-up battery charge is maintained as far as the main battery voltage is higher than the
VMBLO threshold and the back-up battery voltage.
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BACKUP REGISTERS
As part of the RTC the device contains five 8-bit registers which can be used for storage by the application
firmware when the external host is powered down. These registers retain their content as long as the VRTC is
active.
I2C INTERFACE
A general-purpose serial control interface (CTL-I2C) allows read and write access to the configuration registers of
all resources of the system.
A second serial control interface (SR-I2C) is dedicated to SmartReflex applications such as DVFS or AVS.
Both control interfaces are compliant with HS-I2C specification.
These interfaces support the standard slave mode (100 Kbps), Fast mode (400 Kbps), and high-speed mode
(3.4 Mbps). The general-purpose I2C module using one slave hard-coded addresse (ID1 = 2Dh). The
SmartReflex I2C module uses one slave hard-coded address (ID0 = 12h). The master mode is not supported.
Addressing: Seven-bit mode addressing device
They do not support the following features:
•10-bit addressing
•General call
THERMAL MONITORING AND SHUTDOWN
A thermal protection module monitors the junction temperature of the device versus two thesholds:
When the hot-die temperature threshold is reached an interrupt is sent to software to close the noncritical running
tasks.
When the thermal shutdown temperature theshold is reached, the TPS65910 device is set under reset and a
transition to OFF state is initiated. Then the power-on enable conditions of the device is not considered until the
die temperature has decreased below the hot-die threshold. An hysteresis is applied to the hot-die and shutdown
threshold, when detecting a falling edge of temperature, and both detection are debounced to avoid any parasitic
detection. The TPS65910 device allows programming of four hot-die temperature thresholds to increase the
flexibility of the system.
By default, the thermal protection is enabled in ACTIVE state, but can be disabled through programming register
THERM_REG.ThethermalprotectioncanbeenabledinSLEEPstateprogrammingregister
SLEEP_KEEP_RES_ON. The thermal protection is automatically enabled during an OFF-to-ACTIVE state
transition and is kept enabled in OFF state after a switch-off sequence caused by a thermal shutdown event.
Transition to OFF state sequence caused by a thermal shutdown event is highlighted in the INT_STS_REG
status register. Recovery from this OFF state is initiated (switch-on sequence) when the die temperature falls
below the hot-die temperature threshold.
Hot-die and thermal shutdown temperature threshold detections state can be monitored or masked by reading or
programming the THERM_REG register. Hot-die interrupt can be masked by programming the INT_MSK_REG
register.
INTERRUPTS
SWCS046T –MARCH 2010–REVISED SEPTEMBER 2013
Table 13. Interrupt Sources
InterruptDescription
RTC_ALARM_ITRTC alarm event: Occurs at programmed determinate date and time
(running in ACTIVE, OFF, and SLEEP state, default inactive)
RTC_PERIOD_IT
HOT_DIE_IT
PWRHOLD_ITPWRHOLD signal rising edge
PWRON_LP_IT
PWRON_IT
VMBHI_IT
VMBDCH_IT
GPIO0_R_ITGPIO_CKSYNC rising-edge detection (available in ACTIVE and SLEEP state)
GPIO0_F_ITGPIO_CKSYNC falling-edge detection (available in ACTIVE and SLEEP state)
RTC periodic event: Occurs at programmed regular period of time (every second or minute)
(running in ACTIVE, OFF, and SLEEP state, default inactive)
The embedded thermal monitoring module has detected a die temperature above the hot-die
detection threshold (running in ACTIVE and SLEEP state)
Level sensitive interrupt.
PWRON is low during more than the long-press delay: t
register programming).
PWRON is low while the device is on (running in ACTIVE and SLEEP state) or PWON was
low while the device was off (causing a device turn-on). Level-sensitive interrupt
The battery voltage rise above the VMBHI threshold: NOSUPPLY to Off or Backup-to-Off
device states transition (first battery plug or battery voltage bounce detection). This interrupt
source can be disabled through EEPROM programming (VMBHI_IT_DIS). Edge-sensitive
interrupt
The battery voltage falls down below the VMBDCH threshold(running in ACTIVE and SLEEP
state, if enabled programming VMBCH_VSEL). Edge-sensitive interrupt
dPWRONLP
(can be disable though
INT1 signal (active low) warns the host processor of any event that occurred on the TPS65910 device. The host
processor can then poll the interrupt from the interrupt status register via I2C to identify the interrupt source. Each
interrupt source can be individually masked via the interrupt mask register.
0s
2:0WEEKFirst digit of day of the week (range is 0 up to 6)RW0
Table 22. ALARM_SECONDS_REG
Address Offset0x08
Physical AddressInstance
DescriptionRTC register for alarm programmation for seconds
TypeRW
76543210
ReservedALARM_SEC1ALARM_SEC0
BitsField NameDescriptionTypeReset
7ReservedReserved bitRO0
R returns
0s
6:4ALARM_SEC1Second digit of alarm programmation for seconds (range is 0 up to 5)RW0x0
3:0ALARM_SEC0First digit of alarm programmation for seconds (range is 0 up to 9)RW0x0
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Table 23. ALARM_MINUTES_REG
Address Offset0x09
Physical AddressInstance
DescriptionRTC register for alarm programmation for minutes
TypeRW
76543210
ReservedALARM_MIN1ALARM_MIN0
BitsField NameDescriptionTypeReset
7ReservedReserved bitRO0
6:4ALARM_MIN1Second digit of alarm programmation for minutes (range is 0 up to 5)RW0x0
3:0ALARM_MIN0First digit of alarm programmation for minutes (range is 0 up to 9)RW0x0
R returns
0s
Table 24. ALARM_HOURS_REG
Address Offset0x0A
Physical AddressInstance
DescriptionRTC register for alarm programmation for hours
TypeRW
7ALARM_PM_NAMOnly used in PM_AM mode for alarm programmation (otherwise it is setRW0
to 0)
0 is AM
1 is PM
6ReservedReserved bitRO0
5:4ALARM_HOUR1Second digit of alarm programmation for hours(range is 0 up to 2)RW0x0
3:0ALARM_HOUR0First digitof alarm programmation for hours (range is 0 up to 9)RW0x0
Table 25. ALARM_DAYS_REG
Address Offset0x0B
Physical AddressInstance
DescriptionRTC register for alarm programmation for days
TypeRW
76543210
ReservedALARM_DAY1ALARM_DAY0
BitsField NameDescriptionTypeReset
7:6ReservedReserved bitRO0x0
5:4ALARM_DAY1Second digit of alarm programmation for days (range is 0 up to 3)RW0x0
3:0ALARM_DAY0First digit of alarm programmation for days (range is 0 up to 9)RW0x1
SWCS046T –MARCH 2010–REVISED SEPTEMBER 2013
R returns
0s
R Special
Table 26. ALARM_MONTHS_REG
Address Offset0x0C
Physical AddressInstance
DescriptionRTC register for alarm programmation for months
TypeRW
76543210
ReservedALARM_MONTH0
ALARM_MONTH1
BitsField NameDescriptionTypeReset
7:5ReservedReserved bitRO0x0
4ALARM_MONTH1Second digit of alarm programmation for months (range is 0 up to 1)RW0
3:0ALARM_MONTH0First digit of alarm programmation for months (range is 0 up to 9)RW0x1
R returns
0s
Table 27. ALARM_YEARS_REG
Address Offset0x0D
Physical AddressInstance
DescriptionRTC register for alarm programmation for years
TypeRW
7:4ALARM_YEAR1Second digit of alarm programmation for years (range is 0 up to 9)RW0x0
3:0ALARM_YEAR0First digit of alarm programmation for years (range is 0 up to 9)RW0x0
Table 28. RTC_CTRL_REG
Address Offset0x10
Physical AddressInstance
DescriptionRTC control register:
NOTES: A dummy read of this register is necessary before each I2C read in order to update the
ROUND_30S bit value.
6GET_TIMEWhen writing a 1 into this register, the content of the dynamic registersRW0
5SET_32_COUNTER0: No actionRW0
4TEST_MODE0: functional modeRW0
3MODE_12_240: 24 hours modeRW0
2AUTO_COMP0: No auto compensationRW0
1ROUND_30S0: No updateRW0
0STOP_RTC0: RTC is frozenRW0
0: Read access directly to dynamic registers (SECONDS_REG,
MINUTES_REG, HOURS_REG, DAYS_REG, MONTHS_REG,
YEAR_REG, WEEKS_REG)
1: Read access to static shadowed registers: (see GET_TIME bit).
(SECONDS_REG, MINUTES_REG, HOURS_REG, DAYS_REG,
MONTHS_REG, YEAR_REG and WEEKS_REG) is transferred into
static shadowed registers. Each update of the shadowed registers needs
to be done by re-asserting GET_TIME bit to 1 (i.e.: reset it to 0 and then
re-write it to 1)
1: set the 32-kHz counter with COMP_REG value.
It must only be used when the RTC is frozen.
1: test mode (Auto compensation is enable when the 32kHz counter
reaches at its end)
1: 12 hours mode (PM-AM mode)
It is possible to switch between the two modes at any time without
disturbed the RTC, read or write are always performed with the current
mode.
1: Auto compensation enabled
1: When a one is written, the time is rounded to the closest minute.
This bit is a toggle bit, the micro-controller can only write one and RTC
clears it. If the micro-controller sets the ROUND_30S bit and then read it,
the micro-controller will read one until the rounded to the closet.
7POWER_UPIndicates that a reset occurred (bit cleared to 0 by writing 1).RW1
POWER_UP is set by a reset, is cleared by writing one in this bit.
6ALARMIndicates that an alarm interrupt has been generated (bit clear by writingRW0
1).
The alarm interrupt keeps its low level, until the micro-controller write 1 in
the ALARM bit of the RTC_STATUS_REG register.
The timer interrupt is a low-level pulse (15 µs duration).
5EVENT_1DOne day has occurredRO0
4EVENT_1HOne hour has occurredRO0
3EVENT_1MOne minute has occurredRO0
2EVENT_1SOne second has occurredRO0
1RUN0: RTC is frozenRO0
1: RTC is running
This bit shows the real state of the RTC, indeed because of STOP_RTC
signal was resynchronized on 32-kHz clock, the action of this bit is
delayed.
0ReservedReserved bitRO0
SWCS046T –MARCH 2010–REVISED SEPTEMBER 2013
R returns
0s
Table 30. RTC_INTERRUPTS_REG
Address Offset0x12
Physical AddressInstance
DescriptionRTC interrupt control register
TypeRW
76543210
ReservedIT_ALARMIT_TIMEREVERY
IT_SLEEP_MASK_EN
BitsField NameDescriptionTypeReset
7:5ReservedReserved bitRO0x0
4IT_SLEEP_MASK_E1: Mask periodic interrupt while the TPS65910 device is in SLEEP mode.RW0
NInterrupt event is back up in a register and occurred as soon as the
5:0SW_RES_PROGValue of the oscillator resistanceRW0x27
Table 34. RTC_RESET_STATUS_REG
Address Offset0x16
Physical AddressInstance
DescriptionRTC register for reset status
TypeRW
76543210
Reserved
SWCS046T –MARCH 2010–REVISED SEPTEMBER 2013
R returns
0s
RESET_STATUS
BitsField NameDescriptionTypeReset
7:1ReservedReserved bitRO0x0
0RESET_STATUSRW0x0
R returns
0s
Table 35. BCK1_REG
Address Offset0x17
Physical AddressInstance
DescriptionBackup register which can be used for storage by the application firmware when the external host is
TypeRW
76543210
BitsField NameDescriptionTypeReset
7:0BCKUPBackup bitRW0x00
powered down. These registers will retain their content as long as the VRTC is active.
BCKUP
Table 36. BCK2_REG
Address Offset0x18
Physical AddressInstance
DescriptionBackup register which can be used for storage by the application firmware when the external host is
TypeRW
powered down. These registers will retain their content as long as the VRTC is active.
Address Offset0x19
Physical AddressInstance
DescriptionBackup register which can be used for storage by the application firmware when the external host is
powered down. These registers will retain their content as long as the VRTC is active.
TypeRW
76543210
BCKUP
BitsField NameDescriptionTypeReset
7:0BCKUPBackup bitRW0x00
Table 38. BCK4_REG
Address Offset0x1A
Physical AddressInstance
DescriptionBackup register which can be used for storage by the application firmware when the external host is
powered down. These registers will retain their content as long as the VRTC is active.
TypeRW
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76543210
BCKUP
BitsField NameDescriptionTypeReset
7:0BCKUPBackup bitRW0x00
Table 39. BCK5_REG
Address Offset0x1B
Physical AddressInstance
DescriptionBackup register which can be used for storage by the application firmware when the external host is
TypeRW
76543210
BitsField NameDescriptionTypeReset
7:0BCKUPBackup bitRW0x00
powered down. These registers will retain their content as long as the VRTC is active.
BCKUP
Table 40. PUADEN_REG
Address Offset0x1C
Physical AddressInstance
DescriptionPull-up/pull-down control register.
TypeRW
When 11 : 2 ms
3SLEEPSIG_POLWhen 1, SLEEP signal active highRW0
When 0, SLEEP signal active low
2PWRON_LP_OFFWhen 1, allows device turn-off after a PWRON long press (signal low).RW1
1PWRON_LP_RSTWhen 1, allows digital core reset when the device is OFF after aRW0
PWRON long press (signal low).
0IT_POLINT1 interrupt pad polarity control signal (EEPROM bit):RW0
When 0, active low
When 1, active high
PWRON_LP_OFF
R returns
PWRON_LP_RST
0s
Table 64. SLEEP_KEEP_LDO_ON_REG
Address Offset0x41
Physical AddressInstance
DescriptionWhen corresponding control bit=0 in EN1/2_ LDO_ASS register (default setting): Configuration Register
TypeRW
keeping the full load capability of LDO regulator (ACTIVE mode) during the SLEEP state of the device.
When control bit=1, LDO regulator full load capability (ACTIVE mode) is maintained during device
SLEEP state.
When control bit=0, the LDO regulator is set or stay in low power mode during device SLEEP state(but
then supply state can be overwritten programming ST[1:0]). Control bit value has no effect if the LDO
regulator is off.
When corresponding control bit=1 in EN1/2_ LDO_ASS register: Configuration Register setting the LDO
regulator state driven by SCLSR_EN1/2 signal low level (when SCLSR_EN1/2 is high the regulator is
on, full power):
- the regulator is set off if its corresponding Control bit = 0 in SLEEP_KEEP_LDO_ON register (default)
- the regulator is set in low power mode if its corresponding control bit = 1 in SLEEP_KEEP_LDO_ON
7VDAC_KEEPONSetting supply state during device SLEEP state or when SCLSR_EN1/2RW0
is low
6VPLL_KEEPONSetting supply state during device SLEEP state or when SCLSR_EN1/2RW0
is low
5VAUX33_KEEPONSetting supply state during device SLEEP state or when SCLSR_EN1/2RW0
is low
4VAUX2_KEEPONSetting supply state during device SLEEP state or when SCLSR_EN1/2RW0
is low
3VAUX1_KEEPONSetting supply state during device SLEEP state or when SCLSR_EN1/2RW0
is low
2VDIG2_KEEPONSetting supply state during device SLEEP state or when SCLSR_EN1/2RW0
is low
1VDIG1_KEEPONSetting supply state during device SLEEP state or when SCLSR_EN1/2RW0
is low
0VMMC_KEEPONSetting supply state during device SLEEP state or when SCLSR_EN1/2RW0
is low
Table 65. SLEEP_KEEP_RES_ON_REG
Address Offset0x42
Physical AddressInstance
DescriptionConfiguration Register keeping, during the SLEEP state of the device (but then supply state can be
overwritten programming ST[1:0]):
- the full load capability of LDO regulator (ACTIVE mode),
- The PWM mode of DCDC converter
- 32KHz clock output
- Register access though I2C interface (keeping the internal high speed clock on)
- Die Thermal monitoring on
Control bit value has no effect if the resource is off.
TypeRW
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76543210
VIO_KEEPON
THERM_KEEPON
CLKOUT32K_KEEPON
BitsField NameDescriptionTypeReset
7THERM_KEEPONWhen 1, thermal monitoring is maintained during device SLEEP state.RW0
6CLKOUT32K_KEEPO When 1, CLK32KOUT output is maintained during device SLEEP state.RW0
NWhen 0, CLK32KOUT output is set low during device SLEEP state.
5VRTC_KEEPONWhen 1, LDO regulator full load capability (ACTIVE mode) is maintainedRW0
4I2CHS_KEEPONWhen 1, high speed internal clock is maintained during device SLEEPRW0
3VDD3_KEEPONWhen 1, VDD3 SMPS high power mode is maintained during deviceRW0
VRTC_KEEPON
When 0, thermal monitoring is turned off during device SLEEP state.
during device SLEEP state.
When 0, the LDO regulator is set or stays in low power mode during
device SLEEP state.
state.
When 0, high speed internal clock is turned off during device SLEEP
state.
SLEEP state. No effect if VDD3 working mode is low power.
When 0, VDD3 SMPS low power mode is set during device SLEEP
7VDAC_EN1Setting supply state control though SCLSR_EN1 signalRW0
6VPLL_EN1Setting supply state control though SCLSR_EN1 signalRW0
5VAUX33_EN1Setting supply state control though SCLSR_EN1 signalRW0
4VAUX2_EN1Setting supply state control though SCLSR_EN1 signalRW0
3VAUX1_EN1Setting supply state control though SCLSR_EN1 signalRW0
2VDIG2_EN1Setting supply state control though SCLSR_EN1 signalRW0
1VDIG1_EN1Setting supply state control though SCLSR_EN1 signalRW0
0VMMC_EN1Setting supply state control though SCLSR_EN1 signalRW0
7VDAC_EN2Setting supply state control though SDASR_EN2 signalRW0
6VPLL_EN2Setting supply state control though SDASR_EN2 signalRW0
5VAUX33_EN2Setting supply state control though SDASR_EN2 signalRW0
4VAUX2_EN2Setting supply state control though SDASR_EN2 signalRW0
3VAUX1_EN2Setting supply state control though SDASR_EN2 signalRW0
2VDIG2_EN2Setting supply state control though SDASR_EN2 signalRW0
1VDIG1_EN2Setting supply state control though SDASR_EN2 signalRW0
0VMMC_EN2Setting supply state control though SDASR_EN2 signalRW0
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Table 71. EN2_SMPS_ASS_REG
Address Offset0x48
Physical AddressInstance
DescriptionConfiguration Register setting the SMPS Supplies driven by the multiplexed SDASR_EN2 signal.
TypeRW
76543210
RSVDSPARE_EN2VDD3_EN2VDD2_EN2VDD1_EN2VIO_EN2
BitsField NameDescriptionTypeReset
7:5RSVDReserved bitRO0x0
4SPARE_EN2Spare bitRW0
3VDD3_EN2When 1:RW0
When control bit = 1, SMPS Supply state and voltage is driven by the SDASR_EN2 control signal and is
also defined though SLEEP_KEEP_RES_ON register setting.
When control bit = 0 no effect: SMPS Supply state is driven though registers programming and the
device state
Any control bit of this register set to 1 will disable the I2C SR Interface functionality
R returns
0s
When SDASR_EN2 is high the supply is on.
When SDASR_EN2 is low and SLEEP_KEEP_RES_ON = 0 the supply
voltage is off.
When SDASR_EN2 is low and SLEEP_KEEP_RES_ON = 1 the SMPS
is working in low power mode.
When control bit = 0 no effect: supply state is driven though registers
When *_IT_MSK is set to 1, the associated interrupt is masked: INT1 signal is not activated, but *_IT
interrupt status bit is updated.
When *_IT_MSK is set to 0, the associated interrupt is enabled: INT1 signal is activated, *_IT is
updated.
4GPIO_DEBGPIO_CKSYNC input debouncing time configuration:RW0
When 0, the debouncing is 91.5 µs using a 30.5 µs clock rate
When 1, the debouncing is 150 ms using a 50 ms clock rate
3GPIO_PUENGPIO_CKSYNC pad pull-up control:RW1
1: Pull-up is enabled
0: Pull-up is disabled
2GPIO_CFGConfiguration of the GPIO_CKSYNC pad direction:RW0
When 0, the pad is configured as an input
When 1, the pad is configured as an output
1GPIO_STSStatus of the GPIO_CKSYNC padRO1
0GPIO_SETValue set on the GPIO output when configured in output modeRW0
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Table 79. JTAGVERNUM_REG
Address Offset0x80
Physical AddressInstance
DescriptionSilicon version number
TypeRO
76543210
ReservedVERNUM
BitsField NameDescriptionTypeReset
7:4ReservedReserved bitRO0x0
3:0VERNUMValue depending on silicon version number 0000 - Revision 1.0RO0x0
Charger. Update Rated output current, PMOS current limit (High-Side), NMOS current limit (Low-Side), and Conversion Efficiency for
VIO SMPS, VDD1/VDD2/VDD3 SMPS and VDIG1/VDIG2 LDO. Update Input Voltage for VIO/VDD1/VDD2 SMPS. Update DC and
Transient Load and Line Regulatio and Internal Resistance for VDIG1/VDIG2 LDO, VAUX33/VMMC LDO, VAUX1,VAUX2, LDO, and
VDAC/VPLL LDO. Update DC Load Regulation for VAUX3/VMMC/VDAC. Update Power Control Timing. Add Device SLEEP State
Control. Add SMPS Switching Synchronization. Update VIO_REG, VDD1_REG, and VDD2_REG.
(6) SWCS046E: Manually added Thermal Pad Mechanical Data.
(7) SWCS046F: UpdateTable 1, SUPPORTED PROCESSORS AND CORRESPONDING PART NUMBERS.
(8) SWCS046G: Update PACKAGE DESCRIPTION, RECOMMENDED OPERATING CONDITIONS, DIGITAL I/O VOLTAGE ELECTRICAL
CHARACTERISTICS, and PWRON.
(9) SWCS046H: Update Table 40, PUADEN_REG, Table 72, RESERVED, and Table 73, RESERVED.
(10) SWCS046I: Update DC Output voltage V
(11) SWCS046J: UpdateTable 1, SUPPORTED PROCESSORS AND CORRESPONDING PART NUMBERS.
in VAUX1 AND VAUX2 LDO.
OUT
(12) SWCS046K: UpdateTable 1, SUPPORTED PROCESSORS AND CORRESPONDING PART NUMBERS - Add AM335x.
(13) SWCS046L: Update Table 1, SUPPORTED PROCESSORS AND CORRESPONDING PART NUMBERS - Add AM335x with DDR2 and
AM335x with DDR3.
(14) SWCS046M: Update STATE-MACHINE, - Update Device Sleep enable conditions control information.
(15) SWCS046N:
(c) Update Input voltage: VDIG1 AND VDIG2 LDO
(16) SWCS046O: Update Table 6, Power Control Timing Characteristics
(a) Replace unit of µs for t
(17) SWCS046P: Update Table 1, SUPPORTED PROCESSORS AND CORRESPONDING PART NUMBERS -
dbPWRONF
by ms
(a) Add AM335x with DDR3 - TPS65910A31A1RSL
(b) Add Rockchip - RK30xx
(18) SWCS046Q: Update Table 1, SUPPORTED PROCESSORS AND CORRESPONDING PART NUMBERS -
(a) Refer to SWCU093 document: Update document reference from TBD to SWCU093
(19) SWCS046R: Update VRTC LDO, VRTC LDO - Changed Input Voltage - Back-up mode - Max from 3V to 5.5V.
(20) SWCS046S: Update VAUX1 AND VAUX2 LDO, VAUX1 AND VAUX2 LDO - Changed VAUX2 - Rated Output Current I
TPS659104A1RSLPREVIEWVQFNRSL4860TBDCall TICall TI-40 to 85
TPS659104A1RSLRPREVIEWVQFNRSL482500TBDCall TICall TI-40 to 85
TPS659105A1RSLPREVIEWVQFNRSL4860Green (RoHS
TPS659105A1RSLRPREVIEWVQFNRSL482500Green (RoHS
TPS659106A1RSLACTIVEVQFNRSL4860Green (RoHS
TPS659106A1RSLRACTIVEVQFNRSL482500Green (RoHS
TPS659107A1RSLPREVIEWVQFNRSL4860TBDCall TICall TI-40 to 85
TPS659107A1RSLRPREVIEWVQFNRSL482500TBDCall TICall TI-40 to 85
TPS659108A1RSLACTIVEVQFNRSL4860Green (RoHS
TPS659108A1RSLRACTIVEVQFNRSL482500Green (RoHS
TPS659109A1RSLACTIVEVQFNRSL4860Green (RoHS
TPS659109A1RSLRACTIVEVQFNRSL482500Green (RoHS
TPS65910A1RSLACTIVEVQFNRSL4860Green (RoHS
Package Type Package
(1)
Drawing
Pins Package
Qty
Eco Plan
(2)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
Lead/Ball FinishMSL Peak Temp
(3)
CU NIPDAULevel-3-260C-168 HR-40 to 85T659101
CU NIPDAULevel-3-260C-168 HR-40 to 85T659101
CU NIPDAULevel-3-260C-168 HR-40 to 85T659102
CU NIPDAULevel-3-260C-168 HR-40 to 85T659102
CU NIPDAULevel-3-260C-168 HR-40 to 85T659103
CU NIPDAULevel-3-260C-168 HR-40 to 85T659103
CU NIPDAULevel-3-260C-168 HR-40 to 85T659105
CU NIPDAULevel-3-260C-168 HR-40 to 85T659105
CU NIPDAULevel-3-260C-168 HR-40 to 85T659106
CU NIPDAULevel-3-260C-168 HR-40 to 85T659106
CU NIPDAULevel-3-260C-168 HR-40 to 85T659108
CU NIPDAULevel-3-260C-168 HR-40 to 85T659108
CU NIPDAULevel-3-260C-168 HR-40 to 85T659109
CU NIPDAULevel-3-260C-168 HR-40 to 85T659109
CU NIPDAULevel-3-260C-168 HR-40 to 85TPS
Op Temp (°C)Device Marking
(4/5)
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
65910A1
25-Sep-2013
Samples
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable DeviceStatus
TPS65910A1RSLRACTIVEVQFNRSL482500Green (RoHS
TPS65910A31A1RSLRACTIVEVQFNRSL482500Green (RoHS
TPS65910A31A1RSLTACTIVEVQFNRSL48250Green (RoHS
TPS65910A3A1RSLACTIVEVQFNRSL4860Green (RoHS
TPS65910A3A1RSLRACTIVEVQFNRSL482500Green (RoHS
TPS65910AA1RSLACTIVEVQFNRSL4860Green (RoHS
TPS65910AA1RSLRACTIVEVQFNRSL482500Green (RoHS
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Package Type Package
(1)
Drawing
Pins Package
Qty
Eco Plan
(2)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
Lead/Ball FinishMSL Peak Temp
(3)
CU NIPDAULevel-3-260C-168 HR-40 to 85TPS
CU NIPDAULevel-3-260C-168 HR-40 to 8565910
CU NIPDAULevel-3-260C-168 HR-40 to 8565910
CU NIPDAULevel-3-260C-168 HR-40 to 85T65910
CU NIPDAULevel-3-260C-168 HR-40 to 85T65910
CU NIPDAULevel-3-260C-168 HR-40 to 85T65910A
CU NIPDAULevel-3-260C-168 HR-40 to 85T65910A
Op Temp (°C)Device Marking
(4/5)
65910A1
A31A1
A31A1
A3A1
A3A1
A1
A1
25-Sep-2013
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Samples
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
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