Texas Instruments TPS65680 User Manual

ADVANCE INFORMATION

User's Guide

SLVUBB1–November 2017

How to Use the TPS65680 Evaluation Module

The TPS65680EVM is an evaluation tool for the TPS65680 18-Channel Pattern-Programmable Level
Shifter with Overcurrent Protection for use in large format liquid-crystal display (LCD) display applications

such as TVs and monitors. The TPS65680 supports up to twelve high-voltage clock (GCK) outputs in
charge-sharing or gate-voltage shaping configuration, six high-voltage control outputs for generating start,
clear and reset, and low frequency signals and panel discharge. The evaluation module with its graphical
user interface (GUI) enables the programming of the device from a Microsoft®Windows®7 or 10 PC and
provides easy access to all 18 outputs, 3 supplies and logic inputs.

This user's guide describes the characteristics, operation and use of the TPS65680 evaluation module
(EVM) and its drive software. This EVM contains TI's 18-channel pattern-programmable level shifter with
overcurrent protection IC TPS65680. The user's guide includes EVM specifications, the recommended test
setup (hardware and software), the schematic diagram, the bill of materials, and the board layouts.

All typical characteristics measurements in the TPS65680 data sheet were done with this evaluation
module.

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How to Use the TPS65680 Evaluation Module

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Contents

1 Introduction ................................................................................................................... 3

1.1 Requirements ....................................................................................................... 3

1.2 Applications.......................................................................................................... 3

1.3 Features.............................................................................................................. 4

2 TPS65680 EVM Electrical and Performance Specifications ........................................................... 4

3 TPS65680 EVM Schematic ................................................................................................ 5

4 Connector and Test Point Descriptions................................................................................... 6

4.1 Supply Connectors ................................................................................................. 6

4.2 Input Connectors.................................................................................................... 7

4.3 Level-Shifter Output Connectors.................................................................................. 7

4.4 Additional Jumpers and Connectors ............................................................................. 8

5 Test Setup .................................................................................................................... 8

5.1 EVM Operation...................................................................................................... 8

5.2 Software Setup to Change the Output Voltages and Configuration.......................................... 9

5.3 Hardware Setup..................................................................................................... 9

5.4 Software Operation................................................................................................. 9

6 TPS65680 EVM Assembly Drawings and Layout...................................................................... 11

7 Bill of Materials ............................................................................................................. 14

1 TPS65680 EVM Schematic ................................................................................................ 5

2 Two- and Four-Terminal Connection...................................................................................... 6

3 TPS65680 Software Window............................................................................................. 10

4 TPS65680 EVM Top Composite ......................................................................................... 11

5 TPS65680 EVM Top Layer ............................................................................................... 12

6 TPS65680 EVM Bottom Layer (Bottom View).......................................................................... 13

1 TPS65680 EVM Electrical and Performance Specifications........................................................... 4

2 TPS65680 EVM Bill of Materials ......................................................................................... 14

Trademarks

Microsoft, Windows are registered trademarks of Microsoft Corporation.
All other trademarks are the property of their respective owners.

List of Figures

List of Tables

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ADVANCE INFORMATION

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1 Introduction

The TPS65680 EVM uses the TPS65680 device to deliver 18 high-voltage level-shifter output channels to
support the high-voltage gate signals of gate-in-array (GOA) or gate-in-panel (GIP) LCD displays. The
EVM makes it easy to examine the programmability and performance of the TPS65680 device.

1.1 Requirements

The IC on the EVM is not programmed and the outputs will only toggle after a pattern is loaded. The EVM
comes with the USB2ANY interface adapter and the connectors. For programming the device, you
additionally must have a host computer, and a DC power supply. To operate the level shifters, 2 square
wave outputs of a frequency generator or microcontroller are necessary.

1.1.1 Power Supplies

In order to operate this EVM, 3 DC power supplies, PS1, PS2, and PS3, with the following requirements
are needed:

• PS1 to supply VIN: 2.7 V to 5.5 V capable of 0.5 A

• PS2 to supply VGL: –18 V to –4 V capable of 1 A

• PS3 to supply VGH: 9 V to 40 V capable of 1 A

1.1.2 Digital Inputs

The output signals of a gate signal level shifter on an LCD TFT need to be synchronized to the timing
controller that delivers the image content. To keep TPS65680 synchronised to the timing controller
signals, just 2 digital input signals are necessary:

• LN_CLK is the input signal for the TPS65680 internal PLL. This fixed frequency signal is often set to

the line frequency.

• A rising edge on LS_START starts the programmed pattern from the programmed start address. This

fixed frequency signal is normally set to the frame frequency, for example; 60 Hz, 120 Hz, 240 Hz, and
so forth.

Introduction

1.1.3 Host Computer

A computer with a USB port is required program the TPS65680 on the EVM. The TPS65680 software runs
on a personal computer (PC) and communicates with the EVM through a USB port.

The minimum requirements for the PC are:

• Microsoft Windows 7 or 10 operating system

• 1 USB port

• A minimum of 280MB of free hard disk space (610MB recommended)

• A minimum of 512MB of RAM

1.1.4 Software

Texas Instruments provides the software necessary to program the TPS65680 and evaluate the IC
functionality. After you are approved, download the software and install it on your computer.

In addition to ease the first start with the device, TI provides some standard patterns and a How-To-Start
Video. All of these are included in your 'mySecure Software' folder which included this user's guide.

1.2 Applications

• LCD and OLED panels using GIP and GOA technology

• TV, monitor, notebook, and tablet PC

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Introduction

1.3 Features

• Eases design by providing a simple way to evaluate TPS65680

• Includes pattern examples to ease first evaluation

• How-to video available for the first programming steps

• The added interface board (USB2ANY) connects the EVM to a Microsoft Windows 7 or 10 PC

• This tool is tested and includes the graphical user interface (GUI) as well as the hardware and software

user's guide

• Power and sense connections available on power supply inputs

• GUI enables programmability

• Double-sided, two-active-layer printed-circuit board (PCB) with all components on the top side

2 TPS65680 EVM Electrical and Performance Specifications

Table 1 lists the EVM electrical and performance specifications.

Table 1. TPS65680 EVM Electrical and Performance Specifications

Parameter Test Conditions MIN TYP MAX Unit

Supply

V

I

V

(VGL)

V

(VGH)

Logic Signal Requirements (LS_CNTRL, LS_START, LN_CLK, SCL, SDA)

V

IH

V

IL

Operating input voltage on VIN pin 2.7 5.5 V
Operating input voltage on VGL1 and

VGL2 pins
Operating input voltage on VGH pin 9 40 V

Undervoltage lockout threshold (VI)

Undervoltage lockout threshold
(V

)

(VGL)

Undervoltage lockout threshold
(V

)

(VGH)

VIrising 2.55 2.6 2.7 V
VIfalling 2.45 2.5 2.55 V
V

rising –3 –2.5 –2 V

(VGL)

V

falling –4 –3.5 –3 V

(VGL)

V

rising 6 7 8 V

(VGH)

V

falling 3.8 4 4.2 V

(VGH)

High-level input voltage 1.25 V
Low-level input voltage 0.55 V

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–18 –4 V

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VIN

GND

S+

5

4

1
2
3

6

J1

VGH

GND

S+

5

4

1
2
3

6

J2

VGL

GND

S+

5

4

1
2
3

6

J3

S-

S-

S-

TP1

TP2

SCL

SDA

4

1
2
3

J9

OTP_LDO

GND

4

1
2
3

J6

LS_CNTRL

GND

4

1
2
3

J5

LS_START

GND

4

1
2
3

J4

LN_CLK

GND

GND

GND

GND

GND

GND

GND

GND

1

2

3

J49

10µF

C1

2.2µFC32.2µF

C2

2.2µFC52.2µF

C4

1

2

3

J48

CS1

CS2

CS

GVS

CS

GVS

1.00k

R2

1.00k

R1

1.00k

R3

GND

GND

GND

GNDGND

GND GND

2.2µF

C8

GND

GND

GND

1

2

3

J27

C

RC

1000pFC26

1000pFC25

GND

GND

6

4

5

S2

G12AP

1

2

3

J52

GND

VIN

LS_CNTRL_SW

LS_CNTRL_SW

1 2

J50

GCK9

GND

GND

GCK9

1

2

3

J25

C

RC

1000pFC24

1000pFC23

GND

GCK8

GND

GND

1

2

3

J23

C

RC

1000pFC22

1000pFC21

GND

GCK7

GND

GND

1

2

3

J29

C

RC

1000pFC28

1000pFC27

GND

GCK10

GND

GND

1

2

3

J31

C

RC

1000pFC30

1000pFC29

GND

GCK11

GND

GND

1

2

3

J33

C

RC

1000pFC32

1000pFC31

GND

GCK12

GND

GND

1

2

3

J35

C

RC

1000pFC34

1000pFC33

GND

GSP1

GND

GND

123

J11

C

RC

100

R6

1000pF

C10

1000pF

C9

GND

GCK 1

GND

GND

123

J13

C

RC

1000pF

C12

1000pF

C11

GND

GCK 2

GND

GND

123

J15

C

RC

1000pF

C14

1000pF

C13

GND

GCK 3

GND

GND

123

J17

C

RC

1000pF

C16

1000pF

C15

GND

GCK 4

GND

GND

123

J19

C

RC

1000pF

C18

1000pF

C17

GND

GCK 5

GND

GND

123

J21

C

RC

1000pF

C20

1000pF

C19

GND

GCK 6

GND

GND

GCK1

GCK2

GCK3

GCK4

GCK5

GCK6

GCK7

GCK8

GCK10

GCK11

GCK12

GSP1

123

J39

C

RC

1000pF

C38

1000pF

C37

GCP

GND

GND

GND

123

J41

C

RC

1000pF

C40

1000pF

C39

GPP 1

GND

GND

GND

123

J43

C

RC

1000pF

C42

1000pF

C41

GPP 2

GND

GND

GND

123

J45

C

RC

1000pF

C44

1000pF

C43

VSS

GND

GND

GND

1

2

3

J37

C

RC

1000pFC36

1000pFC35

GND

GSP2

GND

GND

GSP2

GCP

GGP1

GGP2

VSS

0.01µF

C45

412

3

J12

412

3

J14

412

3

J16

412

3

J18

412

3

J20

412

3

J22

4

1

2

3

J24

4

1

2

3

J26

4

1

2

3

J28

4

1

2

3

J30

4

1

2

3

J32

4

1

2

3

J34

4

1

2

3

J36

4

1

2

3

J38

412

3

J40

412

3

J42

412

3

J44

412

3

J46

220µF

C46

GND

220µF

C47

GND

220µF

C48

GND

VGL

VGH

VIN

10k

R24

10k

R25

VIN

12

J5412J5512J5612J5712J5812J5912J6012J6112J6212J6312J6412J65

0

R27

0

R26

GNDGND

GCK 1

GCK 2

GCK 3

GCK 4

GCK 5

GCK 6

GCK 7

GCK 8

GCK 9

GCK 10

GCK 11

GCK 12

100

R7

100

R8

100

R9

100

R10

100

R11

100

R12

100

R13

100

R14

100

R15

100

R16

100

R17

100

R18

100

R19

100

R20

100

R21

100

R22

100

R23

1000pF

C50

1000pF

C49

2.2µF

C7

2.2µF

C6

GND

GND

VGL

NC1NC

3

IN4OUT

5

2

GND

U2
TPS71533DCKRG4

0

R4

0.1µF

C51

0.47µF

C52

3V3

LDO

EXT_3V3

VIN

GND

EXT_3V3

3.3V

1
2
3

J7

EXT_3V3

1
2
3

J10

GND

3V3

I2C_SEL

GND

I2C_SEL

3.3V

SCL

1

SDA

2

LN_CLK

3

LS_CNTRL

4

LS_START

5

I2C_SEL

6

OTP_LDO

7

VIN

8

VGL1

9

GGP2

10

GGP1

11

VSS

12

GCP

13

GCK12

14

GCK11

15

GCK10

16

GCK9

17

GCK8

18

GCK7

19

CS2

20

CS1

21

GCK6

22

GCK5

23

GCK4

24

GCK3

25

GCK2

26

GCK1

27

GSP2

28

GSP1

29

VGH

30

GND

31

PLLC

32

PAD

33

TPS65680RSMR

U1

12
34
56
78
910

J53

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TPS65680 EVM Schematic

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3 TPS65680 EVM Schematic

Figure 1 is for reference only; see the bill of materials in Table 2 for specific values.

Figure 1. TPS65680 EVM Schematic

Power

Supply

EVM

+

SNS +

SNS -

-

S +

S -

VIN

GND

Power

Supply

EVM

+

SNS +

SNS -

-

S +

S -

VIN

GND

2-wire connection

4-wire connection

ADVANCE INFORMATION

Connector and Test Point Descriptions

4 Connector and Test Point Descriptions

4.1 Supply Connectors

4.1.1 J1 – VIN, Input Sense, and GND Connector

This header is the connection of the input power supply, VI, and its sense connections. The power supply
must be connected between pins 1 and 2 (VIN) and pins 5 and 6 (GND). Twist the leads to the input
supply and keep them as short as possible. The input voltage must be between 2.7 V and 5.5 V.

4.1.2 J2 – VGH, Input Sense, and GND Connector

This header is the connection of the power supply, V
must be connected between pins 1 and 2 (VGH) and pins 5 and 6 (GND). Twist the leads to the input
supply and keep them as short as possible. The input voltage must be between 9 V and 40 V.

4.1.3 J3 – VGL, Input Sense, and GND Connector

This header is the connection of the power supply, V
must be connected between pins 1 and 2 (VGL) and pins 5 and 6 (GND). Twist the leads to the input
supply and keep them as short as possible. The input voltage must be between –18 V and –4 V.

Use the middle two pins of the input connectors to sense the input voltage and make a four-terminal
connection. Four-terminal connections are more accurate than two-terminal connections. Figure 2 shows
the setup for two-terminal and four-terminal connections.

, and its sense connections. The power supply

(VGH)

and its sense connections. The power supply

(VGL)

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Figure 2. Two- and Four-Terminal Connection

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