Texas Instruments TPS65185, TPS651851 Datasheet

I/O

Control

From Input

Supply

(3 V to 6 V)

DCDC1

From Input

Supply

(3 V to 6 V)

VPOS

LDO1

VEE_D VEE_DRV

VEE_FB

Negative

Charge

Pump

VCOM

VCOM_PANEL

VNEG

VCOM

Temperature

Sensor

VIN

VB_SW

DCDC2

VN_SW

VDDH_D VDDH_DRV

VDDH_FB

Positive Charge

Pump

LDO2

VIN3P3

Load Switch

V3P3

Product Folder

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Technical Documents

Tools & Software

Support & Community

TPS65185, TPS651851

SLVSAQ8G –FEBRUARY 2011–REVISED SEPTEMBER 2017

TPS65185x PMIC for E Ink® Vizplex™ Enabled Electronic Paper Display

1 Features

• Single Chip Power-Management Solution for E Ink®Vizplex™ Electronic Paper (E-Paper) Displays

• Generates Positive and Negative Gates, and Source Driver Voltages and Back-Plane Bias From a Single, Low-Voltage Input Supply

• Supports 9.7-Inch and Larger Panel Sizes

• 3-V to 6-V Input Voltage Range

• Boost Converter for Positive Rail Base

• Inverting Buck-Boost Converter for Negative Rail Base

• Two Adjustable LDOs for Source Driver Supply – TPS65185 LDO1: 15 V, 120 mA (VPOS) – TPS65185 LDO2: –15 V, 120 mA (VNEG) – TPS651851 LDO1: 15 V, 200 mA at

VIN≥ 3.6 V (VPOS)

– TPS651851 LDO2: –15 V, 200 mA at

VIN≥ 3.6 V (VNEG)

• Accurate Output Voltage Tracking – VPOS – VNEG = ±50 mV

• Two Charge Pumps for Gate Driver Supply – CP1: 22 V, 15 mA (VDDH) – CP2: –20 V, 15 mA, (VEE)

• Adjustable VCOM Driver for Accurate PanelBackplane Biasing

– 0 V to –5.11 V – ± 1.5% accuracy (±10 mV) – 9-Bit Control (10-mV Nominal Step Size)

• Active Discharge on All Rails

• Integrated 10-Ω, 3.3-V Power Switch for Disabling System Power Rail to E-Ink Panel

2 Applications

• Power Supply for Active Matrix E Ink Vizplex Panels

• Electronic Paper Display (EPD) Power Supplies

• E-Book Readers

• Dual-Display Phone and Tablets

• Application Processors With Integrated or Software Timing Controller (OMAP™)

3 Description

The TPS65185x device is a single-chip power supply designed to for E Ink Vizplex displays used in portable e-reader applications, and the device supports panel sizes up to 9.7 inches and greater. Two high efficiency DC-DC boost converters generate ±16-V rails that are boosted to 22 V and –20 V by two change pumps to provide the gate driver supply for the Vizplex panel. Two tracking LDOs create the ±15-V source driver supplies that support up to 120/200 mA (TPS65185/TPS651851) of output current. All rails are adjustable through the I2C interface to accommodate specific panel requirements.

Device Information

PART NUMBER PACKAGE BODY SIZE (NOM)

TPS65185

TPS651851 RSL (48) 6.00 mm × 6.00 mm (1) For all available packages, see the orderable addendum at

the end of the data sheet.

RGZ (48) 7.00 mm × 7.00 mm RSL (48) 6.00 mm × 6.00 mm

(1)

Typical Application Schematic

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

TPS65185, TPS651851

SLVSAQ8G –FEBRUARY 2011–REVISED SEPTEMBER 2017

www.ti.com

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description ............................................................. 1

4 Revision History..................................................... 2

5 Description (continued)......................................... 4

6 Pin Configuration and Functions......................... 4

7 Specifications......................................................... 7

7.1 Absolute Maximum Ratings ...................................... 7

7.2 ESD Ratings.............................................................. 7

7.3 Recommended Operating Conditions....................... 7

7.4 Thermal Information.................................................. 8

7.5 Electrical Characteristics........................................... 8

7.6 Timing Requirements: Data Transmission.............. 12

7.7 Typical Characteristics............................................ 14

8 Detailed Description............................................ 17

8.1 Overview ................................................................. 17

8.2 Functional Block Diagram....................................... 18

8.3 Feature Description................................................. 19

8.4 Device Functional Modes........................................ 27

8.5 Programming........................................................... 29

8.6 Register Maps......................................................... 31

9 Application and Implementation ........................ 49

9.1 Application Information............................................ 49

9.2 Typical Application.................................................. 49

10 Power Supply Recommendations ..................... 51

11 Layout................................................................... 52

11.1 Layout Guidelines ................................................. 52

11.2 Layout Example .................................................... 52

12 Device and Documentation Support................. 53

12.1 Device Support...................................................... 53

12.2 Documentation Support ........................................ 53

12.3 Receiving Notification of Documentation Updates 53

12.4 Community Resources.......................................... 53

12.5 Trademarks........................................................... 53

12.6 Electrostatic Discharge Caution............................ 53

12.7 Glossary................................................................ 53

13 Mechanical, Packaging, and Orderable

Information........................................................... 53

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision F (June 2017) to Revision G Page

• Added the load switch and updated the negative and positive charge pumps in the Typical Application Schematic figure . 1

• Added capacitor connection to the pin description for INT_LDO, VB, VCOM, VCOM_PWR, VDDH_D, VEE_D, VIN,

VIN_P, VN, VNEG, VNEG_IN, VPOS, VPOS_IN, VREF in the Pin Functions table............................................................. 5

• Changed the Power-Up and Power-Down Timing Diagram ................................................................................................ 13

• Changed the Functional Block Diagram............................................................................................................................... 18

• Changed the schematic in the Typical Application section.................................................................................................. 49

Changes from Revision E (February 2017) to Revision F Page

• Updated pin out drawing to match Pin Functions table.......................................................................................................... 4

Changes from Revision D (December 2016) to Revision E Page

• Changed changed the maximum input voltage for TPS651851 from 5.9 V to 6 V................................................................ 7

• Changed the VINrange to the V

OUTTOL

and V

parameters in the Electrical Characteristics table..................................... 9

DIFF

• Changed the Electrostatic Discharge Caution statement..................................................................................................... 53

Changes from Revision C (August 2015) to Revision D Page

• Added TPS651851 device to the data sheet.......................................................................................................................... 1

• Added the input voltage range for TPS651851 ...................................................................................................................... 1

• Added TPS651851 LDO1 and LDO2 current limit of 200 mA................................................................................................ 1

• Updated the switch current limit to 2.5 A on DCDC1 for TPS651851 ................................................................................... 8

• Updated the LDO1 ILOAD current limit for TPS651851 ........................................................................................................ 9

• Updated the LDO1 ILIMIT current limit for TPS651851 ........................................................................................................ 9

Product Folder Links: TPS65185

TPS65185, TPS651851

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• Updated the LDO2 ILOAD current range for different VIN conditions .................................................................................. 9

• Updated the LDO2 ILIMIT output current limit to different VIN conditions............................................................................. 9

• Updated the output voltage range (VDDH_OUT) conditions on charge pump 1 ................................................................ 10

• Added the ILOAD current range option for TPS651851 on CP1 ........................................................................................ 10

• Added the ILOAD current range option for TPS651851 on CP2 ........................................................................................ 10

• Added Receiving Notification of Documentation Updates to Device and Documentation Support section ......................... 53

Changes from Revision B (October 2011) to Revision C Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and

Mechanical, Packaging, and Orderable Information section.................................................................................................. 1

SLVSAQ8G –FEBRUARY 2011–REVISED SEPTEMBER 2017

Product Folder Links: TPS65185

36 VDDH_DRV1VREF

37VDDH_IN 24 VIN_P

35 VDDH_DIS2INT

38N/C 23 PWR_GOOD

34 VDDH_D3VNEG

39N/C 22 PBKG

33 VDDH_FB4VNEG_IN

40VB_SW 21 PWRUP

32 PGND25WAKEUP

41PGND1 20 N/C

31 VEE_FB6DGND

42VB 19 VPOS_DIS

30 VEE_D7INT_LDO

43VPOS_IN 18 SDA

29 VEE_DIS8AGND1

44VPOS 17 SCL

28 VEE_DRV9VNEG_DIS

45VIN3P3 16 VCOM_PWR

27 VEE_IN10VIN

46V3P3 15 VCOM

26 VN11N/C

47TS 14 VCOM_DIS

25 VN_SW12VCOM_CTRL

48AGND2 13 N/C

Not to scale

Thermal

Pad

TPS65185, TPS651851

SLVSAQ8G –FEBRUARY 2011–REVISED SEPTEMBER 2017

www.ti.com

5 Description (continued)

Accurate back-plane biasing is provided by a linear amplifier that can be adjusted from 0 V to –5.11 V with 9-bit control through the serial interface; it can source or sink current depending on panel condition. The TPS65185x supports automatic panel kickback voltage measurement, which eliminates the need for manual VCOM calibration in the production line. The measurement result can be stored in non-volatile memory to become the new VCOM power-up default value.

TPS65185 is available in two packages, a 48-pin 7-mm × 7-mm2VQFN (RGZ) with 0.5-mm pitch, and a 48-pin 6-mm × 6-mm2VQFN (RSL) with 0.4-mm pitch. The TPS651851 is available in a 48-pin 6-mm × 6-mm2VQFN (RSL) with 0.4-mm pitch.

6 Pin Configuration and Functions

RGZ Package and RSL Package

48-Pin VQFN With Exposed Thermal Pad

Top View

Product Folder Links: TPS65185

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SLVSAQ8G –FEBRUARY 2011–REVISED SEPTEMBER 2017

Pin Functions

NAME NO.

AGND1 8 — Analog ground for general analog circuitry. AGND2 48 — Reference point to external thermistor and linearization resistor. DGND 6 — Digital ground. Connect to ground plane. INT 2 O Open drain interrupt pin (active low). INT_LDO 7 O Filter pin for 2.7-V internal supply. Connect a 4.7-µF capacitor from this pin to ground.

N/C

11, 13, 20,

38, 39 PBKG 22 — PGND1 41 — Power ground for DCDC1.

PGND2 32 — Power ground for CP1 (VDDH) and CP2 (VEE) charge pumps. PWR_GOOD 23 O PWRUP 21 I Power-up pin. Pull this pin high to power up all output rails.

SCL 17 I Serial interface (I2C) clock input. SDA 18 I/O Serial interface (I2C) data input/output.

TS 47 I V3P3 46 O Output pin of 3.3-V power switch. VB 42 I VB_SW 40 O Boost converter switch out (DCDC1).

VCOM 15 O Filter pin for panel common-voltage driver. Connect a 4.7-µF capacitor from this pin to ground. VCOM_CTRL 12 I

VCOM_DIS 14 I

VCOM_PWR 16 I

VDDH_D 34 O

VDDH_DIS 35 I VDDH_DRV 36 O Driver output pin for positive charge pump (CP1).

VDDH_FB 33 I Feedback pin for positive charge pump (CP1). VDDH_IN 37 I Input supply pin for positive charge pump (CP1).

VEE_D 30 O

VEE_DIS 29 I VEE_DRV 28 O Driver output pin for negative charge pump (CP2).

VEE_FB 31 I Feedback pin for negative charge pump (CP2). VEE_IN 27 I Input supply pin for negative charge pump (CP2) (VEE). VIN 10 I Input power supply to general circuitry. Connect a 10-µF capacitor from this pin to ground. VIN3P3 45 I Input pin to 3.3-V power switch.

VIN_P 24 I

VN 26 I

I/O DESCRIPTION

— Not internally connected.

Die substrate. Connect to the VN pin (–16 V) with a short, wide trace. A wide copper trace improves heat dissipation.

Open-drain power good output pin. Pin is pulled low when one or more rails are disabled or not in regulation. DCDC1, DCDC2, and VCOM have no effect on this pin.

(1)

Thermistor input pin. Connect a 10-kΩ NTC thermistor and a 43-kΩ linearization resistor between this pin and AGND.

Feedback pin for boost converter (DCDC1) and supply for VPOS LDO and VDDH charge pump. Connect a 4.7-µF capacitor from this pin to ground.

VCOM enable. Pull this pin high to enable the VCOM amplifier. When pin is pulled low and VN is enabled, VCOM discharge is enabled.

(2)

Discharge pin for VCOM. Connect to ground to discharge VCOM to ground whenever VCOM is disabled. Leave floating if discharge function is not desired.

Internal supply input pin to VCOM buffer. Connect to the output of DCDC2, and connect a 4.7-µF capacitor from this pin to ground.

Base voltage output pin for positive charge pump (CP1). Connect a 100-nF capacitor from this pin to ground.

Discharge pin for VDDH. Connect to VDDH to discharge VDDH to ground whenever the rail is disabled. Leave floating if discharge function is not desired.

Base voltage output pin for negative charge pump (CP2). Connect a 100-nF capacitor from this pin to ground.

Discharge pin for VEE. Connect a resistor from VEE _DIS to VEE to discharge VEE to ground whenever the rail is disabled. Leave floating if discharge function is not desired.

Input power supply to inverting buck-boost converter (DCDC2). Connect a 10-µF capacitor from this pin to ground.

Feedback pin for inverting buck-boost converter (DCDC2) and supply for VNEG LDO and VEE charge pump. Connect a 4.7-µF capacitor from this pin to ground.

(1) There will be 0-ns of deglitch for PWRx. (2) There will be 62.52-µs of deglitch for VCOM_CTRL.

Product Folder Links: TPS65185

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SLVSAQ8G –FEBRUARY 2011–REVISED SEPTEMBER 2017

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Pin Functions (continued)

NAME NO.

VNEG 3 O

VNEG_DIS 9 O VNEG_IN 4 I Input pin for LDO2 (VNEG). Connect a 4.7-µF capacitor from this pin to ground.

VN_SW 25 O Inverting buck-boost converter switch out (DCDC2). VPOS 44 O Positive supply output pin for panel source drivers. Connect a 4.7-µF capacitor from this pin to ground.

VPOS_DIS 19 I VPOS_IN 43 I Input pin for LDO1 (VPOS). Connect a 4.7-µF capacitor from this pin to ground.

VREF 1 O Filter pin for 2.25-V internal reference to ADC. Connect a 4.7-µF capacitor from this pin to ground.

WAKEUP 5 I

Thermal Pad — —

(3) There will be 93.75-µs of deglitch for WAKEUP.

I/O DESCRIPTION

Negative supply output pin for panel source drivers. Connect a 4.7-µF capacitor from this pin to ground.

Discharge pin for VNEG. Connect to VNEG to discharge VNEG to ground whenever the rail is disabled. Leave floating if discharge function is not desired.

Discharge pin for VPOS. Connect a resistor from VPOS_DIS to VPOS to discharge VPOS to ground whenever the rail is disabled. Leave floating if discharge function is not desired.

Wake up pin (active high). Pull this pin high to wake up from sleep mode. The device accepts I2C commands after WAKEUP pin is pulled high but power rails remain disabled until PWRUP pin is pulled

(3)

high. The thermal pad is internally connected to the PBKG pin. Connect the thermal pad to the VN pin with a

short, wide trace. A wide copper trace improves heat dissipation. Do not connect the thermal pad to ground.

Product Folder Links: TPS65185

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SLVSAQ8G –FEBRUARY 2011–REVISED SEPTEMBER 2017

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

Input voltage at VIN Ground pins to system ground –0.3 0.3 V Voltage at SDA, SCL, WAKEUP, PWRUP, VCOM_CTRL, VDDH_FB, VEE_FB, PWR_GOOD,

nINT Voltage on VB, VB_SW, VPOS_IN, VPOS_DIS, VDDH_IN –0.3 20 V VDDH_DIS –0.3 30 V Voltage on VN, VEE_IN, VCOM_PWR, VNEG_DIS, VNEG_IN –20 0.3 V Voltage from VIN_P to VN_SW –0.3 30 V Voltage on VCOM_DIS –5 0.3 V VEE_DIS –30 0.3 V Peak output current Internally limited mA

Continuous total power dissipation 2 W TJOperating junction temperature –10 125 °C TAOperating ambient temperature T

Storage temperature –65 150 °C

stg

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to network ground terminal. (3) It is recommended that copper plane in proper size on board be in contact with die thermal pad to dissipate heat efficiently. Thermal pad

is electrically connected to PBKG, which is supposed to be tied to the output of buck-boost converter. Thus wide copper trace in the

buck-boost output will help heat dissipated efficiently.

(2)

, VIN_P, VIN3P3 –0.3 7 V

(3)

(1)(2)

MIN MAX UNIT

–0.3 3.6 V

–10 85 °C

7.2 ESD Ratings

(ESD)

Electrostatic discharge

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 Charged-device model (CDM), per JEDEC specification JESD22-C101

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

(1)

(2)

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

Input voltage at VIN, VIN_P, VIN3P3 3 3.7 6 V Voltage at SDA, SCL, WAKEUP, PWRUP, VCOM_CTRL, VDDH_FB,

VEE_FB, PWR_GOOD, nINT

Operating ambient temperature –10 85 °C Operating junction temperature –10 125 °C

0 3.6 V

VALUE UNIT

±2000

±500

Product Folder Links: TPS65185

TPS65185, TPS651851

SLVSAQ8G –FEBRUARY 2011–REVISED SEPTEMBER 2017

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7.4 Thermal Information

TPS65185 TPS651851

THERMAL METRIC

(1)

UNITRGZ (VQFN) RSL (VQFN) RSL (VQFN)

48 PINS 48 PINS 48 PINS

θJA

θJC(top)

θJB

θJC(bot)

Junction-to-ambient thermal resistance 30 30 30 °C/W Junction-to-case (top) thermal resistance 15.6 16.2 16.2 °C/W Junction-to-board thermal resistance 6.6 5.1 5.1 °C/W Junction-to-top characterization parameter 0.2 0.2 0.2 °C/W Junction-to-board characterization parameter 6.6 5.1 5.1 °C/W Junction-to-case (bottom) thermal resistance 0.9 0.9 0.9 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.5 Electrical Characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

INPUT VOLTAGE

UVLO

HYS

INPUT CURRENT

STD

SLEEP

INTERNAL SUPPLIES

NT_LDO

INT_LDO

REF

DCDC1 (POSITIVE BOOST REGULATOR)

OUT

DS(ON)

LIMIT

DCDC1

ESR Output capacitor ESR 20 mΩ

DCDC2 (INVERTING BUCK-BOOST REGULATOR)

OUT

Input voltage range 3 3.7 6 V Undervoltage lockout threshold VINfalling 2.9 V Undervoltage lockout hysteresis VINrising 400 mV

Operating quiescent current into VINDevice switching, no load 5.5 mA Operating quiescent current into VINDevice in standby mode 130 µA Shutdown current Device in sleep mode 3.5 10 µA

Internal supply 2.7 V Nominal output capacitor Capacitor tolerance ±10% 1 4.7 µF Internal supply 2.25 V Nominal output capacitor Capacitor tolerance ±10% 3.3 4.7 µF

Input voltage range 3 3.7 6 V Power good threshold Fraction of nominal output voltage 90% Power good time-out Not tested in production 50 ms Output voltage range 16 V DC set tolerance –4.5% 4.5% Output current 250 mA MOSFET on resistance VIN= 3.7 V 350 mΩ Switch current limit (TPS65185) 1.5 Switch current limit (TPS651851) 2.5 Switch current accuracy –30% 30% Switching frequency 1 MHz Inductor 2.2 µH Nominal output capacitor Capacitor tolerance ±10% 1 2 × 4.7 µF

Input voltage range 3 3.7 6 V Power good threshold Fraction of nominal output voltage 90% Power good time-out Not tested in production 50 ms Output voltage range –16 V DC set tolerance –4.5% 4.5% Output current 250 mA

Product Folder Links: TPS65185

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SLVSAQ8G –FEBRUARY 2011–REVISED SEPTEMBER 2017

Electrical Characteristics (continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DS(ON)

LIMIT

DCDC1

ESR Capacitor ESR 20 mΩ

LDO1 (VPOS)

POS_IN

SET

INTERVAL

OUTTOL

DROPOUT

LOADREG

LOAD

LIMIT

DIS

LDO1

LDO2 (VNEG)

NEG_IN

SET

INTERVAL

OUTTOL

DROPOUT

LOADREG

LOAD

LIMIT

DIS

LDO2

MOSFET on resistance VIN= 3.7 V 350 mΩ Switch current limit 1.5 A Switch current accuracy –30% 30% Inductor 4.7 µH Nominal output capacitor Capacitor tolerance ±10% 1 3 × 4.7 µF

Input voltage range 15.2 16 16.8 V Power good threshold Fraction of nominal output voltage 90% Power good time-out Not tested in production 50 ms

Output voltage set value

VIN= 16 V, VSET[2:0] = 0x3h to 0x6h

14.25 15 V Output voltage set resolution VIN= 16 V 250 mV Output tolerance Dropout voltage I

Load regulation – DC I

= 15 V, I

SET

5.9 V = 120 mA 250 mV

LOAD

= 10% to 90% 1%

LOAD

= 20 mA, 3 V ≤ VIN<

LOAD

–1% 1%

Load current range (TPS65185) VIN≥ 3 V 120

Load current range (TPS651851)

3 V ≤ VIN< 3.6 V 150 VIN≥ 3.6 V 200

Output current limit (TPS65185) VIN≥ 3 V 120

Output current limit (TPS651851)

3 V ≤ VIN< 3.6 V 150

VIN≥ 3.6 V 200 Discharge impedance to ground Enabled when rail is disabled 800 1000 1200 Ω Mismatch to any other RDIS –2% 2% Nominal output capacitor Capacitor tolerance ±10% 1 4.7 µF

Input voltage range 15.2 16 16.8 V Power good threshold Fraction of nominal output voltage 90% Power good time-out Not tested in production 50 ms

Output voltage set value

VIN= –16 V

VSET[2:0] = 0x3h to 0x6h

–15 –14.25 V

Output voltage set resolution VIN= –16 V 250 mV Output tolerance V Dropout voltage I Load regulation – DC I

Load current range

= –15 V, I

SET

= 120 mA 250 mV

LOAD

= 10% to 90% 1%

LOAD

= –20 mA –1% 1%

LOAD

3 V ≤ VIN< 3.6 V (TPS65185 and

TPS651851)

120

VIN≥ 3.6 V (TPS65185 and TPS651851) 200

3 V ≤ VIN< 3.6 V (TPS65185) 180 Output current limit

VIN≥ 3.6 V (TPS65185 and TPS651851) 200 Discharge impedance to ground Enabled when rail is disabled 800 1000 1200 Ω Mismatch to any other RDIS –2% 2% Soft-start time Not tested in production 1 ms Nominal output capacitor Capacitor tolerance ±10% 1 4.7 µF

mA3 V ≤ VIN< 3.6 V (TPS651851) 158

Product Folder Links: TPS65185

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SLVSAQ8G –FEBRUARY 2011–REVISED SEPTEMBER 2017

Electrical Characteristics (continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

LD01 (POS) AND LDO2 (VNEG) TRACKING

DIFF

Difference between VPOS and VNEG

VCOM DRIVER

VCOM

Drive current 15 mA Allowed operating range

Accuracy

COM

Output voltage range –5.11 0 V Resolution 1LSB 10 mV Max number of EEPROM writes V

DIS

VCOM

Input impedance, HiZ state HiZ = 1 150 MΩ Discharge impedance to ground VCOM_CTRL = low, Hi-Z = 0 800 1000 1200 Ω Mismatch to any other R

DIS

Nominal output capacitor Capacitor tolerance ±10% 3.3 4.7 µF

CP1 (VDDH) CHARGE PUMP

DDH_IN

DDH_OUT

LOAD

DIS

Input voltage range 15.2 16 16.8 V Power good threshold Fraction of nominal output voltage 90% Power good time-out Not tested in production 50 ms Feedback voltage 0.998 V Accuracy I

Output voltage range

Load current range (TPS65185) 10 Load current range (TPS651851) 15 Switching frequency 560 kHz Discharge impedance to ground Enabled when rail is disabled 800 1000 1200 Ω Mismatch to any other R

DIS

Driver capacitor 10 nF Output capacitor 1 2.2 µF

CP2 (VEE) NEGATIVE CHARGE PUMP

EE_IN

EE_OUT

LOAD

DIS

Input voltage range 15.2 16 16.8 V Power good threshold Fraction of nominal output voltage 90% Power good time-out Not tested in production 50 ms Feedback voltage –0.994 V Accuracy I Output voltage range V Load current range (TPS65185) 12 Load current range (TPS651851) 15 Switching frequency 560 kHz Discharge impedance to ground Enabled when rail is disabled 800 1000 1200 Ω Mismatch to any other R

DIS

V ≤ VIN< 5.9 V

Outside this range VCOM is shut down

and VCOMF interrupt is set

VCOM[8:0] = 0x07Dh

(–1.25 V), VIN= 3.4 V to 4.2 V, no load

VCOM[8:0] = 0x07Dh

(–1.25 V), VIN= 3 V to 6 V, no load

R10 = 47.5 kΩ

R10 = 41.6 kΩ

R10 = 37 kΩ

= ±15 V,

SET

= ±20 mA, 0°C to 60°C ambient, 3

LOAD

–50 50 mV

–5.5 1 V

–0.8% 0.8%

–1.5% 1.5%

calibration 100

COM

–2% 2%

= 2 mA –2% 2%

LOAD

SET

= 22 V, I

= 25 V, I

= 28 V, I

= 2 mA, R6 = 1MΩ,

LOAD

= 2 mA, R6 = 1MΩ,

LOAD

= 2 mA, R6 = 1MΩ,

LOAD

21 22 23

24 25 26

27 28 29

–2% 2%

= 2 mA –2% 2%

LOAD

SET

= –20 V, I

= 3 mA –21 –20 –19 V

LOAD

–2% 2%

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Product Folder Links: TPS65185

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SLVSAQ8G –FEBRUARY 2011–REVISED SEPTEMBER 2017

Electrical Characteristics (continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

THERMISTOR MONITOR

TMS

Offset V

TMS_HOT

TMS_COOL

TMS_MAX

NTC_PU

LINEAR

ADC ADC TMST

LOGIC LEVELS AND TIMING CHARTERISTICS (SCL, SDA, PWR_GOOD, PWRx, WAKEUP)

(bias)

deglitch

discharge

SCL

OSCILLATOR

OSC

THERMAL SHUTDOWN

SHTDWN

(1) 10-kΩ Murata NCP18XH103F03RB thermistor (1%) in parallel with a linearization resistor (43 kΩ, 1%) are used at TS pin for panel (2) Contact factory for 50-ms, 200-ms or 400-ms option.

(3) Contact TI for alternate address of 0 × 48h.

Driver capacitor 10 nF Nominal output capacitor Capacitor tolerance ±10% 1 2.2 µF

(1)

Temperature to voltage ratio Not tested in production –0.0161 V/°C Offset Temperature = 0°C 1.575 V

TMS

Temp hot trip voltage (T = 50°C) TEMP_HOT_SET = 0x8C 0.768 V Temp hot escape voltage (T = 45°C) TEMP_COOL_SET = 0x82 0.845 V Maximum input level 2.25 V Internal pullup resistor 7.307 kΩ External linearization resistor 43 kΩ ADC resolution Not tested in production, 1 bit 16.1 mV

RES

ADC conversion time Not tested in production 19 µs

DEL

Accuracy Not tested in production –1 1 LSB

TOL

Output low threshold level

IO= 3 mA, sink current

(SDA, nINT, PWR_GOOD) Input low threshold level 0.4 V Input high threshold level 1.2 V Input bias current VIO= 1.8 V 1 µA Deglitch time, WAKEUP pin Not tested in production 500 Deglitch time, PWRUP pin Not tested in production 400 Discharge delay Not tested in production 100

(2)

SCL clock frequency 400 kHz I2C slave address 7-bit address 0 × 68h

(3)

Oscillator frequency 9 MHz Frequency accuracy TA= –40°C to 85°C –10% 10%

Thermal trip point 150 °C Thermal hysteresis 20 °C

temperature measurement.

0.4 V

µs

Product Folder Links: TPS65185

HD;STA

LOW

HD;DAT

SU;DAT

HIGH

SU;STA

HD;STA

SU;STO

BUF

S S

SDA

SCL

TPS65185, TPS651851

SLVSAQ8G –FEBRUARY 2011–REVISED SEPTEMBER 2017

7.6 Timing Requirements: Data Transmission

= 3.6 V ±5%, TA= 25ºC, CL= 100 pF (unless otherwise noted)

BAT

(SCL)

HD;STA

LOW

HIGH

SU;STA

HD;DAT

SU;DAT

SU;STO

BUF

Serial clock frequency 100 400 kHz Hold time (repeated) START condition. After this

period, the first clock pulse is generated.

LOW period of the SCL clock

HIGH period of the SCL clock

Set-up time for a repeated START condition

Data hold time

Data set-up time

Rise time of both SDA and SCL signals

Fall time of both SDA and SCL signals

Set-up time for STOP condition

Bus Free Time Between Stop and Start Condition

Pulse width of spikes that must be suppressed by the input filter

Capacitive load for each bus line

SCL = 100 kHz 4 µs SCL = 400 kHz 600 ns SCL = 100 kHz 4.7 SCL = 400 kHz 1.3 SCL = 100 kHz 4 µs SCL = 400 kHz 600 ns SCL = 100 kHz 4.7 µs SCL = 400 kHz 600 ns SCL = 100 kHz 0 3.45 µs SCL = 400 kHz 0 900 ns SCL = 100 kHz 250 SCL = 400 kHz 100 SCL = 100 kHz 1000 SCL = 400 kHz 300 SCL = 100 kHz 300 SCL = 400 kHz 300 SCL = 100 kHz 4 µs SCL = 400 kHz 600 ns SCL = 100 kHz 4.7 SCL = 400 kHz 1.3 SCL = 100 kHz n/a n/a SCL = 400 kHz 0 50 SCL = 100 kHz 400 SCL = 400 kHz 400

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MIN NOM MAX UNIT

µs

Figure 1. I2C Data Transmission Timing

Product Folder Links: TPS65185

1.8 ms

(1)

100 ms

(2)

STANDBY

ACTIVE

SLEEP

ACTIVE

UDLY1

UDLY2

UDLY3

UDLY4

300 µs (maximum)

DDLY1

DDLY2 UDLY4

UDLY2

UDLY3

DDLY3

DDLY4

UDLY1

VIN

I2C

PWRUP

WAKEUP

VNEG

VEE

VPOS

VDDH

PWR_GOOD

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TPS65185, TPS651851

SLVSAQ8G –FEBRUARY 2011–REVISED SEPTEMBER 2017

(1) Minimum delay time between WAKEUP rising edge and IC ready to accept I2C transaction. (2) The device does not enter the SLEEP state until the final discharge delay time has elapsed.

Note: In this example, the first power-up sequence is started by pulling the PWRUP pin high (rising edge). Power-down is

initiated by pulling the WAKEUP pin low (device enters sleep mode after rails are discharged). The second power-up sequence is initiated by pulling the WAKEUP pin high while the PWRUP pin is also high (power up from sleep to active).

Figure 2. Power-Up and Power-Down Timing Diagram

Product Folder Links: TPS65185

TPS65185, TPS651851

SLVSAQ8G –FEBRUARY 2011–REVISED SEPTEMBER 2017

7.7 Typical Characteristics

Figure 3. Default Power-Up Sequence Figure 4. Default Power-Down Sequence

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VIN= 3.7 V CIN= 100 µF

Figure 5. Inrush Current

VIN= 3 V R

LOAD, VPOS

No Load on VDDH, VEE

Figure 7. Switching Waveforms, VN

= 330 Ω R

LOAD, VNEG

= 330 Ω

VIN= 5 V CIN= 100 µF

Figure 6. Inrush Current

VIN= 3 V R

LOAD, VPOS

No Load on VDDH, VEE

Figure 8. Switching Waveforms, VB

= 330 Ω R

LOAD, VNEG

= 330 Ω

Product Folder Links: TPS65185

-5 0

-4 0

-3 0

-2 0

-1 0

1 0

2 0

3 0

4 0

5 0

0 25 50 75 100 1 25 1 50 1 75

C urr e nt [ m A]

VPOS + VNEG[mV]

IPO S= INEG

IPO S s we ep, INE G= 15m A

IPO S= 15m A, IN EG s wee p

1 1.5 2 2.5 3 3.5 4

VIN3P3[V]

R[ ], (VIN3p3-V3P3)/10mAW

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Typical Characteristics (continued)

TPS65185, TPS651851

SLVSAQ8G –FEBRUARY 2011–REVISED SEPTEMBER 2017

VIN= 3.7 V R

No Load on VDDH, VEE

Figure 9. Switching Waveforms, VN

VIN= 5 V R

No Load on VDDH, VEE

Figure 11. Switching Waveforms, VN

LOAD, VPOS

= 330 Ω R

LOAD, VNEG

= 330 Ω

VIN= 3.7 V R

No Load on VDDH, VEE

Figure 10. Switching Waveforms, VB

VIN= 5 V R

No Load on VDDH, VEE

Figure 12. Switching Waveforms, VB

LOAD, VPOS

= 330 Ω R

LOAD, VNEG

= 330 Ω

VIN= 3.7 V I

Figure 13. 3p3V Switch Impedance

LOAD, V3p3

= 10 mA

VIN= 3.7 V

Product Folder Links: TPS65185

Figure 14. Source Driver Supply Tracking

-2

-1. 5

-1

-0. 5

0. 5

1. 5

0 640 12 80 192 0 256 0 320 0 38 40 44 80 5 12 0

Fo rce d Ki ckba c k V ol tag e [m V]

Measurementerror [LSB]

-5

-4

-3

-2

-1

0 64 128 19 2 25 6 320 384 44 8 512

VC OM CO DE

INL [mV]

-0. 2

-0 .15

-0. 1

-0 .05

0 .05

0. 1

0 .15

0. 2

0 6 4 1 28 1 92 2 56 3 20 38 4 4 48 51 2

V COM CO DE

DNL[LSB]

TPS65185, TPS651851

SLVSAQ8G –FEBRUARY 2011–REVISED SEPTEMBER 2017

Typical Characteristics (continued)

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VIN= 3.7 V R

LOAD, VCOM

= 1 kΩ

Figure 15. VCOM Integrated Non-Linearity

VIN= 3.7 V

Figure 17. Kickback Voltage Measurement Error

VIN= 3.7 V R

LOAD, VCOM

= 1 kΩ

Figure 16. VCOM Differential Non-Linearity

VIN= 3.7 V AVG[1:0] = 00 (Single Measurement)

Time from ACQ Bit Set to ACQC Interrupt Received

Figure 18. Kickback Voltage Measurement Timing

VIN= 3.7 V AVG[1:0] = 11 (Eight Measurements)

Time from ACQ Bit Set to ACQC Interrupt Received

Figure 19. Kickback Voltage Measurement Timing

Product Folder Links: TPS65185

TPS65185, TPS651851

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SLVSAQ8G –FEBRUARY 2011–REVISED SEPTEMBER 2017

8 Detailed Description

8.1 Overview

The TPS65185x device provides two adjustable LDOs, inverting buck-boost converter, boost converter, thermistor monitoring, and flexible power-up and power-down sequencing. The system can be supplied by a regulated input voltage ranging from 3 V to 6 V. The device is characterized across a –10°C to 85°C temperature range, best suited for personal electronic applications.

The I2C interface provides comprehensive features for using the TPS65185x. All rails can be enabled or disabled. Power-up and power-down sequences can also be programmed through the I2C interface, as well as thermistor configuration and interrupt configuration. Voltage adjustment can also be controlled by the I2C interface.

The adjustable LDOs can supply up to 120 mA (TPS65185) and 200 mA (TPS651851) of current. The default output voltages for each LDO can be adjusted through the I2C interface. LDO1 (VPOS) and LDO2 (VNEG) track each other in a way that they are of opposite sign but same magnitude. The sum of VLDO1 and VLOD2 is specified to be less than 50 mV.

There are two charge pumps: where VDDH and VEE are 10 mA and 12 mA (TPS65185) and VDDH and VEE are 15 mA and 15 mA (TPS651851) respectively. These charge pumps boost the DC-DC boost converters ±16-V rails to provide a gate channel supply.

The power good functionality is open-drain output, if any of the four power rails (CP1, CP2, LDO1, LDO2) are not in regulation, encounters a fault, or is disabled the pin is pulled low. PWR_GOOD remains low if one of the rails is not enabled by the host and only after all rails are in regulation PWR_GOOD is released to HiZ state (pulled up by external resistor).

The TPS65185x provides circuitry to bias and measure an external NTC to monitor the display panel temperature in a range from –10°C to 85°C with and accuracy of ±1°C from 0°C to 50°C. Temperature measurement are triggered by the controlling host and the last temperature reading is always stored in the TMST_VALUE register. Interrupts are issued when the temperature exceeds the programmable HOT, or drops below the programmable COLD threshold, or when the temperature has changed by more than a user-defined threshold from the baseline value.

This device has the following two package options:

• TPS65185: 48-Pin, 0.5-mm Pitch, 7 mm × 7 mm × 0.9 mm (QFN) RGZ

• TPS65185 and TPS651851: 48-Pin, 0.4 mm Pitch, 6 mm × 6 mm × 0.9 mm (QFN) RSL

Product Folder Links: TPS65185

TPS65185x

VB_SW

PGND1

VDDH_IN

DCDC1

VIN_P

VN_SW

DCDC2

VDDH_D

VDDH_DRV

VDDH_FB

VDDH_DIS

1 k

VDDH

Charge Pump

PGND2

VDDH_EN

PGND2

LDO1

VPOS_IN

VPOS

VPOS_DIS

1 k

VPOS_EN

PGND2

VEE_IN

VEE_D

VEE_DRV

VEE_FB

VEE_DIS

1 k

VEE

Charge Pump

PGND2

VEE_EN

PGND2

LDO2

VNEG_IN

VNEG

VNEG_DIS

1 k

VNEG_EN

PGND2

PBKG Thermal Pad

PGND2

Temperature

Sensor

AGND2

ADC

TMST_VALUE[7:0]

VIN

Internal LDO

Reference

Voltage

INT_LDO

VCOM

DAC

VCOM[8:0]

VREF

AGND1

VCOM_CTRL

VCOM_DIS

1 k

VCOM_PWR

Gate Driver

V3P3_EN

VIN3P3

V3P3

1 k

Digital Core

6DGND

5WAKEUP

21PWRUP

17SCL

18SDA

INT

PWR_GOOD

TPS65185, TPS651851

SLVSAQ8G –FEBRUARY 2011–REVISED SEPTEMBER 2017

8.2 Functional Block Diagram

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Product Folder Links: TPS65185

TPS65185, TPS651851

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SLVSAQ8G –FEBRUARY 2011–REVISED SEPTEMBER 2017

8.3 Feature Description

8.3.1 Wake-Up and Power-Up Sequencing

The power-up and power-down order and timing is defined by user register settings. The default settings support the E Ink Vizplex panel and typically do not need to be changed.

In SLEEP mode the TPS65185x is completely turned off, the I2C registers are reset, and the device does not accept any I2C transaction. Pull the WAKEUP pin high with the PWRUP pin low and the device enters STANDBY mode which enables the I2C interface. Write to the UPSEQ0 register to define the order in which the output rails are enabled at power-up and to the UPSEQ1 registers to define the power-up delays between rails. Finally, set the ACTIVE bit in the ENABLE register to 1 to execute the power-up sequence and bring up all power rails. Alternatively pull the PWRUP pin high (rising edge).

After the ACTIVE bit has been set, the negative boost converter (VN) is powered up first, followed by the positive boost (VB). The positive boost enable is gated by the internal power-good signal of the negative boost. Once VB is in regulation, it issues an internal power-good signal and after delay time UDLY1 has expired, STROBE1 is issued. The rail assigned to STROBE1 will power up next and after its power-good signal has been asserted and delay time UDLY2 has expired, STROBE2 is issued. The sequence continues until STROBE4 has occurred and the last rail has been enabled.

To power down the device, set the STANDBY bit of the ENABLE register to 1 or pull the PWRUP pin low (falling edge) and the TPS65185x will power down in the order defined by DWNSEQx registers. The delay times DDLY2, DDLY3, and DDLY4 are weighted by a factor of DFCTR which allows the user to space out the power down of the rails to avoid crossing during discharge. DFCTR is located in register DWNSEQ1. The positive boost (VB) is shut down together with the last rail at STROBE4. However, the negative boost (VN) remains up and running for another 100 ms (discharge delay) to allow complete discharge of all rails. After the discharge delay, VN is powered down and the device enters STANDBY or SLEEP mode, depending on the WAKEUP pin.

If either the ACTIVE bit is set or the PWRUP pin is pulled high while the device is powering down, the powerdown sequence (STROBE1-4) is completed first, followed by a power-up sequence. VB and VN may or may not be powered down and the discharge delay may be cut short depending on the relative timing of STROBE4 to the new power-up event.

During power-up, if the STANDBY bit is set or the PWRUP pin is pulled low, the power-up sequence is aborted and the power-down sequence starts immediately.

8.3.2 Dependencies Between Rails

Charge pumps, LDOs, and VCOM driver are dependent on the positive and inverting buck-boost converters and several dependencies exist that affect the power-up sequencing. These dependencies are listed below.

• Inverting buck-boost (DCDC2) must be in regulation before positive boost (DCDC1) can be enabled. Internally, DCDC1 enable is gated by DCDC2 power good.

• Positive boost (DCDC1) must be in regulation before LDO2 (VNEG) can be enabled. Internally LDO2 enable is gated DCDC1 power-good.

• Positive boost (DCDC1) must be in regulation before VCOM can be enabled. Internally VCOM enable is gated by DCDC1 power good.

• Positive boost (DCDC1) must be in regulation before negative charge pump (CP2) can be enabled. Internally CP2 enable is gated by DCDC1 power good.

• Positive boost (DCDC1) must be in regulation before positive charge pump (CP1) can be enabled. Internally CP1 enable is gated by DCDC1 power good.

• LDO2 must be in regulation before LDO1 can be enabled. Internally LDO1 enable is gated by LDO2 power good.

Product Folder Links: TPS65185

UDLY1

ACTIVE bit

WAKEUP high

VN PG VB PG

UDLY2

PG1

STROBE 1 STROBE 2

UDLY3

PG2

STROBE 3

UDLY4

PG3

STROBE 4

PG4

STANDBY bit

WAKEUP low

STROBE 2STROBE 1

DDLY1 DDLY2 DDLY3

STROBE 3 STROBE 4

DDLY4

Discharge DELAY

powers up

1strail

powers up

2ndrail

powers up

3ndrail

powers up

4thrail

powers up

4thrail

powers down

3ndrail

powers down

2ndrail

powers down

1strail

powers down

powers up

TPS65185, TPS651851

SLVSAQ8G –FEBRUARY 2011–REVISED SEPTEMBER 2017

Feature Description (continued)

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8.3.3 Soft Start

TPS65185x supports soft start for all rails, that is, inrush current is limited during startup of DCDC1, DCDC2, LDO1, LDO2, CP1 and CP2. If DCDC1 or DCDC2 are unable to reach power-good status within 50 ms, the corresponding UV flag is set in the interrupt registers, the interrupt pin is pulled low, and the device enters STANDBY mode. LDO1, LDO2, positive and negative charge pumps also have a 50-ms power-good time-out limit. If either rail is unable to power up within 50 ms after it has been enabled, the corresponding UV flag is set and the interrupt pin is pulled low. However, the device will remain in ACTIVE mode in this case.

8.3.4 Active Discharge

TPS65185x provides low-impedance discharge paths for the display power rails (VEE, VNEG, VPOS, VDDH, and VCOM) which are enabled whenever the corresponding rail is disabled. The discharge paths are connected to the rails on the PCB which allows adding external resistors to customize the discharge time. However, external resistors are not required.

TOP: Power-up sequence is defined by assigning strobes to individual rails. STROBE1 is the first strobe to occur after ACTIVE bit is set and STROBE4 is the last event in the sequence. Strobes are assigned to rails in UPSEQ0 register and delays between STROBES are defined in UPSEQ1 register.

BOTTOM: Power-down sequence is independent of power-up sequence. Strobes and delay times for power down sequence are set in DWNSEQ0 and DWNSEQ1 register.

Figure 20. Power-Up and Power-Down Sequence

Product Folder Links: TPS65185

+ 45 hidden pages

Texas Instruments TPS65185, TPS651851 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

1 Features

2 Applications

3 Description

Table of Contents

4 Revision History

5 Description (continued)

6 Pin Configuration and Functions

7 Specifications

7.1 Absolute Maximum Ratings

7.2 ESD Ratings

7.3 Recommended Operating Conditions

7.4 Thermal Information

7.5 Electrical Characteristics

7.6 Timing Requirements: Data Transmission

7.7 Typical Characteristics

8 Detailed Description

8.1 Overview

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Wake-Up and Power-Up Sequencing

8.3.2 Dependencies Between Rails

8.3.3 Soft Start

8.3.4 Active Discharge