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TPS62233EVM-574
User Manual
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Texas Instruments LP38798EVM, AN-1662 LMV551, SN65LVCP114, TPS2378, TPS62233EVM-574 User Manual

User's Guide
SNOA914–March 2013
LP38798EVM User's Guide
The LP38798EVM evaluation board is designed to demonstrate the capabilities of the LP38798SD-ADJ high performance LDO voltage regulator. It is intended to provide a flexible circuit configurations and access to points of interest. The circuit schematic is shown in Figure 1.
Contents
1 Introduction .................................................................................................................. 2
3 Evaluation Board Start-Up ................................................................................................. 2
5 Schematic for LP38798EVAL ............................................................................................. 5
List of Figures
1 LP38798EVM Schematic .................................................................................................. 3
2 LP38798SD-ADJ (12-lead WSON) Connection Diagram.............................................................. 3
4 Copper Layer 1 (Top Layer) as Viewed from Top ..................................................................... 4
5 Copper Layer 2 (Mid-Layer 1) as Viewed from Top.................................................................... 4
6 Copper Layer 3 (Mid-Layer 2) as Viewed from Top.................................................................... 5
List of Tables
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SNOA914–March 2013 LP38798EVM User's Guide
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1
Introduction

1 Introduction

The LP38798EVM evaluation board is designed to demonstrate the capabilities of the LP38798-ADJ high performance LDO voltage regulator. It is intended to provide for flexible circuit configurations and access to points of interest. The circuit schematic is shown in Figure 1.

2 Operating Range

• Minimum Operating Input Voltage: 5.50V
• Maximum Operating Input Voltage: 20.0V
• Output Voltage : 5.00V
• Maximum Operating Output Current: 800mA
• Ambient Temperature Operating Range 0°C to 50°C
• Board Size 1.00 inches x 1.33 inches While the values listed for the Operating Range are all accurate, some combinations of ambient
temperature (TA), device dissipation (PD), and the maximum junction temperature (TJ) of 125°C may limit the useable range. See the device datasheet for a full discussion of thermal considerations.
Typical evaluation board performance and characteristics curves are shown in the LP38798-ADJ datasheet (Literature Number SNOSCT6). The PCB layout is shown in Figure 3 through Figure 7. Test points are provided on the evaluation board for signal monitoring and optional Enable control.

3 Evaluation Board Start-Up

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Before applying power to the LP38798EVM board, all external connections should be verified. The external power supply must be turned off before being connected, Confirm proper polarity to the 'VIN' and 'GND' terminals before turning the external power supply on. An appropriate load should be connected between the 'VOUT' and 'GND' terminals. Under basic evaluation conditions all of the test points can be left open. The evaluation board will be in the normal operating mode when input power is applied.
Use of the ENABLE function is optional. Pulling the ENABLE pin low, either by connecting to voltage lower than the typical OFF threshold of 1.00V, or by connecting directly to ground, will disable the output. Do not connect the ENABLE pin to any voltage above the EN

4 Setting the Output Voltage

The LP38798EVM board is assembled with R1= 47.5 kΩ and R2= 15.0 kΩ, to set the output voltage to
5.00V. Resistors R1 and R2 may be replaced, as needed, to achieve the desired output voltage as long as the
value for R2 is no less than 12.9 kΩ The following formula is used to determine the typical output voltage:
V
= ( ( VFBx ( 1 + (R1 / R2 ) ) ) + VOS) (1)
OUT
Alternately, the following formula can be used to determine the appropriate R1 value for a given R2 value with a V
The following table suggests some ±1% tolerance values for R1, keeping R2 held at the installed value of
15.0 kΩ , for a range of output voltages using the typical VFBvalue of 1.200V. This is not a definitive list, as other combinations R1 and R2 exist that will provide similar, possibly better, performance.
≥ 1.20V:
OUT
R1 = ( ( ( V
/ VFB) - 1) x R2 ) (2)
OUT
voltage of 5.0V (typical).
(CLAMP)
Target V
2
LP38798EVM User's Guide SNOA914–March 2013
OUT
1.50V 3.74 kΩ 15.0 kΩ 1.499V
1.80V 7.50 kΩ 15.0 kΩ 1.800V
1.90V 8.66 kΩ 15.0 kΩ 1.893V
2.00V 10.0 kΩ 15.0 kΩ 2.000V
2.50V 16.2 kΩ 15.0 kΩ 2.496V
R1 R2 Typical V
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OUT
IN
EN
CP
GND (CP)
OUT
SET FB GND
OUT OUT (FB)
IN
IN (CP)
Exposed Pad on
Bottom
(DAP)
1 2 3 4 5 6 7
8
9
10
11
12
OUT(FB)
2
3
4
5
6
7
8
1
SET
FB
GND(CP)
CP
EN
IN(CP)
V
IN
V
OUT
GNDGND
R1
R2
LP38798SD-ADJ
GND
IN
IN
OUT
OUT
9
10
11
12
V
EN
DAP
+
+
C2
C1
C3
C4
C5
TP1 TP2
TP3
TP4
TP5
J1
J5
J2
J3 J4
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Setting the Output Voltage
Target V
OUT
R1 R2 Typical V
3.00V 22.6 kΩ 15.0 kΩ 3.008V
3.30V 26.1 kΩ 15.0 kΩ 3.288V
4.70V 44.2 kΩ 15.0 kΩ 4.736V
5.00V 47.5 kΩ 15.0 kΩ 5.000V
Figure 1. LP38798EVM Schematic
OUT
Figure 2. LP38798SD-ADJ (12-lead WSON) Connection Diagram
SNOA914–March 2013 LP38798EVM User's Guide
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Figure 3. Top Layer as Viewed from Top
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3
GND 3
GND 4
Setting the Output Voltage
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Figure 4. Copper Layer 1 (Top Layer) as Viewed from Top
Figure 5. Copper Layer 2 (Mid-Layer 1) as Viewed from Top
4
LP38798EVM User's Guide SNOA914–March 2013
Copyright © 2013, Texas Instruments Incorporated
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