•High-Efficiency Synchronous Step-Down
Converter With up to 95% Efficiency
•12-µA Quiescent Current (Typ)for systems powered from a 1-cell or 2-cell Li-Ion
•2.7-V to 10-V Operating Input Voltage Range
•Adjustable Output Voltage Range From 0.7 V
to 6 V
•Fixed Output Voltage Options Available in
1.5 V, 1.8 V, and 3.3 V
•Synchronizable to External Clock Signal up to
1.2 MHz
•High Efficiency Over a Wide Load Current
Range in Power-Save Mode
•100% Maximum Duty Cycle for Lowest
Dropout
•Low Noise Operation in Forced Fixed
Frequency PWM Operation Mode
•Internal Softstart
•Overtemperature and Overcurrent Protected
•Available in 10-Pin Microsmall Outline
Package MSOP
The TPS6205x devices are a family of high-efficiency
synchronous step-down dc/dc converters ideally suited
battery or from a 3-cell to 5-cell NiCd, NiMH, or alkaline
battery.
The TPS62050 is a synchronous PWM converter with
integrated N-channel and P-channel power MOSFET
switches. Synchronous rectification increases efficiency and reduces external component count. To
achieve highest efficiency over a wide load current
range,theconverterentersapower-saving
pulse-frequency modulation (PFM) mode at light load
currents. Operating frequency is typically 850 kHz,
allowing the use of small inductor and capacitor values.
The device can be synchronized to an external clock
signal in the range of 600 kHz to 1.2 MHz. For low noise
operation, the converter can be programmed into
forced-fixed frequency in PWM mode. In shutdown
mode, the current consumption is reduced to less than
2 µA. The TPS6205x is available in the 10-pin (DGS)
micro-small outline package (MSOP) and operates
over an free air temperature range of -40°C to 85°C.
APPLICATIONS
•Cellular Phones
•Organizers, PDAs, and Handheld PCs
•Low Power DSP Supply
•Digital Cameras and Hard Disks
MATHCAD is a trademark of Mathsoft Incorporated.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform tospecifications per the terms ofTexas Instruments
standard warranty. Production processing does not necessarily includetestingof allparameters.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can
range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to
damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION
PACKAGED DEVICES
PLASTIC MSOP
TPS62050DGSAdjustable 0.7 V to 6 VStandardBFM
TPS62051DGSAdjustable 0.7 V to 6 VEnhancedBGB
TPS62052DGS1.5 VStandardBGC
TPS62054DGS1.8 VStandardBGE
TPS62056DGS3.3 VStandardBGG
(1)
The DGS packages are available taped and reeled. Add an R suffix to the device type (i.e., TPS62050DGSR) to order quantities of
2500 devices per reel.
(1)
(DGS)
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
Supply voltage, V
Voltage at EN, SYNC-0.3 V to V
Voltage at LBI, FB, LBO, PG-0.3 V to 7 V
Voltage at SW-0.3 V to 11 V
Output current, I
Maximum junction temperature, T
Operating free-air temperature range, T
Storage temperature range, T
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds300°C
(1)
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2)
The voltage at the SW pin is sampled in PFM mode 15 µs after the PMOS has switched off. During this time the voltage at SW is
limited to 7 V maximum. Therefore, the output voltage of the converter is limited to 7 V maximum.
EN8IEnable. A logic high enables the converter, logic low forces the device into shutdown mode, reducing the supply
FB5IFeedback pin for the fixed output voltage option. For the adjustable version, an external resistive divider is
GND3IGround
LBO2OOpen drain low battery output. Logic low signal indicates a low battery voltage.
LBI6ILow battery input
PG4OPower good comparator output. This is an open-drain output. A pullup resistor should be connected between PG
PGND10IPower ground. Connect all power grounds to this pin.
SW9OConnect the inductor to this pin. This pin is the switch pin and connected to the drain of the internal power
SYNC7IInput for synchronization to the external clock signal. This input can be connected to an external clock or pulled to
VIN1ISupply voltage input
I/ODESCRIPTION
current to less than 2 µA.
connected to this pin. The internal voltage divider is disabled for the adjustable version.
and VOUT. The output goes active high when the output voltage is greater than 95% of the nominal value.
MOSFETS.
GND or VI. When an external clock signal is applied, the device synchronizes to this external clock and the device
operates in fixed PWM mode. When the pin is pulled to either GND or VI, the internal oscillator is used and the
logic level determines if the device operates in fixed PWM or PWM/PFM mode.SYNC = HIGH: Low-noise mode
enabled, fixed frequency PWM operation is forcedSYNC = LOW (GND): Power-save mode enabled, PFM/PWM
mode enabled.
5
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Undervoltage
Lockout
Bias Supply
_
+
+
–
REF
Current Limit Comparator
+
–
REF
I
(AVG)
Comparator
P-Channel
Power MOSFET
N-Channel
Power MOSFET
Driver
Shoot-Through
Logic
+
–
Load Comparator
Control
Logic
+
–
1.21 V
Soft Start
850 kHz
Oscillator
+
–
S
R
Comparator High
Comparator Low
Comparator High2
+
–
Compensation
R2
See Note
R1
V
REF
= 0.5 V
Comparator Low
Comparator Low2
Comparator High
Saw Tooth
Generator
V
I
V
(COMP)
Comparator
SW
PG
LBO
GNDPGNDLBIFB
V
I
EN
SKIP Comparator
Error Amp
SYNC
TPS62050, TPS62051
TPS62052, TPS62054, TPS62056
SLVS432D–SEPTEMBER 2002 – REVISED OCTOBER 2003
FUNCTIONAL BLOCK DIAGRAM
6
NOTE: For the adjustable versions (TPS62050, TPS62051), the internal feedback driver is disabled and the FB pin is
directly connected to the GM amplifier.
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PGND
FB
PG
VIN
8
LBO
GND
SYNC
EN
LBI
TPS62050
SW
1
6
7
3
2
9
5
4
10
L1 = 10 µH
VO = 5 V
R1 =
820 kΩ
C
(ff)
= 6.8 pF
R2 = 91 kΩ
Co = 22 µF
Ci = 10 µF
V
I
R5
130 kΩ
R6
100 kΩ
R3
1 MR41 M
TDK
C3216X5R1A106M
Taiyo Yuden
JMK316BJ226ML
WE PD 744 777 10
Quiescent Current Measurements and Efficiency Were Taken
With: R5 = Open, R4 = Open, LBI Connected to GND.
TPS62050, TPS62051
TPS62052, TPS62054, TPS62056
SLVS432D–SEPTEMBER 2002 – REVISED OCTOBER 2003
PARAMETER MEASUREMENT INFORMATION
All graphs were generated using the circuit as shown unless otherwise noted. For output voltages other than 5 V,
the fixed voltage versions are used. The resistors R1, R2, and the feedforward capacitor (Cff) are removed and
the feedback pin is directly connected to the output.
STANDARD CIRCUIT FOR ADJUSTABLE VERSION
7
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