Texas Instruments TPS61280D, TPS61281D, TPS61282D Datasheet

1.5µF X5R 6.3V (0402)

C (x2) 10µF X5R 6.3V (0603)

VBAT’

0.47 Hμ

TPS61280D

VIN

VSEL

BYP

SCL

SDA

PGND

VOUT

GPIO

AGND

Battery

2.5V .. 4.35V

Enable

1.8V

Interrupt

Forced Bypass / Auto

Voltage Select

I C Bus

Product Folder

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Technical Documents

Tools & Software

Support & Community

TPS61280D

SLVSEA0A –JANUARY 2018–REVISED AUGUST 2018

TPS6128xD Low-IQ, Wide-Voltage Battery Front-End DC/DC Converter for

Single-Cell Li-Ion, Ni-Rich, Si-Anode Applications

1 Features

• 95% Efficiency at 2.3 MHz Operation

• 3-µA Quiescent Current in Low IQPass-Through Mode

• Wide VINRange From 2.3 V To 4.8 V

• I

≥ 4A (Peak) at V

OUT

= 3.35 V, VIN≥ 2.65 V

OUT

• Integrated Pass-Through Mode (35 mΩ)

• Programmable Valley Inductor Current Limit and Output Voltage

• True Pass-Through Mode During Shutdown

• Best-in-Class Line and Load Transient

• Low-Ripple Light-Load PFM Mode

• In-Situ Customization with On-Chip E2PROM (Write Protection)

• Two Interface Options: – I2C Compatible I/F up to 3.4 Mbps

(TPS61280D)

– Simple I/O Logic Control Interface

• Thermal Shutdown and Overload Protection

• Total Solution Size < 20 mm2, Sub 1-mm Profile

2 Applications

• Single-Cell Ni-Rich, Si-Anode, Li-Ion, LiFePO4 Smart-Phones or Tablet PCs

• 2.5G, 3G, 4G Mini-Module Data Cards

• Current Limited Applications Featuring High Peak Power Loads

3 Description

The TPS6128xD device provides a power supply solution for products powered by either by a Li-Ion, Nickel-Rich, Silicon Anode, Li-Ion or LiFePO4 battery. The voltage range is optimized for single-cell portable applications like in smart-phones or tablet PCs.

Used as a high-power pre-regulator, the TPS6128xD extends the battery run-time and overcomes input current- and voltage limitations of the powered system.

While in shutdown, the TPS6128xD operates in a true pass-through mode with only 3-µA quiescent consumption for longest battery shelf life.

During operation, when the battery is at a good stateof-charge, a low-ohmic, high-efficient integrated passthrough path connects the battery to the powered system.

If the battery gets to a lower state of charge and its voltage becomes lower than the desired minimum system voltage, the device seamlessly transits into boost mode to uses the full battery capacity.

Device Information

PART NUMBER PACKAGE BODY SIZE (NOM)

TPS61280D

DSBGA (16) 1.66 mm x 1.66 mmTPS61281D

TPS61282D (1) For all available packages, see the orderable addendum at

the end of the datasheet.

(1)

Simplified Schematic

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

TPS61280D

SLVSEA0A –JANUARY 2018–REVISED AUGUST 2018

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1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description ............................................................. 1

4 Revision History..................................................... 2

5 Description (continued)......................................... 3

6 Device Comparison Table..................................... 3

7 Pin Configuration and Functions......................... 4

8 Specifications......................................................... 6

8.1 Absolute Maximum Ratings ..................................... 6

8.2 ESD Ratings.............................................................. 6

8.3 Recommended Operating Conditions....................... 6

8.4 Thermal Information.................................................. 7

8.5 Electrical Characteristics........................................... 7

8.6 I2C Interface Timing Characteristics ........................ 9

8.7 I2C Timing Diagrams............................................... 11

8.8 Typical Characteristics............................................ 12

9 Detailed Description ............................................ 14

9.1 Overview................................................................. 14

9.2 Functional Block Diagram....................................... 15

9.3 Feature Description................................................. 16

9.4 Device Functional Modes........................................ 17

9.5 Programming........................................................... 22

9.6 Register Maps......................................................... 25

10 Application and Implementation........................ 33

10.1 Application Information.......................................... 33

10.2 Typical Application ................................................ 34

11 Power Supply Recommendations..................... 46

12 Layout................................................................... 46

12.1 Layout Guidelines ................................................. 46

12.2 Layout Example .................................................... 46

12.3 Thermal Information.............................................. 47

13 Device and Documentation Support ................. 48

13.1 Device Support...................................................... 48

13.2 Receiving Notification of Documentation Updates 48

13.3 Community Resources.......................................... 48

13.4 Trademarks........................................................... 48

13.5 Electrostatic Discharge Caution............................ 48

13.6 Glossary................................................................ 48

14 Mechanical, Packaging, and Orderable

Information........................................................... 49

14.1 Package Summary................................................ 49

4 Revision History

Changes from Original (January 2018) to Revision A Page

• Changed devices TPS61281D and TPS61282D From: Product Preview To: Production data............................................. 1

• Changed the TPS61280D pin configuration........................................................................................................................... 4

• Changed the TPS6128xD pin configuration ........................................................................................................................... 5

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5 Description (continued)

TPS6128xD device supports more than 4 A pulsed load current even from a deeply discharged battery. In this mode of operation, the TPS6128xD enables the use of the full battery capacity: A high battery-cut-off voltage originated by powered components with a high minimum input voltage is overcome; new battery chemistries can be fully discharged; high current pulses forcing the system into shutdown are buffered by the device seamlessly transitioning between boost and by-pass mode back and forth.

This has significant impact on the battery on-time and translates into either a longer use-time and better userexperience at an equal battery capacity or into reduced battery costs at similar use-times.

The TPS6128xD offers a small solution size (< 20 mm2) due to minimum amount of external components, enabling the use of small inductors and input capacitors, available as a 16-pin chip-scale package (CSP).

The TPS6128xD operates in synchronous, 2.3 MHz boost mode and enters power-save mode operation (PFM) at light load currents to maintain high efficiency over the entire load current range.

6 Device Comparison Table

PART NUMBER

TPS61280D

TPS61281D Simple Logic Control Interface

TPS61282D Simple Logic Control Interface

I2C Control Interface User Prog. E2PROM Settings

DEVICE

SPECIFIC FEATURES

DC/DC boost / bypass threshold = 3.15 V (VSEL = L) DC/DC boost / bypass threshold = 3.35 V (VSEL = H) Valley inductor current limit = 3 A DC/DC boost / bypass threshold = 3.15 V (VSEL = L) DC/DC boost / bypass threshold = 3.35 V (VSEL = H) Valley inductor current limit = 3 A DC/DC boost / bypass threshold = 3.3 V (VSEL = L) DC/DC boost / bypass threshold = 3.5 V (VSEL = H) Valley inductor current limit = 4 A

Product Folder Links: TPS61280D

1 2 3 4

Not to scale

AGND PGND PGND PGND

nBYP SDA SW SW

VSEL SCL VOUT VOUT

EN GPIO VIN VIN

1 2 3 4

Not to scale

EN GPIO VIN VIN

VSEL SCL VOUT VOUT

nBYP SDA SW SW

AGND PGND PGND PGND

TPS61280D

SLVSEA0A –JANUARY 2018–REVISED AUGUST 2018

7 Pin Configuration and Functions

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TPS61280D YFF Package

16-Bump DSBGA

Top View

TPS61280D YFF Package

16-Bump DSBGA

Bottom View

Pin Functions, TPS61280D

NAME NO.

VIN A3, A4 I Power supply input. VOUT B3, B4 O Boost converter output.

EN A1 I

GPIO A2 I/O

VSEL B1 I

nBYP C1 I SCL B2 I Serial interface clock line. This pin must not be left floating and must be terminated.

SDA C2 I/O Serial interface address/data line. This pin must not be left floating and must be terminated. SW C3, C4 I/O Inductor connection. Drain of the internal power MOSFET. Connect to the switched side of the inductor. PGND D2, D3, D4 Power ground pin. AGND D1 Analog ground pin. This is the signal ground reference for the IC.

I/O DESCRIPTION

This is the enable pin of the device. On the rising edge of the enable pin, all the registers are reset with their default values. This input must not be left floating and must be terminated.

EN = Low: The device is forced into shutdown mode and the I2C control interface is disabled. Depending on the logic level applied to the nBYP input, the converter can either be forced in pass-through mode or it's output can be regulated to a minimum level so as to limit the input-to-output voltage difference to less than 3.6V (typ). The current consumption is reduced to a few µA. For more details, refer to Table 2.

EN = High: The device is operating normally featuring automatic dc/dc boost, pass-through mode transition. For more details, refer to Table 2.

This pin can either be configured as a input (mode selection) or as dual role input/open-drain output RST/FAULT ) pin. Per default, the pin is configured as RST/FAULT input/output. The input must not be left floating and must be terminated.

Manual Reset Input: Drive RST/FAULT low to initiate a reset of the converter's output. nRST/nFAULT controls a falling edge-triggered sequence consisting of a discharge phase of the capacitance located at the converter's output followed by a start-up phase.

Fault Output (open-drain interrupt signal to host): Indicates that a fault has occurred (e.g. thermal shutdown, output voltage out of limits, current limit triggered, and so on). To signal such an event, the device generates a falling edgetriggered interrupt by driving a negative pulse onto the GPIO line and then releases the line to its inactive state.

Mode selection input = Low: The device is operating in regulated frequency pulse width modulation mode (PWM) at high-load currents and in pulse frequency modulation mode (PFM) at light load currents.

Mode selection input = High: Low-noise mode enabled, regulated frequency PWM operation forced. VSEL signal is primarily used to set the output voltage dc/dc boost, pass-through threshold. This pin must not be left

floating and must be terminated. A logic low level on the BYP input forces the device in pass-through mode. This pin must not be left floating and

must be terminated.

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1 2 3 4

Not to scale

AGND PGND PGND PGND

nBYP AGND SW SW

VSEL MODE VOUT VOUT

EN PG VIN VIN

1 2 3 4

Not to scale

EN PG VIN VIN

VSEL MODE VOUT VOUT

nBYP AGND SW SW

AGND PGND PGND PGND

TPS61280D

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TPS6128xD YFF Package

16-Bump DSBGA

Top View

SLVSEA0A –JANUARY 2018–REVISED AUGUST 2018

TPS6128xD YFF Package

16-Bump DSBGA

Bottom View

Pin Functions, TPS6128xD

NAME NO.

VIN A3, A4 I Power supply input. VOUT B3, B4 O Boost converter output.

EN A1 I

PG A2 O

VSEL B1 I

nBYP C1 I

MODE B2 I

SW C3, C4 I/O Inductor connection. Drain of the internal power MOSFET. Connect to the switched side of the inductor. PGND D2, D3, D4 Power ground pin. AGND C2, D1 Analog ground pin. This is the signal ground reference for the IC.

I/O DESCRIPTION

This is the enable pin of the device. On the rising edge of the enable pin, all the registers are reset with their default values. This input must not be left floating and must be terminated.

EN = Low: The device is forced into shutdown mode. Depending on the logic level applied to the nBYP input, the converter can either be forced in pass-through mode or it's output can be regulated to a minimum level so as to limit the input-to-output voltage difference to less than 3.6V (typ). The current consumption is reduced to a few µA. For more details, refer to Table 2.

EN = High: The device is operating normally featuring automatic dc/dc boost, pass-through mode transition. For more details, refer to Table 2.

Power-Good Output (open-drain output to host): A logic high on the PG output indicates that the converter's output voltage is within its regulation limits. A logic low indicates a fault has occurred (e.g. thermal shutdown, output voltage out of limits, current limit triggered, and so on). The PG signal is de-asserted automatically once the IC resumes proper operation.

VSEL signal is primarily used to set the output voltage dc/dc boost, pass-through threshold. This pin must not be left floating and must be terminated.

A logic low level on the BYP input forces the device in pass-through mode. For more details, refer to Table 2. This pin must not be left floating and must be terminated.

This is the mode selection pin of the device. This pin must not be left floating, must be terminated and can be connected to AGND. During start-up this pin must be held low. Once the output voltage settled and PG pin indicates that the converter's output voltage is within its regulation limits the device can be forced in PWM mode operation by applying a high level on this pin.

MODE = Low: The device is operating in regulated frequency pulse width modulation mode (PWM) at high-load currents and in pulse frequency modulation mode (PFM) at light load currents. This pin must be held low during device start-up.

MODE = High: Low-noise mode enabled, regulated frequency PWM operation forced.

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8 Specifications

8.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(2)

, EN

, SDA

(2)

, VSEL

(2)

(4)

MODE

(2)

, BYP

(2)

(5)

A(max)

(2)

, PG

(3)

) is dependent on the maximum operating junction temperature (T

A(max)

Voltage at VOUT Voltage at VIN

(2)

GPIO

Input voltage

Voltage at SCL

Voltage at SW

Differential voltage between VIN and VOUT DC –0.3 4 V

Input current

Continuous average current into SW Peak current into SW

Power dissipation Internally limited

Temperature range

stg

Operating temperature range, T Operating virtual junction, T Storage temperature range –65 150 °C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability. (2) All voltages are with respect to network ground terminal. (3) Limit the junction temperature to 105°C for continuous operation at maximum output power. (4) Limit the junction temperature to 105°C for 15% duty cycle operation. (5) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may

have to be derated. Maximum ambient temperature (T

maximum power dissipation of the device in the application (P

in the application (θJA), as given by the following equation: T

recommended to operate the device with a maximum junction temperature of 105°C.

(1)

MIN MAX UNIT

DC –0.3 4.7 V

(2)

DC –0.3 5.2 V DC –0.3 3.6 V

DC –0.3 4.7 V Transient: 2 ns, 2.3

MHz

–0.3 5.5 V

1.8 A

5.5 A

–40 85 °C –40 150 °C

), and the junction-to-ambient thermal resistance of the part/package

D(max)

= T

J(max)

– (θJAX P

). To achieve optimum performance, it is

D(max)

J(max)

), the

8.2 ESD Ratings

VALUE UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins

ESD

Electrostatic discharge

Charged device model (CDM), per JEDEC specification JESD22-C101, all pins

(1)

(2)

±2000 V

±1000 V

Machine Model - (MM) ±200 V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.3 Recommended Operating Conditions

MIN NOM MAX UNIT

L Inductance 200 470 800 nH C

Input voltage range 2.30 4.85 V Input voltage range for in-situ customization by E2PROM write operation 3.4 3.5 3.6 V

Output capacitance 9 13 100 µF Maximum load current during start-up 250 mA Ambient temperature –40 85 °C Operating junction temperature –40 125 °C

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8.4 Thermal Information

TPS6128xD

THERMAL METRIC

(1)

UNITYFF (DSBGA)

16 PINS

R R R

θJA θJCtop θJB

JT JB

θJCbot

Junction-to-ambient thermal resistance 78 °C/W Junction-to-case (top) thermal resistance 0.6 °C/W Junction-to-board thermal resistance 13 °C/W Junction-to-top characterization parameter 2.4 °C/W Junction-to-board characterization parameter 13 °C/W Junction-to-case (bottom) thermal resistance n/a °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

8.5 Electrical Characteristics

Minimum and maximum values are at VIN= 2.3 V to 4.85 V, V

1.8 V, nBYP = 1.8 V, –40°C ≤ TJ≤ 125°C; Circuit of Parameter Measurement Information section (unless otherwise noted). Typical values are at VIN= 3.2 V, V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SUPPLY CURRENT

Operating quiescent current into V

UVLO

EN, VSEL, nBYP, MODE, SDA, SCL, GPIO, PG

THPG

lkg

OUTPUT

OUT(TH)

OUT

Operating quiescent current into V

OUT

Shutdown current TPS6128xD

Under-voltage lockout threshold TPS6128xD

Low-level input voltage High-level input voltage 1.2 V Low-level output voltage (SDA) Low-level output voltage (GPIO) IOL= 8 mA, GPIOCFG = 0 0.3 V Low-level output voltage (PG) TPS6128xD IOL= 8 mA 0.3 V EN, VSEL, BYP,

pull-down resistance EN, VSEL, BYP, MODE, PG

input capacitance SDA, SCL, GPIO input

capacitance

Power good threshold TPS6128xD

Input leakage current TPS6128xD

Threshold DC voltage accuracy TPS6128xD No load. Open loop -1.5% 1.5%

Regulated DC voltage accuracy TPS6128xD

= 3.4 V, EN = 1.8 V, TJ= 25°C (unless otherwise noted).

OUT

DC/DC boost mode. Device not switching I

= 0 mA, VIN= 3.2 V, V

OUT

Pass-through mode (auto)

TPS6128xD

EN = 1.8 V, BYP = 1.8 V, VIN= 3.6 V Pass-through mode (forced)

EN = 1.8 V, BYP = AGND, V DC/DC boost mode. Device not

switching I

= 0 mA, VIN= 3.2 V, V

OUT

EN = 0 V, BYP = 0 V, VIN= 3.6 V 3 6.6 μA EN = 0 V, BYP = 1.8 V, VIN= 3.6 V 8.9 20.6 μA Falling 2 2.1 V Hysteresis 0.1 V

TPS6128xD

TPS61280D

IOL= 8 mA 0.3 V

TPS6128xD Input ≤ 0.4 V 300 kΩ

TPS6128xD

Input connected to AGND or V

TPS61280D 9 pF

Rising V

OUT

Falling V

OUT

Input connected to AGND Input connected V

2.65 V ≤ VIN≤ V I

= 0mA

OUT

PWM operation.

2.65 V ≤ VIN≤ V I

= 0 mA

OUT

PFM/PWM operation

= 3.4 V (or VIN, whichever is higher), EN = 1.8 V, VSEL =

OUT

47.4 65.6 µA

= 3.4 V

OUT

27.4 42.6 µA

OUT

= 3.6 V

–40°C ≤ T 85°C

≤

15.4 25.6 µA

8.9 19.6 µA

= 3.4 V

OUT

9 pF

0.95 x V

OUT

0.9 x V

OUT

0 µA

OUT_TH

- 150 mV

–40°C ≤ T 85°C

≤

-2% 2%

-2% 4%

0.4 V

0.5 µA

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Electrical Characteristics (continued)

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Minimum and maximum values are at VIN= 2.3 V to 4.85 V, V

= 3.4 V (or VIN, whichever is higher), EN = 1.8 V, VSEL =

OUT

1.8 V, nBYP = 1.8 V, –40°C ≤ TJ≤ 125°C; Circuit of Parameter Measurement Information section (unless otherwise noted). Typical values are at VIN= 3.2 V, V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Power-save mode

ΔV

POWER SWITCH

DS(on)

lkg

SINK

OSCILLATOR

OSC

THERMAL SHUTDOWN, HOT DIE DETECTOR

TIMING

(1) Specified by characterization. Not tested in production.

output ripple voltage

OUT

PWM mode output ripple voltage PWM operation, I

Low-side switch MOSFET on resistance

High-side rectifier MOSFET on resistance

High-side pass-through MOSFET on resistance

Reverse leakage current into SW

Reverse leakage current into VOUT

VOUT sink capability TPS6128xD EN = AGND, V Valley inductor current limit

Valley inductor current limit TPS61282D

Pass through mode current limit TPS6128xD

Pre-charge mode current limit (linear mode, phase 1)

Pre-charge mode current limit (linear mode, phase 2)

Oscillator frequency TPS6128xD VIN= 2.7 V, V

Thermal shutdown Hot die detector accuracy

(1)

Start-up time TPS6128xD GPIO rise time

(1)

= 3.4 V, EN = 1.8 V, TJ= 25°C (unless otherwise noted).

OUT

TPS6128xD

PFM operation, I

VIN= 3.2 V, V

= 1 mA 30 mVpk

OUT

= 500 mA 15 mVpk

OUT

= 3.5 V 45 80 mΩ

OUT

= 3.5 V 40 70 mΩ

OUT

VIN= 3.2 V 35 60 mΩ

TPS6128xD

EN = AGND, VIN= V –40°C ≤ TJ≤ 85°C

EN = BYP = VIN, VIN= 2.9 V, V device not switching

= SW = 3.5 V

OUT

= 4.4 V, VSW= 0 V

OUT

0.1 2 µA

0.11 2 µA

–40°C ≤ TJ≤ 85°C

TPS61280D TPS61281D

VIN= 2.9 V, V PFM/PWM

≤ 3.6 V,I

OUT

= 3.5 V, –40°C ≤ TJ≤ 125°C, auto

OUT

= 3.5 V, –40°C ≤ TJ≤ 125°C, auto

OUT

= -10 mA 0.3 V

OUT

2475 3000 3525 mA

3300 4000 4700 mA

EN = BYP = GND, VIN= 3.2 V 5000 mA EN = VIN, BYP = don't care , VIN= 3.2 V 5600 7400 9100 mA

500 650 mA

TPS6128xD VIN- V

>= 300 mV

OUT

2000 mA

= 3.5 V 2.3 MHz

OUT

TPS6128xD 140 160 °C TPS61280D -10 105 10 °C

VIN= 3.2 V, VOUT_TH = 01011 (3.4 V), R Time from active VINto V

OUT

settled

LOAD

= 50 Ω

500 µs

TPS61280D 200 ns

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8.6 I2C Interface Timing Characteristics

PARAMETER TEST CONDITIONS MIN MAX UNIT

(SCL)

BUF

tHD, t

LOW

HIGH

tSU, t

tHD, t

RCL

RCL1

SCL Clock Frequency

Bus Free Time Between a STOP and START Condition

Hold Time (Repeated) START

STA

Condition

LOW Period of the SCL Clock

HIGH Period of the SCL Clock

Setup Time for a Repeated START

STA

Condition

Data Setup Time

DAT

Data Hold Time

DAT

Rise Time of SCL Signal

Rise Time of SCL Signal After a Repeated START Condition and After an Acknowledge BIT

High-speed mode (write operation), CB– 100 pF max 3.4 MHz High-speed mode (read operation), CB– 100 pF max 3.4 MHz High-speed mode (write operation), CB– 400 pF max 1.7 MHz High-speed mode (read operation), CB– 400 pF max 1.7 MHz

(1)

Standard mode 100 kHz

Fast mode 400 kHz

Fast mode plus 1 MHz

Standard mode 4.7 μs

Fast mode 1.3 μs Fast mode plus 0.5 μs Standard mode 4 μs

Fast mode 600 ns Fast mode plus 260 ns

High-speed mode 160 ns

Standard mode 4.7 μs

Fast mode 1.3 μs Fast mode plus 0.5 μs

High-speed mode, CB– 100 pF max 160 ns High-speed mode, CB– 400 pF max 320 ns

Standard mode 4 μs

Fast mode 600 ns Fast mode plus 260 ns

High-speed mode, CB– 100 pF max 60 ns High-speed mode, CB– 400 pF max 120 ns

Standard mode 4.7 μs

Fast mode 600 ns Fast mode plus 260 ns

High-speed mode 160 ns

Standard mode 250 ns

Fast mode 100 ns Fast mode plus 50 ns

High-speed mode 10 ns

Standard mode 0 3.45 μs

Fast mode 0 0.9 μs Fast mode plus 0 μs

High-speed mode, CB– 100 pF max 0 70 ns High-speed mode, CB– 400 pF max 0 150 ns

Standard mode 1000 ns

Fast mode 20 + 0.1 C

300 ns

Fast mode plus 120 ns

High-speed mode, CB– 100 pF max 10 40 ns High-speed mode, CB– 400 pF max 20 80 ns

Standard mode 20 + 0.1 CB1000 ns

Fast mode 20 + 0.1 C

300 ns

Fast mode plus 120 ns

High-speed mode, CB– 100 pF max 10 80 ns High-speed mode, CB– 400 pF max 20 160 ns

(1) Specified by design. Not tested in production.

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I2C Interface Timing Characteristics

PARAMETER TEST CONDITIONS MIN MAX UNIT

FCL

RDA

FDA

SU,tSTO

Fall Time of SCL Signal

Rise Time of SDA Signal

Fall Time of SDA Signal

Setup Time of STOP Condition

Capacitive Load for SDA and SCL

(1)

(continued)

High-speed mode, CB– 100 pF max 10 40 ns High-speed mode, CB– 400 pF max 20 80 ns

High-speed mode, CB– 100 pF max 10 80 ns High-speed mode, CB– 400 pF max 20 160 ns

Standard mode 20 + 0.1 C

300 ns

Fast mode 300 ns Fast mode plus 120 ns

Standard mode 1000 ns

Fast mode 20 + 0.1 C

300 ns

Fast mode plus 120 ns

Standard mode 300 ns

Fast mode 20 + 0.1 C

300 ns

Fast mode plus 120 ns

Standard mode 4 μs

Fast mode 600 ns Fast mode plus 260 ns

High-Speed mode 160 ns

Standard mode 400 pF

Fast mode 400 pF Fast mode plus 550 pF

High-Speed mode 400 pF

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Sr PSr

fDA

rDA

hd;DAT

su;STA

hd;STA

su;DAT

su;STO

rCL1

fCL

HIGHtLOW

LOWtHIGH

rCL

rCL1

= MCS Current Source Pull-Up = R

(P)

Resistor Pull-Up

SDAH

SCLH

Note A: First rising edge of the SCLH signal after Sr and after each acknowledge bit.

See Note ASee Note A

LOW

hd;STA

hd;DAT

su;DAT

HIGH

su;STA

S Sr P S

hd;STA

BUF

su;STO

SDA

SCL

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8.7 I2C Timing Diagrams

Figure 1. Serial Interface Timing Diagram for Standard-, Fast-, Fast-Mode Plus

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Figure 2. Serial Interface Timing Diagram for H/S-Mode

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3.5 4.5

Quiescent Current_Force Bypass (µA)

Input Voltage (V)

Tj=25C Tj=-40 Tj = 85 C

C005

TJ = 30°C TJ = -40°C TJ = 85°C

3.5 4.5

Quiescent Current_Auto Bypass (µA)

Input Voltage (V)

Tj=25C Tj=-40 Tj = 85 C

C006

TJ = 30°C TJ = -40°C TJ = 85°C

-40 -20 0 20 40 60 80 100 120

LS FET On Resistance (m

Junction Temperature (ƒC)

C003

2.3 2.5 2.7 2.9 3.1

Quiescent Current_Boost (µA)

Input Voltage (V)

Tj=25C Tj=-40 Tj = 85 C

C004

TJ = 30°C TJ = -40°C TJ = 85°C

-40 -20 0 20 40 60 80 100 120

HS FET On Resistance (m

Junction Temperature (ƒC)

C001

-40 -20 0 20 40 60 80 100 120

LS FET On Resistance (m

Junction Temperature (ƒC)

C002

TPS61280D

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8.8 Typical Characteristics

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VIN= 3.2 V V

Figure 3. High side R

= 3.5 V TJ= –40 to 125°C

OUT

vs Junction Temperature

ds(on)

VIN= 3.2 V Bypass TJ= –40 to 125°C

Figure 5. Bypass FET R

vs Junction Temperature

ds(on)

VIN= 3.2 V V

Figure 4. Low side R

VIN= 2.3 - 3.4 V V

= 3.5 V TJ= –40 to 125°C

OUT

vs Junction Temperature

ds(on)

= 3.4 V I

OUT

= 0 mA

EN = High Bypass = High

Figure 6. Quiescent Current at Boost Mode vs Input Voltage

VIN= 3.5 - 4.4 V V

EN = High Bypass = Low

Figure 7. Quiescent Current at Forced Bypass Mode vs

= 3.4 V I

OUT

Input Voltage

OUT

= 0 mA

VIN= 3.6 - 4.4 V V

EN = High Bypass = High

Figure 8. Quiescent Current at Auto Bypass Mode vs Input

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= 3.4 V I

OUT

Voltage

OUT

= 0 mA

0.50

0.60

0.70

0.80

0.90

1.00

1.10

-40 -20 0 20 40 60 80 100 120

EN Logic Threshold (V)

Junction Temperature (ƒC)

EN Rising EN Falling

C011

0.50

0.60

0.70

0.80

0.90

1.00

1.10

-40 -20 0 20 40 60 80 100 120

EN Logic Threshold (V)

Junction Temperature (ƒC)

nBYP Rising nBYP Falling

C012

1.80

2.00

2.20

-40 -20 0 20 40 60 80 100 120

Vin UVLO Threshold (V)

Junction Temperature (ƒC)

Vin Rising Vin Falling

C010

VIN Rising VIN Falling

2.0

2.5

3.0

3.5

4.0

4.5

-40 10 60 110

Switch Valley Current Limit (A)

Temperature ( C)

TPS61281D

TPS61282D

C009

2.3 3.3 4.3

Leakage Current_Low Iq (µA)

Input Voltage (V)

Tj=25C Tj=-40 Tj = 85 C

C007

TJ = 30°C TJ = -40°C TJ = 85°C

2.3 3.3 4.3

Leakage Current_Low Iq (µA)

Input Voltage (V)

Tj = 25C Tj = -40 Tj = 85 C

C008

TJ = 30°C TJ = -40°C TJ = 85°C

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Typical Characteristics (continued)

TPS61280D

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VIN= 2.3 - 4.4 V V

= 4.4 V VSW= 0 V

OUT

EN = Low Bypass = Low

Figure 9. Shutdown Current at Low IQmode vs Input

Voltage

VIN= 3.2 V V

= 3.5 V TJ= –40 to 125°C

OUT

EN = High Bypass = High

Figure 11. Switch Valley Current Limit: TPS61281D,

TPS61282D vs Input Voltage

VIN= 2.3 - 4.4 V V

= 4.4 V VSW= 0 V

OUT

EN = Low Bypass = High

Figure 10. Shutdown Current vs Input Voltage

VIN= 3.2 V V

= 3.5 V TJ= –40 to 125°C

OUT

Figure 12. VINUVLO Threshold Rising/Falling vs Junction

Temperature

VIN= 3.2 V V

OUT

Figure 13. EN Logic High Threshold Rising/Falling vs

Junction Temperature

= 3.5 V TJ= –40 to 125°C

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VIN= 3.2 V TJ= –40 to 125°C

Figure 14. BYP Logic High Threshold Rising/Falling vs

Junction Temperature

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9 Detailed Description

9.1 Overview

The TPS6128xD is a high-efficiency step-up converter featuring pass-through mode optimized to provide lownoise voltage supply for 2G RF power amplifiers (PAs) in mobile phones and/or to pre-regulate voltage for supplying subsystem like eMMC memory, audio codec, LCD bias, antenna switches, RF engine PMIC and so on. It is designed to allow the system to operate at maximum efficiency for a wide range of power consumption levels from a low-, wide- voltage battery cell.

The capability of the TPS6128xD to step-up the voltage as well as to pass-through the input battery voltage when its level is high enough allow systems to operate at maximum performance over a wide range of battery voltages, thereby extending the battery life between charging. The device also addresses brownouts caused by the peak currents drawn by the APU and GPU which can cause the battery rail to droop momentarily. Using the TPS6128xD device as a pre-regulator eliminates system brownout condition while maintaining a stable supply rail for critical sub-system to function properly.

The TPS6128xD synchronous step-up converter typically operates at a quasi-constant 2.3-MHz frequency pulse width modulation (PWM) at moderate to heavy load currents. At light load currents, the TPS6128xD converter operates in power-save mode with pulse frequency modulation (PFM).

In general, a dc/dc step-up converter can only operate in "true" boost mode, that is the output “boosted” by a certain amount above the input voltage. The TPS6128xD device operates differently as it can smoothly transition in and out of zero duty cycle operation. Depending upon the input voltage, output voltage threshold and load current, the integrated bypass switch automatically transitions the converter into pass-through mode to maintain low-dropout and high-efficiency. The device exits pass-through mode (0% duty cycle operation) if the total dropout resistance in bypass mode is insufficient to maintain the output voltage at it's nominal level. Refer to the typical characteristics section (DC Output Voltage vs. Input Voltage) for further details.

During PWM operation, the converter uses a novel quasi-constant on-time valley current mode control scheme to achieve excellent line/load regulation and allows the use of a small ceramic inductor and capacitors. Based on the VIN/V side N-MOS switch is turned-on and the inductor current ramps up to a peak current that is defined by the ontime and the inductance. In the second phase, once the on-timer has expired, the rectifier is turned-on and the inductor current decays to a preset valley current threshold. Finally, the switching cycle repeats by setting the on timer again and activating the low-side N-MOS switch.

The current mode architecture provides excellent transient load response, requiring minimal output filtering. Internal soft-start and loop compensation simplifies the design process while minimizing the number of external components.

The TPS6128xD directly and accurately controls the average input current through intelligent adjustment of the valley current limit, allowing an accuracy of ±17.5%. Together with an external bulk capacitor, the TPS6128xD allows an application to be interfaced directly to its load, without overloading the input source due to appropriate set average input current limit. An open-drain output (PG or GPIO/nFAULT) provides a signal to issue an interrupt to the system if any fault is detected on the device (thermal shutdown, output voltage out-of limits, and so on).

The output voltage can be dynamically adjusted between two values (floor and roof voltages) by toggling a logic control input (VSEL) without the need for external feedback resistors. This features can either be used to raise the output voltage in anticipation of a positive load transient or to dynamically change the PA supply voltage depending on its mode of operation and/or transmitting power.

The TPS61280D integrates an I2C compatible interface allowing transfers up to 3.4Mbps. This communication interface can be used to set the output voltage threshold at which the converter transitions between boost and pass-through mode, for reprogramming the mode of operation (PFM/PWM or forced PWM), for settings the average input current limit or resetting the output voltage for instance.

Configuration parameters can be changed by writing the desired values to the appropriate I2C register(s). The I2C registers are volatile and their contents are lost when power is removed from the device. By writing to the

E2PROMCTRL Register [reset = 0xFF], it is possible to store the active configuration in non-volatile E2PROM;

during power-up, the contents of the E2PROM are copied into the I2C registers and used to configure the device.

ratio, a simple circuit predicts the required on-time. At the beginning of the switching cycle, the low-

OUT

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9.2 Functional Block Diagram

TPS61280D

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( )

hmfB

ffmfB

fmh

mcfm

×+××=

+D×=+××=

)(212

( )

)(212

mcfm

ffmfB +D×=+××=

0dBV

0dBVref

ENV,PEAK

Dfc

Non-modulatedharmonic

Side-bandharmonics windowaftermodulation

TPS61280D

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9.3 Feature Description

9.3.1 Voltage Scaling Management (VSEL)

In order to maintain a certain minimum output voltage under heavy load transients, the output voltage set point can be dynamically increased by asserting the VSEL input. The functionality also helps to mitigate undershoot during severe line transients, while minimizing the output voltage during more benign operating conditions to save power.

The output voltage ramps up (floor to roof transition) at pre-defined rate defined by the average input current limit setting. The required time to ramp down the voltage (roof to floor transition) largely depends on the amount of capacitance present at the converter's output as well as on the load current. Table 1 shows the ramp rate control when transitioning to a lower voltage.

Table 1. Ramp Down Rate vs. Target Mode

Mode Associated with Floor Voltage Output Voltage Ramp Rate

Forced PWM Output capacitance is being discharged at a rate of approx. 50mA (or higher) constant current

PFM Output capacitance is being discharged (solely) by the load current drawn

9.3.2 Spread Spectrum, PWM Frequency Dithering

The goal is to spread out the emitted RF energy over a larger frequency range so that the resulting EMI is similar to white noise. The end result is a spectrum that is continuous and lower in peak amplitude, making it easier to comply with electromagnetic interference (EMI) standards and with the power supply ripple requirements in cellular and non-cellular wireless applications. Radio receivers are typically susceptible to narrowband noise that is focused on specific frequencies.

Switching regulators can be particularly troublesome in applications where electromagnetic interference (EMI) is a concern. Switching regulators operate on a cycle-by-cycle basis to transfer power to an output. In most cases, the frequency of operation is either fixed or regulated, based on the output load. This method of conversion creates large components of noise at the frequency of operation (fundamental) and multiples of the operating frequency (harmonics).

The spread spectrum architecture varies the switching frequency by ca. ±15% of the nominal switching frequency thereby significantly reducing the peak radiated and conducting noise on both the input and output supplies. The frequency dithering scheme is modulated with a triangle profile and a modulation frequency fm.

in addition to the load current drawn

Figure 15. Spectrum of a Frequency Modulated

Sin. Wave with Sinusoidal Variation in Time

The above figures show that after modulation the sideband harmonic is attenuated compared to the nonmodulated harmonic, and the harmonic energy is spread into a certain frequency band. The higher the modulation index (mf) the larger the attenuation.

(1) Spectrum illustrations and formulae (Figure 15 and Figure 16) copyright IEEE TRANSACTIONS ON ELECTROMAGNETIC

COMPATIBILITY, VOL. 47, NO.3, AUGUST 2005.

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Figure 16. Spread Bands of Harmonics in

Modulated Square Signals

(1)

( )

m c m

B = 2 1 + m = 2 +

´ ¦ ´ ´ D ¦ ¦

δ ƒ

m =

TPS61280D

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where

• fcis the carrier frequency (approx. 2.3MHz)

• fmis the modulating frequency (approx. 40kHz)

• δ is the modulation ratio (approx 0.15) (1)

(2)

The maximum switching frequency fcis limited by the process and finally the parameter modulation ratio (δ), together with fm, which is the side-band harmonics bandwidth around the carrier frequency fc. The bandwidth of a frequency modulated waveform is approximately given by the Carson’s rule and can be summarized as:

(3)

fm< RBW: The receiver is not able to distinguish individual side-band harmonics, so, several harmonics are

added in the input filter and the measured value is higher than expected in theoretical calculations.

fm> RBW: The receiver is able to properly measure each individual side-band harmonic separately, so the

measurements match with the theoretical calculations.

9.4 Device Functional Modes

9.4.1 Power-Save Mode

The TPS6128xD integrates a power-save mode to improve efficiency at light load. In power save mode the converter only operates when the output voltage trips below a set threshold voltage. It ramps up the output voltage with several pulses and goes into power save mode once the output voltage exceeds the set threshold voltage. The PFM mode is left and PWM mode entered in case the output current can not longer be supported in PFM mode.

Figure 17. Power-Save Mode Ripple

9.4.2 Pass-Through Mode

The TPS6128xD contains an internal switch for bypassing the dc/dc boost converter during pass-through mode. When the input voltage is larger than the preset output voltage, the converter seamlessly transitions into 0% duty cycle operation and the bypass FET is fully enhanced. Entry in pass-through mode is triggered by condition where V

In this mode of operation, the load (2G RF PA for instance) is directly supplied from the battery for maximum RF output power, highest efficiency and lowest possible input-to-output voltage difference. The device consumes only a standby current of 15µA (typ). In pass-through mode, the device is short-circuit protected by a very fast current limit detection scheme.

During this operation, the output voltage follows the input voltage and will not fall below the programmed output voltage threshold as the input voltage decreases. The output voltage drop during pass-through mode depends on the load current and input voltage, the resulting output voltage is calculated as:

>(1+2%)* V

OUT

OUT_NORM

and no switching has occurred during past 8µs.

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3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.9

4.1

4.2

4.3

4.4

4.5

2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 Input Voltage (V)

Output Voltage (V)

Vout_nom = 3.15V Vout_nom = 3.35V Vout_nom = 3.3V Vout_nom = 3.5V

G000

OUT

DSON(BP)

η = 1 - R

OUT IN DSON(BP) OUT

V = V - (R x I )

TPS61280D

SLVSEA0A –JANUARY 2018–REVISED AUGUST 2018

Device Functional Modes (continued)

Conversely, the efficiency in pass-through mode is defined as:

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(4)

• in which R

Pass-through mode exit is triggered when the output voltage reaches the pre-defined threshold (that is, 3.4V). During pass-through mode, the TPS6128xD device is short-circuit protected by a fast current limit detection

scheme. If the current in the pass-through FET exceeds approximately 7.3 Amps a fault is declared and the device cycles through a start-up procedure.

9.4.3 Mode Selection

Depending on the settings of CONFIG Register [reset = 0x01] the device can be operated at a quasi-constant

2.3-MHz frequency PWM mode or in automatic PFM/PWM mode. In this mode, the converter operates in pseudo-fixed frequency PWM mode at moderate to heavy loads and in the PFM mode during light loads, which maintains high efficiency over a wide load current range. For more details, see the CONFIG Register [reset =

0x01] description.

The quasi-constant frequency PWM mode has the tightest regulation and the best line/load transient performance. In forced PWM mode, the device features a unique R broadband efficiency as well as low resistance in pass-through mode.

In the TPS61280D device, the GPIO pin can be configured (via the CONFIG Register [reset = 0x01] ) to select the operating mode of the device. In the other TPS6128xD devices, the MODE pin is used to select the operating mode. Pulling this pin high forces the converter to operate in the PWM mode even at light load currents. The advantage is that the converter modulates its switching frequency according to a spread spectrum PWM modulation technique allowing simple filtering of the switching harmonics in noise-sensitive applications.

For additional flexibility, it is possible to switch from power-save mode (GPIO or MODE input = L) to PWM mode (GPIO or MODE input = H) during operation. This allows efficient power management by adjusting the operation of the converter to the specific system requirements (that is, 2G RF PA Rx/Tx operation).

Entry to forced pass-through mode (nBYP = L) initiates with a current limited transition followed by a true bypass state. To prevent reverse current to the battery, the devices waits until the output discharges below the input voltage level before entering forced pass-through mode. Care should be taken to prohibit the output voltage from collapsing whilst transitioning into forced pass-through mode under heavy load conditions and/or limited output capacitance. This can be easily done by adding capacitance to the output of the converter. In forced passthrough mode, the output follows the input below the preset output threshold voltage (VOUT_TH).

DSON(BP)

is the typical on-resistance of the bypass FET (5)

Figure 18. DC Output Voltage vs. Input Voltage

management function to maintain high

DS(ON)

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+ 39 hidden pages

Texas Instruments TPS61280D, TPS61281D, TPS61282D Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

1 Features

2 Applications

3 Description

Table of Contents

4 Revision History

5 Description (continued)

6 Device Comparison Table

7 Pin Configuration and Functions

8 Specifications

8.1 Absolute Maximum Ratings

8.2 ESD Ratings

8.3 Recommended Operating Conditions

8.4 Thermal Information

8.5 Electrical Characteristics

8.6 I2C Interface Timing Characteristics

8.7 I2C Timing Diagrams

8.8 Typical Characteristics

9 Detailed Description

9.1 Overview

9.2 Functional Block Diagram

9.3 Feature Description

9.3.1 Voltage Scaling Management (VSEL)

9.3.2 Spread Spectrum, PWM Frequency Dithering

9.4 Device Functional Modes

9.4.1 Power-Save Mode

9.4.2 Pass-Through Mode

9.4.3 Mode Selection