Texas Instruments TPS51640A, TPS59640, TPS59641 Schematic

TPS51640

VCC_CPU

VCC_GFX

Processor

3-phase CPU

Controller

IMVP-7

SVID Interface

1-phase GPU

Controller

TPS51601 FET Driver

CPU Power Stage

TPS51601 FET Driver

Internal

FET Driver

Internal

FET Driver

GPU Power Stage

UDG-11062

TPS51640A, TPS59640, TPS59641

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SLUSAQ2 –JANUARY 2012

Dual-Channel (3-Phase CPU/1-Phase GPU) SVID, D-CAP+™ Step-Down Controller for

IMVP-7 V

1

FEATURES

2

• Intel IMVP-7 Serial VID (SVID) Compliant

with Two Integrated Drivers

CORE

• Supports CPU and GPU Outputs

• CPU Channel 1, 2, or 3 Phase

• Single-Phase GPU Channel

• Full IMVP-7 Mobile Feature Set Including

Digital Current Monitor

• 8-Bit DAC with 0.250-V to 1.52-V Output Range

• Optimized Efficiency at Light and Heavy Loads

• V

Overshoot Reduction (OSR)

CORE

Undershoot Reduction (USR)

CORE

• Accurate, Adjustable Voltage Positioning

• 8 Independent Frequency Selections per

Channel (CPU/GPU)

• Patent Pending AutoBalance™ Phase Balancing

• Selectable 8-Level Current Limit

• 3-V to 28-V Conversion Voltage Range

• Two Integrated Fast FET Drivers w/Integrated

Boost FET

• Internal Driver Bypass Mode for Use with DrMOS Devices

• Small 6 × 6 , 48-Pin, QFN, PowerPAD™ Package

DESCRIPTION

The TPS51640A, TPS59640 and TPS59641 are dual-channel, fully SVID compliant IMVP-7 step-down controllers with two integrated gate drivers. Advanced control features such as D-CAP™+ architecture with overlapping pulse support (undershoot reduction, USR) and overshoot reduction (OSR) provide fast transient response, lowest output capacitance and high efficiency. All of these controllers also support single-phase operation for light loads. The full compliment of IMVP-7 I/O is integrated into the controllers including dual PGOOD signals, ALERT and VR_HOT. Adjustable control of V and voltage positioning round out the IMVP-7 features. In addition, the controllers' CPU channel includes two high-current FET gate drivers to drive high-side and low-side N-channel FETs with exceptionally high speed and low switching loss. The TPS51601 or TPS51601A driver is used for the third phase of the CPU and the GPU channel.

The BOOT voltage (V

) on the TPS51640A and

BOOT

TPS59640 is 0 V. The TPS59641 is specifically designed for a V

level of 1.1 V.

BOOT

These controllers are packaged in a space saving, thermally enhanced 48-pin QFN. The TPS51640A is rated to operate from –10°C to 105°C. The TPS59640 and TPS59641 are rated to operate from –40°C to 105°C.

CORE

slew rate

APPLICATIONS

• IMVP-7 V Battery, NVDC or 3 V/5 V/12 V rails

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2D-CAP+, PowerPAD, D-CAP are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Applications for Adapter,

CORE

SIMPLIFIED APPLICATION

TPS51640A, TPS59640, TPS59641

SLUSAQ2 –JANUARY 2012

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

www.ti.com

(1)(2)

Green (RoHS and

no Sb/Br)

250

2500

V

T

A

PACKAGE PINS ECO PLAN

BOOT

–10°C to 105°C 0

Plastic Quad Flat

Pack (QFN)

–40°C to 105°C

1.1

ORDERING INFORMATION

(V) NUMBER MEDIA QUANTITY

0 48 Tape-and-reel

ORDERABLE TRANSPORT MINIMUM

TPS51640ARSLT 250 TPS51640ARSLR 2500

TPS59640RSLT 250 TPS59640RSLR 2500

TPS59641RSLT

TPS59641RSLTR

(3)

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com. (2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. (3) Product preview. Not currently available.

ABSOLUTE MAXIMUM RATINGS

(1)(2)

over operating free-air temperature range (unless otherwise noted)

MIN TYP MAX UNIT

VBAT –0.3 32 CSW1, CSW2 –6.0 32 V CDH1 to CSW1; CDH2 to CSW2; CBST1 to CSW1; CBST2 to CSW2 –0.3 6.0

Input voltage

CTHERM, CCOMP, CF-IMAX, GF-IMAX, GCOMP, GTHERM, V5DRV, V5

COCP-I, CCSP1, CCSP2, CCSP3, CCSN1, CCSN2, CCSN3, CVFB, CGFB, V3R3, VR_ON, VCLK, VDIO, SLEWA, GGFB, GVFB, GCSN, –0.3 3.6 GCSP, GOCP-I,

PGND –0.3 0.3 VREF –0.3 1.8

Output voltage CPGOOD, ALERT, VR_HOT, GPGOOD, CIMON, GIMON –0.3 3.6 V

CPWM3, CSKIP, GPWM, GSKIP, CDL1, CDL2 –0.3 6.0

Electrotatic discharge

Operating junction temperature, T Storage temperature, T

stg

(HBM) QSS 009-105 (JESD22-A114A) 1.5 kV (CDM) QSS 009-147 (JESD22-C101B.01) 500 V

J

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to the network ground terminal unless otherwise noted.

–0.3 6.0

-40 125 °C

-55 150 °C

V

TPS51640A, TPS59640, TPS59641

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THERMAL INFORMATION

THERMAL METRIC

θ

JA

θ

JCtop

θ

JB

ψ

θ

JCbot

JT JB

Junction-to-ambient thermal resistance 31.7 Junction-to-case (top) thermal resistance 19.8 Junction-to-board thermal resistance 7.1 Junction-to-top characterization parameter 0.3 Junction-to-board characterization parameter 7.1 Junction-to-case (bottom) thermal resistance 2.1

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(1)

RECOMMENDED OPERATING CONDITIONS

MIN TYP MAX UNIT

VBAT –0.1 28 CSW1, CSW2 –3.0 30 CDH1 to CSW1; CDH2 to CSW2; CBST1 to CSW1; CBST2 to

CSW2 V5DRV, V5 4.5 5.5 V3R3 3.1 3.5

Input voltage CCOMP, GCOMP –0.1 2.5 V

CTHERM, GTHERM 0.1 3.6 CF-IMAX, GF-IMAX, COCP-I, GOCP-I 0.1 1.7 CCSP1, CCSP2, CCSP3, CCSN1, CCSN2, CCSN3, CVFB, CGFB,

GGFB, GVFB, GCSN, GCSP, VR_ON, VCLK, VDIO, SLEWA, –0.1 3.5 PGND –0.1 0.1 VREF –0.1 1.72

Output voltage V

CIMON, GIMON –0.1 V CPGOOD, ALERT, VR_HOT, GPGOOD, –0.1 V CPWM3, CSKIP, GPWM, GSKIP, CDL1, CDL2, –0.1 V

Operating free air temperature, T

A

TPS59640,TPS59641 –40 105

TPS51460A –10 105

–0.1 5.5

–0.1 1.7

SLUSAQ2 –JANUARY 2012

TPS51640A

TPS59640 TPS59641

RSL

48 PINS

UNITS

°C/W

VREF

V3R3

V5

°C

TPS51640A, TPS59640, TPS59641

SLUSAQ2 –JANUARY 2012

ELECTRICAL CHARACTERISTICS

over recommended free-air temperature range, VV5= V (Unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SUPPLY: CURRENTS, UVLO AND POWER-ON RESET

I

V5-4

I

V5-3

I

V5-2

I

V5-PS3

I

V5STBY

V

UVLOH

V

UVLOL

I

V3R3

I

V3R3SBY

V

3UVLOH

V

3UVLOL

V5 supply current CPU: 3-phase active GPU: 1-phase active

V5 supply current CPU: 2-phase active GPU: 1-phase active

V5 supply current CPU: 1-phase IV5+ I active GPU: 1-phase active

V5 supply current CPU: 3-phase active GPU: 1-phase active

V5DRV standby current VR_ON = ‘LO’, IV5+ I V5 UVLO 'OK' Threshold Ramp up, VR_ON=’HI’, 4.25 4.4 4.5 V V5 UVLO fault threshold Ramp down, VR_ON = ’HI’, 3.95 4.2 4.3 V V3R3 supply current SVID bus idle, VR_ON = ‘HI’ 0.5 1.0 mA V3R3 standby current VR_ON = ‘LO’ 10 µA V3R3 UVLO 'OK' threshold Ramp up, VR_ON=’HI’, 2.5 2.9 3.0 V V3R3 UVLO fault threshold Ramp down, VR_ON = ’HI’, 2.4 2.7 2.8 V

IV5+ I VR_ON = ‘HI’

IV5+ I VR_ON = ‘HI’, V

VR_ON = ‘HI’, V IV5+ I

VR_ON = ‘HI’, SetPS = PS3 5.1 mA (Note: 3-phase CPU goes to 1-phase in PS3)

REFERENCES: DAC, VREF, VBOOT AND DRVL DISCHARGE FOR BOTH CPU AND GPU

V

BOOT

V

VIDSTP

Boot voltage

VID step size 5 mV

0.25 ≤ V I

V

DAC1

xVFB tolerance no load active

xPU_CORE

0.25 ≤ V I

xPU_CORE

–40°C ≤ TA≤ 105°C

1.000V ≤ V I

V

DAC4

V

VREF

V

VREFSRC

V

VREFSNK

V

DLDQ

xVFB tolerance above 1 V VID

VREF Output 4.5 V ≤ VV5≤ 5.5 V, I VREF output source 0 µA ≤ I VREF output sink –500 µA ≤ I DRVL discharge threshold Soft-stop transistor turns on at this point. 200 300 mV

xPU_CORE

1.000V ≤ V I

xPU_CORE

–40°C ≤ TA≤ 105°C

VOLTAGE SENSE: xVFB AND xGFB FOR BOTH CPU AND GPU

I

xVFB

I

xGFB

A

GAINGND

xVFB input bias current V xGFB input bias current V

xVFB xVFB

xGFB/GND gain 1 V/V

CURRENT MONITOR

V

CiMONLK

V

CIMONLO

V

CIMONMID

V

CIMONHI

Zero level current output Σ∆CS = 0 mV, AIMON = 12 × (1+1.27) 35 mV Low level current output Σ∆CS = 15.6 mV, AIMON = 12 × (1+1.27) 425 mV Mid level current output Σ∆CS = 31.1 mV, AIMON = 12 × (1+1.27) 850 mV High level current output Σ∆CS = 62.3 mV, AIMON = 12 × (1+1.27) 1700 mV

ZERO-CROSSING

V

Zx

Inductor zero crossing threshold voltage

, V

V5DRV

, V

V5DRV

, V

V5DRV

, V

V5DRV

xVFB

= 0 A, 0°C ≤ TA≤ 85°C

xVFB

= 0 A, –6 8.3

xVFB

= 0 A, 0°C ≤ TA≤ 85°C

xVFB

= 0 A, –0.65% 1.0%

VREF

=2 V, V =2 V, V

V5DRV

VDAC

CCSP3

VDAC

CCSP3

VDAC

= 5.0 V; V

< V

xVFB

< V

xVFB

=3.3 V

< V

xVFB

= V

CCSP2

< V

xVFB

V5DRV

< (V

V3R3

VDAC

= 3.3 V

VDAC

= 3.3 V; V

+ 100 mV),

TPS59640

TPS51640A

TPS59641 1.1

≤ 0.995V,

TPS51640A –5 5

TPS59640 TPS59641

≤ 1.520 V,

TPS51640A –0.5% 0.5%

TPS59640 TPS59641

= 0 A 1.70 V

VREF

≤ 500 µA –4 –0.1 mV

≤ 0 µA 0.1 4 mV

=0 V 20 40 µA

xGFB

=0 V -40 -20 µA

xGFB

= V

PGND

= V

, V

GND

xVFB

6.0 9.0 mA

5.5 mA

4.9 mA

10 20 µA

0 V

0 mV

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= V

CORE

mV

TPS51640A, TPS59640, TPS59641

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ELECTRICAL CHARACTERISTICS (continued)

over recommended free-air temperature range, VV5= V (Unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

CURRENT SENSE: OVERCURRENT, ZERO CROSSING, VOLTAGE POSITIONING AND PHASE BALANCING

R

= 20 kΩ

xOCP-I

R

= 24 kΩ

xOCP-I

R

= 30 kΩ

xOCP-I

R

= 39 kΩ

xOCP-I

V

OCPP

V

IMAX

I

CS

I

xVFBDQ

G

M-DROOP

I

BAL_TOL

A

CSINT

OCP voltage (valley current limit)

R

= 56 kΩ

xOCP-I

R

= 75 kΩ

xOCP-I

R

= 100 kΩ

xOCP-I

R

= 150 kΩ

xOCP-I

IMAX values both channels

V

IMAX_MIN

V

IMAX

V

IMAX_MAX

= 133 mV, value of xIMAX,

= V

REF

= 653mV, value of xIMAX 98 A CS pin input bias current CSPx and CSNx –1.0 0.2 1.0 µA xVFB input bias current,

discharge

Droop amplifier transconductance

Internal current share tolerance –3% +3%

End of soft-stop, xVFB = 100mV 90 125 180 µA

xVFB = 1 V µS

(V

– V

(V

CSP1 CSP3

– V

CSN1

CSN3

Internal current sense gain Gain from CSPx – CSNx to PWM comparator 11.65 12.00 12.30 V/V

V5DRV

× I

MAX

) = (V ) = V

= 5.0 V; V

/ 255

– V

CSP2

OCPP_MIN

CSN2

V3R3

= 3.3 V; V

xGFB

= V

PGND

= V

TPS51640A 5.1 7.0 9.7

TPS59640 TPS59641

4.6 7.0 9.7

TPS51640A 8.1 10.0 12.6

TPS59640 TPS59641

7.6 10.0 13.1

TPS51640A 12.1 14.0 16.7

TPS59640 TPS59641

11.6 14.0 17.2

TPS51640A 17.1 19.0 21.7

TPS59640 TPS59641

16.6 19.0 22.2

TPS51640A 23.1 25.0 27.9

TPS59640 TPS59641

22.6 25.0 28.4

TPS51640A 29.7 32.0 35.0

TPS59640 TPS59641

29.2 32.0 35.5

TPS51640A 37.9 40.0 43.3

TPS59640 TPS59641

37.4 40.0 43.8

TPS51640A 46.8 49.0 52.6

TPS59640 TPS59641

46.2 49.0 53.1

TPS51640A 486 497 518

TPS59640 TPS59641

480 497 518

) =

SLUSAQ2 –JANUARY 2012

, V

xVFB

= V

CORE

GND

mV

20 A

TPS51640A, TPS59640, TPS59641

SLUSAQ2 –JANUARY 2012

ELECTRICAL CHARACTERISTICS (continued)

over recommended free-air temperature range, VV5= V (Unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

TIMERS: SLEW RATE, ISLEW, ADDR, ON-TIME AND I/O TIMING

V

t

STARTUP1

SL

STRTSTP

SL

SET

t

PGDDGLTO

t

PGDDGLTU

t

TON_CPU

Start-up time time from VR_ON until the controller responds to 5 ms

xVFB slew soft-start / soft-stop 1.25 1.50 1.75 mV/µs

Slew rate setting V

xPGOOD deglitch time 5 100 µs

xPGOOD deglitch time 150 500 µs

CPU on-time RCF=39 kΩ, V

BOOT

SVID commands SLEWRATE = 12mV/µs, VR_ON goes ‘HI’,

VR_ON goes ‘LO = ‘Soft-stop’ VSLEWA ≤ 0.30V (Also disables SVID CLK timer) 10.0 12.0 14.5 V

SLEWA

V

SLEWA

0.75 V ≤ V

SLEWA

V

SLEWA

V

SLEWA

V

SLEWA

V

SLEWA

Time from xVFB out of +220 mV VDAC boundary to xPGOOD low.

Time from xVFB out of –315 mV VDAC boundary to xPGOOD low.

RCF=20 kΩ, V (250 kHz)

RCF=24 kΩ, V (300 kHz)

RCF=30 kΩ, V (350 kHz)

(400 kHz)

RCF=56 kΩ, V (450 kHz)

RCF=75 kΩ, V (500 kHz)

RCF=100 kΩ, V RCF=150 kΩ, V

V5DRV

> 0 V, SLEWRATE = 12 mV/µs, no faults,

= 0.4 V 3.5 4.0 5.0 = 0.6 V 7.5 8.5 9.5

≤ 0.85 V 10.0 12.0 14.5

SLEWA

= 1.0 V 16 mV/µs = 1.2 V 20 = 1.4 V 23 = 1.6 V 26 ≥ 2.50 V 26

=12 V, V

BAT

=12 V, V

BAT

=12 V, V

BAT

=12 V, V

BAT

=12 V, V

BAT

=12 V, V

BAT

BAT BAT

= 5.0 V; V

=12 V, V =12 V, V

= 3.3 V; V

V3R3

DAC

=1.1 V

TPS51640A 270 327 375

TPS59640 TPS59641

DAC

=1.1 V

TPS51640A 225 272 320

TPS59640 TPS59641

DAC

=1.1 V

TPS51640A 185 235 280

TPS59640 TPS59641

=1.1 V ns

DAC

TPS51640A 160 207 252

TPS59640 TPS59641

DAC

=1.1 V

TPS51640A 140 185 231

TPS59640 TPS59641

DAC

=1.1 V

TPS51640A 120 167 212

TPS59640 TPS59641

=1.1 V (550 kHz) 109 152 198

DAC

=1.1 V (600 kHz) 105 140 177

DAC

xGFB

= V

PGND

= V

GND

265 327 380

220 272 325

180 235 285

155 207 262

134 185 241

115 167 217

, V

xVFB

= V

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CORE

TPS51640A, TPS59640, TPS59641

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ELECTRICAL CHARACTERISTICS (continued)

over recommended free-air temperature range, VV5= V (Unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

TIMERS: SLEW RATE, ISLEW, ADDR, ON-TIME AND I/O TIMING (Continued)

RGF=20 kΩ, V (275 kHz)

RGF=24 kΩ, V (330 kHz)

RGF=30 kΩ, V (385 kHz)

t

TON_GPU

t

MIN

t

VCCVID

t

VRONPGD

t

PGDVCC

t

VRTDGLT

R

SFTSTP

PROTECTION: OVP, UVP PGOOD, VR_HOT, ‘FAULTS OFF’ AND INTERNAL THERMAL SHUTDOWN

V

OVPH

V

PGDH

V

PGDL

V

THERM

I

THRM

TH

INT

TH

HYS

GPU on-time

RGF=39 kΩ,V (440 kHz)

RGF=56 kΩ, V (495 kHz)

RGF=75 kΩ, V RGF=100 kΩ, V RGF=150 kΩ, V

Controller minimum off time Fixed value 150 200 ns

ACK of SetVID-x command to start of voltage

VID change to xVFB change

(1)

ramp VR_ON low to xPGOOD low 20 50 100 ns xPGOOD low to xVFB change

(1)

VR_HOT# deglitch time 0.2 0.7 ms Soft-stop transistor resistance Connect to CVFB, GVFB 550 770 1100 Ω

Fixed OVP voltage threshold voltage

xPGOOD high threshold 190 220 245 mV

xPGOOD low threshold –348 –315 –280 mV

VCSN1 or VGCSN > V

Measured at the xVFB pin wrt/VID code,

device latches OFF

Measured at the xVFB pin wrt/VID code,

device latches OFF

bit0 of xTHERM register = high 757 783 808

bit1 of xTHERM register also is high 651 680 707

bit2 of xTHERM register also is high 611 638 663

bit3 of xTHERM register also is high 570 598 623 IMVP-7 thermal bit voltage

definition

bit4 of xTHERM register also is high 531 559 583

bit5 of xTHERM register also is high 496 523 548

bit6 of xTHERM register also is high,

ALERT goes low

bit7 of XTHERM register also is high,

VR_HOT goes low

CDLx goes low, CDHx goes low 373 410 425 THERM current Leakage current –5 5 µA Internal controller thermal

Shutdown Controller thermal SD

hysteresis

(1)

Latch off controller 155 °C

Cooling required before converter can be reset 20 °C

V5DRV

BAT

BAT BAT

= 5.0 V; V

=12 V, V

=12 V, V =12 V, V

OVPH

DAC

V3R3

=1.1 V

= 3.3 V; V

TPS51640A 315 347 388

TPS59640

xGFB

= V

TPS59641

DAC

=1.1V

TPS51640A 251 287 330

TPS59640 TPS59641

DAC

=1.1 V

TPS51640A 215 245 287

TPS59640 TPS59641

DAC

=1.1 V

TPS51640A 180 216 252

TPS59640 TPS59641

DAC

=1.1 V

TPS51640A 160 190 223

TPS59640 TPS59641

=1.1 V (550 kHz) 145 171 210

DAC

=1.1 V (605 kHz) 120 156 205

DAC

=1.1 V (660 kHz) 100 150 201

DAC

for 1 µs, DRVL → ON 1.68 1.72 1.77 V

SLUSAQ2 –JANUARY 2012

= V

, V

PGND

GND

xVFB

= V

CORE

310 347 393

246 287 335

210 245 292 ns

175 216 257

155 190 228

2 µs

100 ns

461 488 513

428 455 481

mV

(1) Specified by design. Not production tested.

TPS51640A, TPS59640, TPS59641

SLUSAQ2 –JANUARY 2012

ELECTRICAL CHARACTERISTICS (continued)

over recommended free-air temperature range, VV5= V (Unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

LOGIC (VCLK, VDIO, ALERT, VR_HOT, VR_ON) INTERFACE PINS: I/O VOLTAGE AND CURRENT

R

RSVIDL

R

RPGDL

I

VRTTLK

V

IL

V

IH

V

HYST

V

VR_ONL

V

VR_ONH

I

VR_ONH

Open drain pull down resistance 4 8 13 Ω Open drain pull down resistance xPGOOD pull-down resistance at 0.31 V 36 50 Open drain leakage current -2 0.2 2 µA Input logic low 0.45 V

Input logic high 0.65 V Hysteresis voltage

(1)

VR_ON logic low 0.3 V VR_ON logic high 0.8 V I/O 3.3 V leakage Leakage current , V

OVERSHOOT AND UNDERSHOOT REDUCTION (OSR/USR) THRESHOLD SETTING

V

OSR

V

USR

V

OSR_OFF

V

OSRHYS

OSR voltage set mV

USR voltage set mV

OSR OFF setting V OSR/USR voltage hysteresis

(2) Specified by design. Not production tested.

VDIO, ALERT, VR_HOT, pull-down resistance at

0.31 V

VR_HOT, xPGOOD, Hi-Z leakage,

apply 3.3-V in off state

VCLK, VDIO

R

= 20 kΩ 106

xSKIP

R

= 24 kΩ 156

xSKIP

R

= 30 kΩ 207

xSKIP

R

= 39 kΩ 257

xSKIP

R

= 56 kΩ 308

xSKIP

R

= 75 kΩ 409

xSKIP

R

= 100 kΩ 510

xSKIP

R

= 150 kΩ 610

xSKIP

R

= 20 kΩ 40

xSKIP

R

= 24 kΩ 60

xSKIP

R

= 30 kΩ 75

xSKIP

R

= 39 kΩ 115

xSKIP

R

= 56 kΩ 153

xSKIP

R

= 75 kΩ 190

xSKIP

R

= 100 kΩ 230

xSKIP

R

≥ 150 kΩ = OFF –

xSKIP

at start up 100 300 mV

xSKIP

(2)

All settings 20%

V5DRV

= 5.0 V; V

= 1.1 V 10 25.0 µA

VR_ON

V3R3

= 3.3 V; V

xGFB

= V

PGND

= V

, V

GND

xVFB

0.05 V

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= V

CORE

TPS51640A, TPS59640, TPS59641

www.ti.com

ELECTRICAL CHARACTERISTICS (continued)

over recommended free-air temperature range, VV5= V (Unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DRIVERS: HIGH-SIDE, LOW-SIDE, CROSS CONDUCTION PREVENTION AND BOOST RECTIFIER

(V

– V

R

DRVH

DRVH ON resistance Ω

(V

V

I

DRVH

t

DRVH

R

DRVL

I

DRVL

t

DRVL

t

NONOVLP

R

DS(on)

I

BSTLK

DRVH sink/source current

(3)

DRVH transition time CDHx 10% to 90% or 90% to 10%, C

DRVL ON resistance Ω

DRVL sink/source current

(3)

DRVL transition time ns

Driver non overlap time ns

BST on-resistance (V BST switch leakage current V

CDHx

V

CDHx

‘HI’ State, (V

‘LO’ State, (V

V

CDLx

V

CDLx

V

CDLx

V

CDLx

V

CSWx

CDLx falls to 1 V to CDHx rises to 1 V 13 25

VBST

PWM and SKIP OUTPUT: I/O Voltage and Current

V

PWML

V

PWMH

V

SKIPL

V

SKIPH

V

PW(leak)

xPWMy output low level 0.7 V xPWMy output high level 4.2 V SKIP output low level 0.7 V xSKIP output high level 4.2 V xPWM leakage Tri-state, V = 5 V 0.1 µA

(3) Specified by design. Not production tested.

CBSTx VBST

CBSTx DRVH

V5DRV

CSWx

– V

VDRVH

– V

CSWx

– VLL) = 0.25 V = 2.5 V, (V = 2.5 V, (V

= 2.5 V, Source 2.7 A = 2.5 V, Sink 6 A 90% to 10%, C 10% to 90%, C

falls to 1 V to V

– V

VBST

= 34 V, V

V5DRV

= 5.0 V; V

V3R3

= 3.3 V; V

xGFB

) = 5 V, ‘HI’ state,

) = 0.25 V

) = 5 V, ‘LO’ state,

– V

) = 5 V, Source 2.2 A

CSWx

– V

) = 5 V, Sink 2.2 A

CSWx

= 3 nF

CDHx

) = 0.25 V 0.9 2 )= 0.2 V 0.4 1

PGND

= 3 nF 15 40 = 3 nF 15 40

rises to 1 V 13 25

V5DRV

VDRVL

CBSTx CBSTx

– V

VDRVL

CDLx CDLx

CDLx

), IF= 5 mA 5 10 20 Ω

=28 V 0.1 1 µA

CSWx

= V

PGND

SLUSAQ2 –JANUARY 2012

= V

, V

xVFB

= V

GND

1.2 2.5

0.8 2.5

15 40 ns 15 40 ns

CORE

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

36

35

34

33

32

31

30

29

28

27

26

25

48

47

46

45

44

43

42

41

40

39

38

37

CTHERM

COCP-I

CIMON

CCSP1

CCSN1

CCSN2

CCSP2

CCSP3

CCSN3

CVFB

CCOMP

CGFB

CF-IMAX

VREF

V3R3

VR_ON

CPGOOD

VCLK

ALERT

VDIO

VR_HOT

SLEWA

GPGOOD

GF-IMAX

CPWM3

CSKIP

GPWM

GSKIP

GTHERM

GOCP-I

GIMON

GCSP

GCSN

GCOMP

GVFB

GGFB

V5

CDH1

CBST1

CSW1

CDL1

V5DRV

PGND

CDL2

CSW2

CBST2

CDH2

VBAT

TPS51640A

TPS59640 TPS59641

TPS51640A, TPS59640, TPS59641

SLUSAQ2 –JANUARY 2012

www.ti.com

DEVICE INFORMATION

RSL PACKAGE

48 PINS

(TOP VIEW)

PIN FUNCTIONS

NAME NO.

ALERT 19 O SVID interrupt line, open drain. Route between VCLK and VDIO to prevent cross-talk. CBST1 46 I Top N-channel FET bootstrap voltage input for CPU phase 1. CBST2 39 I Top N-channel bootstrap voltage input for CPU phase 2. CCSN1 5 CCSN2 6 I CCSN3 9 CCOMP 10 O Output of GM error amplifier for the CPU converter. A resistor to VREF sets the droop gain. CCSP1 4 CCSP2 7 I or inductor DCR sense network. Tie CCSP3, 2 or 1 (in that order) to V3R3 to disable the phase. Tie CCSP1 to CCSP3 8 CDH1 47 O Top N-channel FET gate drive output for CPU phase 1. CDH2 38 O Top N-channel FET gate drive output for CPU phase 2. CDL1 44 O Synchronous N-channel FET gate drive output for CPU phase 1. CDL2 41 O Synchronous N-channel FET gate drive output for CPU phase 2.

I/O DESCRIPTION

Negative current sense inputs for the CPU converter. Connect to the most negative node of current sense resistor or inductor DCR sense network. CCSN1 has a secondary OVP comparator.

Positive current sense inputs for the CPU converter. Connect to the most positive node of current sense resistor V3R3 to run the GPU converter only.

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TPS51640A, TPS59640, TPS59641

SLUSAQ2 –JANUARY 2012

NAME NO.

I/O DESCRIPTION

Voltage divider to VREF. A resistor to GND sets the operating frequency of the CPU converter. The voltage level

CF-IMAX 13 I sets the maximum operating current of the CPU converter. The IMAX value is an 8-bit A/D where V

I

/ 255. Both are latched at start-up.

MAX

CGFB 12 I

CIMON 3 O

COCP-I 2 I

Voltage sense return tied for the CPU converter. Tie to GND with a 10-Ω resistor to close feedback when the microprocessor is not in the socket.

Analog current monitor output for the CPU converter. V 220-nF capacitor to GND for stability.

Resistor to GND (R voltage divider to CIMON. Resistor ratio sets the IMON gain (see CIMON pin description).

) selects 1 of 8 OCP levels (per phase, latched at start-up) of the CPU converter. Also,

COCP

= ΣVCS× ACS × (1 + R

CIMON

CIMON/RCOCP

= V

IMAX

REF

). Connect a

CPGOOD 17 O IMVP-7_PWRGD output for the CPU converter. Open-drain. CSW1 45 I/O Top N-channel FET gate drive return for CPU phase 1. CSW2 40 I/O Top N-channel FET gate drive return for CPU phase 2. CPWM3 36 O PWM control for the external driver, 5V logic level.

CSKIP 35 O

CTHERM 1 I/O

CVFB 11 I

Skip mode control of the external driver for the CPU converter. A logic HI = FCCM, LO = SKIP. R to GND selects 1 of 8 OSR/USR levels. 0.1 V < V

< 0.3 V at start-up turns OSR off.

CSKIP

Thermal sensor connection for the CPU converter. A resistor connected to VREF forms a divider with an NTC thermistor connected to GND.

Voltage sense line tied directly to V feedback when µP is not in the socket. The soft-stop transistor is on this pin

of the CPU converter. Tie to V

CORE

with a 10-Ω resistor to close

CORE

Negative current sense input for the GPU converter. Connect to the most negative node of current sense resistor

GCSN 28 I or inductor DCR sense network. GCSN has a secondary OVP comparator and includes the soft-stop pull-down

transistor.

GCSP 29 I

Positive current sense input for the GPU converter. Connect to the most positive node of current sense resistor or inductor DCR sense network. Tie to V3R3 to disable the GPU converter.

GCOMP 27 O Output of gMerror amplifier for the GPU converter. A resistor to VREF sets the droop gain. GGFB 25 I

Voltage sense return tied for the GPU converter. Tie to GND with a 10-Ω resistor to close feedback when the microprocessor is not in the socket.

24 I Voltage divider to VREF. R to GND sets the operating frequency of the GPU converter. The voltage level sets

GF-IMAX the maximum operating current of the GPU converter. The IMAX value is an 8-bit A/D where V

I

/ 255. Both are latched at start-up.

MAX

GIMON

GOCP-I

30 O Analog current monitor output for the GPU converter. V

220-nF capacitor to GND for stability.

31 I Voltage divider to GIMON. Resistor ratio sets the IMON gain (see GIMON pin). Resistor to GND (R

1 of 8 OCP levels (per phase, latched at start-up) of the GPU converter.

GIMON

= V

ISENSE

× (1 + R

GIMON/RGOCP

= V

IMAX

REF

). Connect a

GOCP

×

) selects

GPGOOD 23 O IMVP-7_PWRGD output for the GPU converter. Open-drain. GPWM 34 O PWM control for the external driver, 5-V logic level.

GSKIP

GTHERM

GVFB

33 O Skip mode control of the external driver for the GPU converter, 5-V logic level. Logic HI = FCCM, LO = SKIP. R

to GND selects 1 of 8 OSR/USR levels. 0.1 V < V

< 0.3 V at start-up turns OSR off.

GSKIP

32 I/O Thermal sensor input for the GPU converter. A resistor connected to VREF forms a divider with an NTC

thermistor connected to GND.

26 I Voltage sense line tied directly to V

when the microprocessor is not in the socket. The soft-stop transistor is on this pin

of the GPU converter. Tie to V

GFX

with a 10-Ω resistor to close feedback

GFX

PGND 42 – Synchronous N-channel FET gate drive return. SLEWA

V5

V5DRV

22 I The voltage at start-up sets 1 of 7 slew rates for both converters. The SLOW rate is SLEWRATE/4. Soft-start

and soft-stop rates are SLEWRATE/8. This value is latched at start-up. Tie to GND to disable SCLK timer.

48 I 5-V power input for analog circuits; connect through resistor to 5-V plane and bypass to GND with ≥1 µF ceramic

capacitor

43 I Power input for the gate drivers; connected with an external resistor to V5F; decouple with a ≥2.2 µF ceramic

capacitor.

V3R3 15 I 3.3-V power input; bypass to GND with ≥1 µF ceramic cap. VBAT

37 I Provides VBAT information to the on-time circuits for both converters. A 10-kΩ series resistor protects the

adjacent pins from inadvertent shorts due to solder bridges or mis-probing during test. VCLK 18 I SVID clock. 1-V logic level. VDIO 20 I/O SVID digital I/O line. 1-V logic level. VREF 14 O 1.7-V, 500-µA reference. Bypass to GND with a 0.22-µF ceramic capacitor.

×

TPS51640A, TPS59640, TPS59641

SLUSAQ2 –JANUARY 2012

www.ti.com

NAME NO.

VR_ON 16 I IMVP-7 VR enable; 1V I/O level; 100-ns de-bounce. Regulator enters controlled soft-stop when brought low. VR_HOT PAD GND – Thermal pad and analog circuit reference; tie to a quiet area in the system ground plane with multiple vias.

I/O DESCRIPTION

21 O IMVP-7 thermal flag open drain output – active low. Typically pulled up to 1-V logic level through 56 Ω. Fall time

< 100 ns. 1-ms de-glitch using consecutive 1-ms samples.

0.80

0.85

0.90

0.95

1.00

1.05

Output Voltage (V)

VIN= 9 V VIN= 20 V Nominal

Specified Maximum

Specified Minimum

V

VID

= 1.05 V

0 10 20 90 100

Output Current (A)

30 40 50 70 8060

0.500

0.525

0.575

0.600

0.625

0.675

0.700

0 2 4 18 20

Output Current (A)

Output Voltage (V)

6 8 10 14 1612

VIN= 9 V VIN= 20 V Nominal

Specified Maximum

Specified Minimum

V

VID

= 0.6 V

0.550

0.650

65

75

80

85

90

Efficiency (%)

V

VID

= 0.6 V

70

VIN= 9 V VIN= 20 V

0 2 4 18 20

Output Current (A)

6 8 10 14 1612

65

75

80

85

90

95

Efficiency (%)

V

VID

= 1.05 V

70

VIN= 9 V VIN= 20 V

0 10 20 90 100

Output Current (A)

30 40 50 70 8060

0

100

150

200

350

400

Frequency (Hz)

50

0 10 20 90 100

Output Current (A)

30 40 50 70 8060

RCF= 24 kW

PS0, V

VID

= 1.05 V, VIN= 9 V

PS0, V

VID

= 1.05 V, VIN= 20 V

PS1, V

VID

= 1.05 V, VIN= 20 V

PS1, V

VID

= 1.05 V, VIN= 9 V

250

300

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TPS51640A, TPS59640, TPS59641

SLUSAQ2 –JANUARY 2012

TYPICAL CHARACTERISTICS

3-Phase Configuration, 94-A CPU

Figure 1. Output Voltage vs. Load Current in PS0 Figure 2. Output Voltage vs. Load Current in PS1

Figure 3. Efficiency vs. Load Current in PS0 Figure 4. Efficiency vs. Load Current in PS1

Figure 5. Frequency vs Load-Current (PS0 and PS1) Figure 6. Switching Ripple in PS0, VIN= 20 V

TPS51640A, TPS59640, TPS59641

SLUSAQ2 –JANUARY 2012

TYPICAL CHARACTERISTICS

3-Phase Configuration, 94-A CPU (continued)

Figure 7. Start-Up and PGOOD Figure 8. Soft-Stop

(TPS51640A and TPS59640 Only)

www.ti.com

Figure 9. Load Transient, VIN= 9 V, Load step = 66 A Figure 10. Load Transient, VIN= 20 V, Load step = 66 A

Figure 11. Load Insertion, VIN= 9 V, Load step = 66 A Figure 12. Load Release, VIN= 20 V, Load step = 66 A

100 1000 10000 100000 1000000

−50

−40

−30

−20

−10

0

10

20

30

40

50

−225

−180

−135

−90

−45

0

45

90

135

180

225

Frequency (Hz)

Magnitude (dB)

Phase (°)

Gain Phase

3−Phase CPU V

OUT

= 1.05 V

I

OUT

~ 20 A

0.0005

0.001

0.0015

0.002

0.0025

0.003

0.0035

0.004

0.0045

-80

-60

-40

-20

0

20

40

60

80

100 1 k 10 k 100 k 1 M

Frequency (Hz)

Z

OUT

Magnitude (W)

Z

OUT

Phase (°)

Magnitude Target Phase

CPU

3-Phase

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TPS51640A, TPS59640, TPS59641

SLUSAQ2 –JANUARY 2012

TYPICAL CHARACTERISTICS

3-Phase Configuration, 94-A CPU (continued)

Figure 13. Dynamic VID: SetVID-Slow/SetVID-Slow Figure 14. Dynamic VID: SetVID-Fast/SetVID-Fast

Figure 15. SetVID-Decay/SetVID-Fast Figure 16. PS Change PS0 to PS1 Toggle

Figure 17. CPU Bode Plot Figure 18. Output Impedance

0.80

0.85

0.90

0.95

1.00

1.05

1.10

Output Voltage (V)

0 10 20

Output Current (A)

30 40 50 60

V

VID

= 1.05 V

VIN= 9 V VIN= 20 V Nominal

Specified Maximum

Specified Minimum

65

75

80

85

90

95

Efficiency (%)

70

0 5 10 50 55

Output Current (A)

15 20 25 40 4535

VIN= 9 V VIN= 20 V

V

VID

= 1.05 V

30

TPS51640A, TPS59640, TPS59641

SLUSAQ2 –JANUARY 2012

TYPICAL CHARACTERISTICS

2-Phase Configuration, 53-A CPU

Figure 19. Output Voltage Vs. Load Current in PS0 Figure 20. Efficiency Vs. Load Current in PS0

www.ti.com

Figure 21. Switching Ripple in PS0 (Persistence), Figure 22. Switching Ripple in PS0 (Persistence),

Figure 23. Switching Ripple in PS0, VIN= 9 V Figure 24. Switching Ripple in PS0, VIN= 20 V

VIN= 9 V VIN= 20 V

www.ti.com

TPS51640A, TPS59640, TPS59641

SLUSAQ2 –JANUARY 2012

TYPICAL CHARACTERISTICS

2-Phase Configuration, 53-A CPU (continued)

Figure 25. Load Transient, VIN= 9 V, Load Step = 43 A Figure 26. Load Transient, VIN= 20 V, Load Step = 43 A

Figure 27. Load Insertion, VIN= 9 V, Load Step = 43 A, Figure 28. Load Release, VIN= 20 V, Load Step = 43 A,

Figure 29. Load Insertion, VIN= 9 V, Load Step = 43 A, Figure 30. Load Release,VIN= 20 V, Load Step = 43 A,

OSR/USR Setting 39 kΩ (Reduced Output Capacitance) OSR/USR Setting 39 kΩ (Reduced Output Capacitance)

OSR/USR Setting 150 kΩ) OSR/USR Setting 150 kΩ)

Texas Instruments TPS51640A, TPS59640, TPS59641 Schematic [ru]

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

DESCRIPTION

APPLICATIONS

SIMPLIFIED APPLICATION

ABSOLUTE MAXIMUM RATINGS

THERMAL INFORMATION

RECOMMENDED OPERATING CONDITIONS

ELECTRICAL CHARACTERISTICS

DEVICE INFORMATION

PIN FUNCTIONS