Texas Instruments TPS56300PWPR, TPS56300PWP, TPS56300EVM-139 Datasheet

TPS56300

DUAL-OUTPUT LOW-INPUT-VOLTAGE

DSP POWER SUPPLY CONTROLLER WITH SEQUENCING

SLVS261A – DECEMBER 1999 – JANUAR Y 2000

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

2.8 V – 5.5 V Input Voltage Range

D

Programmable Dual Output Controller
Supports Popular DSP and Microcontroller
Core and I/O Voltages
– Switching Regulator Controls Core

Voltage

– Low Dropout Controller Regulates I/O

Voltage

D

Programmable Slow-Start Ensures
Simultaneous Powerup of Both Outputs

D

Power Good Output Monitors Both Outputs

D

Fast Ripple Regulator Reduces Bulk
Capacitance for Lower System Costs

D

±1.5% Reference V oltage Tolerance

D

Efficiencies Greater than 90%

D

Overvoltage, Undervoltage, and Adjustable
Overcurrent Protection

D

Drives Low-Cost Logic Level N-Channel
MOSFETs Through Entire Input Voltage
Range

D

Evaluation Module TPS56300EVM–139
Available

description

The high performance TPS56300 synchronous-buck regulator provides two supply voltages to power the core
and I/O of digital signal processors, such as the ‘C6000 family . The ripple regulator, using hysteretic control with
droop compensation, is configured for the core voltage and features fast transient response time reducing
output bulk capacitance (continued).

typical design

+

++

See Note A
See Note A

NOTE A: See Table 1

Copyright  2000, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1
2
3
4
5
6
7
8
9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

VID0
VID1

SLOWST

VHYST
VREFB

VSEN–RR

ANAGND

BIAS

VLDODRV

CPC1

V

CC

CPC2

VDRV

DRVGND

DROOP
OCP
IOUT
PWRGD
VSEN–LDO
NGATE–LDO
INHIBIT
IOUTLO
HISENSE
LOSENSE/LOHIB
HIGHDR
BOOT
BOOTLO
LDWDR

PWP PACKAGE

(TOP VIEW)

Thermal

Pad

PowerPAD Package

PowerPAD is a trademark of Texas Instruments Incorporated.

TPS56300
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING

SLVS261A – DECEMBER 1999 – JANUAR Y 2000

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description (continued)

The LDO controller drives an external N-channel power MOSFET and functions as an LDO regulator, suitable
for powering the I/O or as a power distribution switch. To promote better system reliability during power up,
voltage sequencing and protection are controlled such that the core and I/O power up together with the same
slow-start voltage. At power down, the LDO and ripple regulator are discharged towards ground for added
protection. The TPS56300 also includes inhibit, slowstart, and under-voltage lockout features to aide in
controlling power sequencing. A tri-level voltage identification network (VID) sets both regulated voltages to any
of 9 preset voltage pairs from 1.3 V to 3.3 V . Other voltages are possible by implementing an external voltage
divider. Strong MOSFET drivers, with a typical peak current rating of 2-A sink and source are included on chip,
enabling high system currents beyond 30 A. The high-side driver features a floating bootstrap driver with the
internal bootstrap synchronous rectifier. Many protection features are incorporated within the device to ensure
better system integrity . An open-drain output POWER GOOD status circuit monitors both output voltages, and
is pulled low if either output fall below the threshold. An over current shutdown circuit protects the high-side
power MOSFET against short-to-ground faults at load or the phase node, while over voltage protection turns
off the output drivers and LDO controller if either output exceeds its threshold. Under voltage protection turns
off the high-side and low-side MOSFET drivers and the LDO controller if either output is 25% below V

REF

.
Lossless current-sensing is done by detecting the drain-source voltage drop across the high-side power
MOSFET while it is conducting. The TPS56300 is fully compliant with TI DSP power requirements such as the
‘C6000 family.

AVAILABLE OPTIONS

PACKAGES

T

J

TSSOP

†

(PWP)

EVALUATION MODULE

–40°C to 125°C TPS56300PWP TPS56300EVM–139 (SLVP139)

†

The PWP package is also available taped and reel. To order, add an R to the end of
the part number (e.g., TPS56300PWPR).

TPS56300

DUAL-OUTPUT LOW-INPUT-VOLTAGE

DSP POWER SUPPLY CONTROLLER WITH SEQUENCING

SLVS261A – DECEMBER 1999 – JANUAR Y 2000

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

23

24

VLDODRV

NGATE–LDO

VSEN–LDO

RR_OVP

LDO_OVP

RR_UVP *

LDO_UVP *

SHUTDOWN

VID

2

1

VID0

VID1

Vref_LDO

Vref_RR

5

VREFB

Hysteresis

Setting

+

–

28

VHYST

6

VSEN–RR

Hysteresis

Comparator

Adaptive

Deadtime

15

18

16

14

17

VDRV

BOOT

HIGHDR

BOOTLO

LOWDR

DRVGND

22

11

INHIBIT

Vcc

VDRV UVLO

Vcc UVLO

3

SLOWST

SHUTDOWN

+

–

–

+

Delay

26202119

LOSENSE/

LOHIB

IOUTLO HISENSE

IOUT

HIGHDR

Ivrefb/5

Vbias

8

Bias

7

Reg.

VLDODRV

25

>0.93xVSEN–RR

>0.93xVSEN–LDO

4

DROOP

PWRGD

ANAGND

SHUTDOWN

27

125 mV

OCP

RS

Q

Fault

Latch

SHUTDOWN

INHIBIT

SLOWST

SLOWST

SHUTDOWN

SHUTDOWN

5 V

10

CPC1

9

12

CPC2

13

VDRV

VDRV

BOOT

–

+

E/A

Synchronous

FET

RR–Ripple Regulator

See table 1

VDRV

* UVP is disabled during

slowstart

TPS56300
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING

SLVS261A – DECEMBER 1999 – JANUAR Y 2000

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

NAME NO.

DESCRIPTION

VID0 1 Voltage Identification input 0. VID pins are tri-level programming pins that set the output voltages for both convert-

ers. The code pattern for setting the output voltage is located in table 1. The VID pins are internally pulled to

Vbias/2, allowing floating voltage set to logic 1 (see table 1).
VID1 2 Voltage Identification input 1 (see VID0 above and table 1).
SLOWST 3 Slow start (soft start). A capacitor from pin 3 to GND sets the slowstart time for VOUT-RR and VOUT-LDO. Both

supplies will ramp-up together while tracking the slow-start voltage.
VHYST 4 Hysteresis set pin. The hysteresis is set by 2 × (VREFB – Vhyst).
VREFB 5 Buffered ripple regulator reference voltage from VID network.
VSEN-RR 6 Ripple regulator VOL TAGE SENSE input. This pin is connected to the ripple regulator output. It is used to sense

the ripple regulator voltage for regulation, OVP, UVP, and Powergood functions.. It is recommended that an RC

low pass filter be connected at this pin to filter high frequency noise.
ANAGND 7 Analog ground
BIAS 8 Analog BIAS pin. Recommended that a 1-µF capacitor be connected to ANAGND.
VLDODRV 9 Output of charge pump generated through bootstrap diode. Approximately equal to VDRV + VIN – 300mV . Used

as supply for LDO driver and Bias regulator. Recommended that a 1-µF capacitor be connected to DRVGND.
CPC1 10 Connect one end of Charge pump capacitor. Recommended that a 1-µF capacitor be connected from CPC1 to

CPC2.
V

CC

11 3.3 V or 5 V supply (2.8 V – 5.5 V). Recommended that a low ESR capacitor be connected directly from VCC to

DRVGND. (Bulk capacitors supplied at power stage input).
CPC2 12 Other end of charge pump capacitor from CPC1.
VDRV 13 Regulated output of internal charge pump. Supplies DRIVE charge for the low-side MOSFET driver (5V). Recom-

mended that a 10-µF capacitor be connected to DRVGND.
DRVGND 14 Drive ground. Ground for FET drivers. Connect to source of low-side FET.
LOWDR 15 Low drive. Output drive to synchronous rectifier low-side FET.
BOOTLO 16 Bootstrap low. This pin connects to the junction of the high-side and low-side FETs.
BOOT 17 Bootstrap pin. Connect a 1-µF low ESR capacitor to BOOTLO to generate floating drive for the high-side FET

driver.
HIGHDR 18 High drive. Output drive to high-side power switching FETs
LOSENSE/

LOHIB

19 Low sense/low-side inhibit. This pin is connected to the junction of the high and low-side FETs and is used in cur-

rent sensing and the anti-cross-conduction to eliminate shoot-through current.
HISENSE 20 High current sense. For current sensing across high-side FETs, connect to the drain of the high-side FETs.
IOUTLO 21 Current sense low output. Voltage on this pin is the voltage on the LOSENSE pin when the high-side FETs are on.
INHIBIT 22 Inhibits the drive signals to the MOSFET drivers. IC is in low Iq state if INHIBIT is grounded. It is recommended

that an external pullup resistor be connected to 5 V .
NGATE-LDO 23 Drives external N-channel power MOSFET to regulate LDO voltage to VREF-LDO.
VSEN–LDO 24 LDO voltage sense. This pin is connected to the LDO output. It is used to sense the LDO voltage for regulation,

OVP, UVP, and power good functions.
PWRGD 25 Power good. Power good signal goes high when output voltage is about 93% of V

REF

for both ripple regulator and

LDO. This is an open-drain output.

TPS56300

DUAL-OUTPUT LOW-INPUT-VOLTAGE

DSP POWER SUPPLY CONTROLLER WITH SEQUENCING

SLVS261A – DECEMBER 1999 – JANUAR Y 2000

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions (continued)

TERMINAL

NAME NO.

I/O

DESCRIPTION

IOUT 26 Current signal output. Output voltage on this pin is proportional to the load current as measured across

the high-side FETs on-resistance. The voltage on this pin equals 2 × RON× IOUT, where Ron is the
equivalent on-resistance of the high-side FETs

OCP 27 Over current protection. Current limit trip point for ripple regulator is set with a resistor divider between

IOUT pin and

ANAGND.

DROOP 28 Droop voltage. Voltage input used to set the amount of output voltage droop as a function of load current.

The amount of droop compensation is set with a resistor divider between the IOUT pin and ANAGND.

Table 1. Voltage Identification Code

§¶

VID Terminals

†

VREF–RR

‡

VREF–LDO

‡

VID1 VID0

(Vdc) (Vdc)

0 0 1.30 1.5
0 1 1.50 1.80
0 2 1.30 1.80
1 0 1.80 3.30
1 1 1.30 1.30
1 2 2.50 3.30
2 0 1.30 2.50
2 1 1.50 3.30
2 2 1.80 2.50

†

0 = ground (GND), 1 = floating(Vbias/2), 2 = (Vbias)

‡

RR = Ripple Regulator, LDO = Low Drop-Out Regulator

§

Vbias/2 is internal, leave VID pin floating. Adding an external 0.1-µF capacitor to ANAGND may be used to
avoid erroneous level.

¶

External resistors may be used as a voltage divider (from V

OUT

to VSEN–xx to Gnd) to program output

voltages to other values.

TPS56300
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING

SLVS261A – DECEMBER 1999 – JANUAR Y 2000

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating virtual junction temperature (unless otherwise noted)

†

Supply voltage range, V

CC

(see Note1) –0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range: VDRV –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

BOOT to DRVGND (High-side Driver ON) –0.3 V to 15 V. . . . . . . . . . . . . . . . . . . . . . . . .

BOOT to BOOTLO –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

BOOT to HIGHDRV –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

BOOTLO to DRVGND –0.5 V to 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DRV to DRVGND –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

BIAS to ANAGND –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

INHIBIT –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DROOP –0.3 V to V

CC

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OCP –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

VID0, VID1 (tri-level terminals) –0.3 V to VBIAS + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . .

PWRGD –0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

LOSENSE, LOHIB –0.5 V to 14 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IOUTLO –0.3 V to 14 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

HISENSE –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

VSEN–LDO –0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

VSEN–RR –0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage difference between ANAGND and DRVGND ±300 mV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating virtual junction temperature range, T

J

–40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds 300°C. . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: Unless otherwise specified, all voltages are with respect to ANAGND.

DISSIPATION RATING TABLE

PWP

TA < 25°C Derating Factor

‡

TA = 70°C TA = 85°C

PowerPAD mounted 3.58 W 0.0358 W/°C 1.96 W 1.43 W
PowerPAD unmounted 1.78 W 0.0178 W/°C 0.98 W 0.71 W

JUNCTION-CASE THERMAL RESISTANCE TABLE

Junction-case thermal resistance

0.72 °C/W

‡

Test Board Conditions:

1. Thickness: 0.062”

2. 3”x 3” (for packages < 27 mm long)

3. 4” x 4” (for packages > 27 mm long)

4. 2 oz. Copper traces located on the top of the board (0.071 mm thick )

5. Copper areas located on the top and bottom of the PCB for soldering

6. Power and ground planes, 1oz. Copper (0.036 mm thick)

7. Thermal vias, 0.33 mm diameter, 1.5 mm pitch

8. Thermal isolation of power plane
For more information, refer to TI technical brief SLMA002.

TPS56300

DUAL-OUTPUT LOW-INPUT-VOLTAGE

DSP POWER SUPPLY CONTROLLER WITH SEQUENCING

SLVS261A – DECEMBER 1999 – JANUAR Y 2000

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics TJ = 0° to 125°C, VCC = 2.8 V to 5.5 V (unless otherwise noted)

input

PARAMETER CONDITIONS MIN TYP MAX UNITS

VCC Supply voltage range 2.8 3.3 5.5 V
ICC Quiescent current

INHIBIT = 0 V,
VCC = 5 V

15 mA

NOTE 2. Ensured by design, not production tested.

reference/voltage identification

PARAMETER CONDITIONS MIN TYP MAX UNITS

D0–D1 High level input voltage (2) Vbias – 0.3 V V
D0–D1 Mid level floating voltage (1)

V

bias

2

*

1

V

bias

2

)

1

V

D0–D1 Low level input voltage (0) 0.3 V
Input pull-to-mid resistance 36.5 73 95 KΩ

cumulative reference

PARAMETER CONDITIONS MIN TYP MAX UNITS

V

REF

= 1.3 V, Hysteresis window = 30 mV,

TJ = 25°C

–1.3 0.25 1.3

Cumulative accuracy ripple regulator

V

REF

= 1.3 V, Hysteresis window = 30 mV,

TJ = –40°C, See Note 2

–0.2

%

V

REF

= full range, Hysteresis window = 30 mV,

Droop = 0, See Note 2

–1.5 1.5

V

REF

= 1.3 V, IO=0.1 A,
Closed Loop, Pass device = IRFZ24N,
TJ = 25°C, See Note 2

–2 2

Cumulative accuracy LDO

V

REF

= full range, IO=0.1 A,
Closed Loop, Pass device = IRFZ24N,
See Note 2

–2.5 2.5

%

NOTE 2. Ensured by design, not production tested.

hysteretic comparator(ripreg)

PARAMETER CONDITIONS MIN TYP MAX UNITS

Input bias current See Note 2 500 nA
Hysteresis accuracy

V

VREFB

– V

VHYST

= 15 mV,

Hysteresis window = 30mV

–3.5 3.5 mV

Maximum hysteresis setting V

VREFB

– V

VHYST

= 30 mV , See Note 2 60 mV

Propagation delay time from VSENSE to
HIGHDR or LOWDR
(excluding deadtime)

10 mV overdrive, 1.3 V <= V

REF

<= 3.3 V

See Note 2

150 250 ns

Prefilter pole frequency See Note 2 5 MHz

NOTE 2. Ensured by design, not production tested.

TPS56300
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING

SLVS261A – DECEMBER 1999 – JANUAR Y 2000

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics TJ = 0° to 125°C, VCC = 2.8 V to 5.5 V (unless otherwise noted)

overvoltage protection

PARAMETER CONDITIONS MIN TYP MAX UNITS

OVP ripple regulator trip point (RR) Upper threshold 112 115 120 % V

REF

Hysteresis (RR)

Upper threshold – lower threshold,
See Note 2

10 mV

Comparator propagation delay time (RR) V

overdrive

= 30mV , See Note 2 1 µs

Deglitch time (includes comparator
propagation delay time) (RR)

V

overdrive

= 30mV , See Note 2 2.25 11 µs

OVP LDO trip point (LDO) Upper threshold 112 115 120 % V

REF

Hysteresis (LDO)

Upper threshold – lower threshold,
See Note 2

10 mV

Comparator propagation delay time (LDO) V

overdrive

= 50mV , See Note 2 1 µs

Deglitch time (includes comparator
propagation delay time) (LDO)

V

overdrive

= 50mV , See Note 2 2.25 11 µs

NOTE 2. Ensured by design, not production tested.

undervoltage protection

PARAMETER CONDITIONS MIN TYP MAX UNITS

UVP ripple regulator trip point (RR) Lower threshold 70 75 80 % V

REF

Hysteresis (RR)

Upper threshold – lower threshold,
See Note 2

10 mV

Comparator propagation delay time (RR) V

overdrive

= 50mV , See Note 2 1 µs

Deglitch time (includes comparator
propagation delay time) (RR)

V

overdrive

= 50mV , See Note 2 0.1 1 ms

UVP LDO trip point (LDO) Lower threshold 70 75 80 % V

REF

Hysteresis (LDO)

Upper threshold – lower threshold,
See Note 2

10 mV

Comparator propagation delay time (LDO) V

overdrive

= 50mV , See Note 2 1 µs

Deglitch time (includes comparator
propagation delay time) (LDO)

V

overdrive

= 50mV , See Note 2 0.1 1 ms

NOTE 2. Ensured by design, not production tested.

inhibit comparator

PARAMETER CONDITIONS MIN TYP MAX UNITS

2.1 2.35

Start threshold

TJ = –40°C, See Note 2 2.1

V

Stop threshold 1.79 V

NOTE 2. Ensured by design, not production tested.

VDRV UVLO

PARAMETER CONDITIONS MIN TYP MAX UNITS

Start threshold See Note 2 4.9 V
Hysteresis See Note 2 0.3 0.35 V
Stop threshold See Note 2 4.4 V

NOTE 2. Ensured by design, not production tested.

TPS56300

DUAL-OUTPUT LOW-INPUT-VOLTAGE

DSP POWER SUPPLY CONTROLLER WITH SEQUENCING

SLVS261A – DECEMBER 1999 – JANUAR Y 2000

9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics TJ = 0° to 125°C, VCC = 2.8 V to 5.5 V (unless otherwise noted)

slowstart

PARAMETER CONDITIONS MIN TYP MAX UNITS

Charge current

V

(S/S)

= 0.5V ,
Resistance from VREFB pin to ANAGND = 20 kΩ
VREFB = 1.3 V, Ichg = (I

VREFB

/5)

10.4 13 15.6 µA

Discharge current V

(S/S)

= 1.3 V 3 mA

Comparator input offset voltage 10 mV
Comparator input bias current See Note 2 10 100 nA
Hysteresis accuracy –7.5 7.5 mV
Comparator propagation delay Overdrive = 10 mV, See Note 2 560 1000 ns

NOTE 2. Ensured by design, not production tested.

VCC UVLO

PARAMETER CONDITIONS MIN TYP MAX UNITS

See Note 2 2.72 2.80

Start threshold

TJ = –40°C, See Note 2 2.71

V

Stop threshold See Note 2 2.48 V

NOTE 2. Ensured by design, not production tested.

power good

PARAMETER CONDITIONS MIN TYP MAX UNITS

Undervoltage trip point ripple regulator

VIN and VDRV above UVLO thresholds 90 93 95

gg

(VSENSE–RR)

TJ = –40°C, See Note 2 93

% V

REF

Undervoltage trip point LDO

VIN and VDRV above UVLO thresholds 90 93 95

g

(VSENSE–LDO)

TJ = –40°C, See Note 2 93

% V

REF

Output saturation voltage IO=5 mA 0.5 0.75 V
Leakage current V

PGD

= 4.5V 1 µA

V

REF

= 1.3V , 1.5V, or 1.8V 50 75 mV

Hysteresis

V

REF

= 2.5V , or 3.3V 100 125 mV

Comparator high–low transition time
(propagation delay only)

See Note 2 1 µs

Comparator low–high transition time
(propagation delay + deglitch)

See Note 2 0.2 1 2 ms

NOTE 2. Ensured by design, not production tested.

droop compensation

PARAMETER CONDITIONS MIN TYP MAX UNITS

Initial accuracy V

DROOP

= 50 mV 46 54 mV

overcurrent protection (RR)

PARAMETER CONDITIONS MIN TYP MAX UNITS

OCP trip point 118 130 142 mV
Input bias current 300 nA
Comparator propagation delay time V

overdrive

= 30mV , See Note 2 1 µs

Deglitch time (includes comparator
propagation delay time)

V

overdrive

= 30mV , See Note 2 2.25 11 µs

NOTE 2. Ensured by design, not production tested.

TPS56300
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING

SLVS261A – DECEMBER 1999 – JANUAR Y 2000

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics TJ = 0° to 125°C, VCC = 2.8 V to 5.5 V (unless otherwise noted)

high-side VDS sensing

PARAMETER CONDITIONS MIN TYP MAX UNITS

Gain 2 V/V
Initial accuracy

V

HISENSE

= 3.3 V, V

IOUTLO

= 3.2 V,

Differential input to Vds sensing amp = 100 mV

194 208 mV

Common-mode rejection ratio

V

HISENSE

=2.8 V to 5.5 V ,

V

HISENSE

– V

IOUTLO

=100 mV

69 75 dB

Sink current (IOUTLO) 2.8 V < V

IOUTLO

< 5.5 V 250 nA

Source current (IOUT)

V

IOUT

= 0.5 V, V

HISENSE

=3.3 V ,

V

IOUTLO

=2.8 V

500 µA

Sink current (IOUT)

V

IOUT

= 0.05 V , V

HISENSE

=3.35 V ,

V

IOUTLO

=3.3 V

50 µA

V

HISENSE

=5.5 V , R

IOUT

= 10 kΩ 0 1.75

Output voltage swing

V

HISENSE

=4.5 V , R

IOUT

= 10 kΩ 0 1.5

V

V

HISENSE

=3 V, R

IOUT

= 10 kΩ 0 0.75

LOSENSE high level input voltage V

HISENSE

=2.8 V , See Note 2 1.77 V

LOSENSE low level input voltage V

HISENSE

=2.8 V , See Note 2 1.49 V

LOSENSE high level input voltage V

HISENSE

=4.5 V , See Note 2 2.85 V

LOSENSE low level input voltage V

HISENSE

=4.5 V , See Note 2 2.4 V

LOSENSE high level input voltage V

HISENSE

=5.5 V , See Note 2 3.80 V

LOSENSE low level input voltage V

HISENSE

=5.5 V , See Note 2 3.2 V

V

HISENSE =

6 V, See Note 2 70 90

p

V

HISENSE =

4.5 V , See Note 2 80 100

Sample/hold resistance

V

HISENSE =

3.6 V , See Note 2 90 120

Ω

V

HISENSE =

2.8 V , See Note 2 120 180

V

HISENSE

= 2.55 V ,

V

IOUTLO

pulsed from 2.55 V to 2.45 V ,

100 ns rise and fall times, See Note 2

4

Response time (measured from 90% of

V

HISENSE

= 2.8 V,

V

IOUTLO

pulsed from 2.8 V to 2.7 V ,

100 ns rise and fall times, See Note 2

3.5

(

V

IOUTLO

to 90% of V

IOUT

)

V

HISENSE

= 4.5 V,

V

IOUTLO

pulsed from 4.5V to 4.4V ,

100 ns rise and fall times, See Note 2

3

µ

s

V

HISENSE

= 5.5 V,

V

IOUTLO

pulsed from 5.5 V to 5.9 V ,

100 ns rise and fall times, See Note 2

3

Short circuit protection rising edge delay LOSENSE grounded, See Note 2 300

500

ns

Sample/hold switch turnon/turnoff delay

2.8V < V

HISENSE

< 5.5V ,

V

LOSENSE

= V

HISENSE

, See Note 2

30

100

ns

NOTE 2. Ensured by design, not production tested.

TPS56300

DUAL-OUTPUT LOW-INPUT-VOLTAGE

DSP POWER SUPPLY CONTROLLER WITH SEQUENCING

SLVS261A – DECEMBER 1999 – JANUAR Y 2000

11

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics TJ = 0° to 125°C, VCC = 2.8 V to 5.5 V (unless otherwise noted)

buffered reference

PARAMETER CONDITIONS MIN TYP MAX UNITS

p

I

REFB

=50 µA, Accuracy from V

REF

nominal

V

REF

–1.5%

V

REF

V

REF

+1.5%

VREFB output voltage

I

REFB

=50 µA, Accuracy from V

REF

nominal

TJ = –40°C, See Note 2

V

REF

–0.6%

V

VREFB load regulation 10 µA < I

REFB

< 500 µA 2 mV

NOTE 2. Ensured by design, not production tested.

thermal shutdown

PARAMETER CONDITIONS MIN TYP MAX UNITS

Over temperature trip point See Note 2 145 °C
Hysteresis See Note 2 10 °C

NOTE 2. Ensured by design, not production tested.

synch charge pump regulator

PARAMETER CONDITIONS MIN TYP MAX UNITS

Internal oscillator frequency 2.8 V < VIN < 5.5 V, I

DRV

= 50 mA, VDRV=5 V 200 300 400 kHz
Internal oscillator turnon threshold VCC above UVLO threshold, See Note 2 5.05 5.2 V
Internal oscillator turnon hysteresis VCC above UVLO threshold, See Note 2 20 mV

NOTE 2. Ensured by design, not production tested.

hysteretic comparator (charge pump)

PARAMETER CONDITIONS MIN TYP MAX UNITS

Threshold VIN above UVLO threshold, See Note 2 5.05 5.2 V
Hysteresis VIN above UVLO threshold, See Note 2 20 mV

NOTE 2. Ensured by design, not production tested.

bias regulator

PARAMETER CONDITIONS MIN TYP MAX UNITS

Output voltage 2.8V < VIN < 5.5 V , Rip reg operating See Note 3 6.1 V

NOTE 3. The BIAS regulator is designed to provide a quiet bias supply for TPS56300 controller. External loads should not be driven by the BIAS

Regulator.

deadtime circuit

PARAMETER CONDITIONS MIN TYP MAX UNITS

LOSENSE/LOHIB high level input voltage V

HISENSE

=2.55 V – 5.5 V , See Note 2 2.4 V

LOSENSE/LOHIB low level input voltage V

HISENSE

=2.55 V – 5.5 V , See Note 2 1.33 V

LOWDR high level input voltage V

HISENSE

=2.55 V–5.5 V , See Note 2 3 V

LOWDR low level input voltage V

HISENSE

=2.55 V–5.5 V , See Note 2 1.7 V

Driver nonoverlap time C

lowdr

= 9 nF, 10% threshold on LOWDR, VDRV=5 V 40 170 ns

NOTE 2. Ensured by design, not production tested.