Texas Instruments TPS56100PWPR, TPS56100PWP, TPS56100EVM-133, TPS56100EVM-128 Datasheet
TPS56100
HIGH-EFFICIENCY DSP POWER SUPPLY CONTROLLER
FOR 5-V INPUT SYSTEMS
SLVS201A – JUNE 1999 – REVISED JULY 1999
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Single-Channel, 5-V Controller
D
Synchronous-Rectifier Drivers for Greater
Than 90% Efficiency
D
Useable for All Common DSP Supply
Voltages – Popular Output Voltage Options
Set With Program Pins
D
EVM Available
D
Ideal for Applications With Current Ranges
From 3 A to 30 A.
D
Hysteretic Control Technique Enables Fast
Transient Response — Ideal for ’C6000 or
Multiple ’C5000 Applications
D
Low Supply Current
– 3 mA in Operation
– 90 µA in Standby
D
Power Good Output
D
28-Pin TSSOP PowerP AD Package
description
The TPS56100 is a high-efficiency synchronous-buck regulator controller which provides an accurate
programmable supply voltage to low-voltage digital signal processors, such as the ‘C6x and ‘C54x DSPs. An
internal 5-bit DAC is used to program the reference voltage from 1.3 V to 2.6 V . Higher output voltages can be
implemented using an external input resistive divider. The TPS56100 uses a fast hysteretic control method that
provides a quick transient response. The propagation delay from the comparator input to the output driver is
application example
15
14
2122 17 1620
87 9
19 18
131211101
28
5 643
27 26 25 24 23
2
TPS56100
+
IOUTNCOCP
VHYST
VREFB
VSENSE
ANAGND
SLOWST
BIAS
LODRV
LOHIB
DRVGND
LOWDR
DRV
PWRGD
VP0
VP1
VP2
VP3
VP4
INHIBIT
IOUTLO
LOSENSE
HISENSE
BOOTLO
HIGHDR
BOOT
V
CC
DSP
CV
DD
GND
5 V
1.5 V
GND
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
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9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
IOUT
NC
OCP
VHYST
VREFB
VSENSE
ANAGND
SLOWST
BIAS
LODRV
LOHIB
DRVGND
LOWDR
DRV
PWRGD
VP0
VP1
VP2
VP3
VP4
INHIBIT
IOUTLO
LOSENSE
HISENSE
BOOTLO
HIGHDR
BOOT
V
CC
PWP PACKAGE
(TOP VIEW)
NC – Not Connected
PowerPAD is a trademark of Texas Instruments Incorporated.
TPS56100
HIGH-EFFICIENCY DSP POWER SUPPLY CONTROLLER
FOR 5-V INPUT SYSTEMS
SLVS201A – JUNE 1999 – REVISED JULY 1999
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
less than 300 ns, even at maximum output current. Overcurrent shutdown and crossover protection combine
to eliminate destructive faults in the output MOSFETs, thereby protecting the processor during operation. The
slowstart current source is proportional to the reference voltage, thereby eliminating variation of the slowstart
timing when changes are made to the output voltage. When the output drops to less than 93% of the nominal
output voltage, PWRGD will pull the open-drain output low. The overvoltage circuit will disable the output drivers
if the output voltage rises more than 15% above the nominal output voltage. The TPS56100 also includes an
inhibit input to control power sequencing and undervoltage lockout thereby insuring the 5-V supply is within
limits before the controller starts. The 2-A MOSFET drivers can power multiple MOSFETs in parallel to drive
single or multiple DSPs and load currents up to 30 A. The high-side driver can be configured as a
ground-referenced driver or as a floating bootstrap driver with the included internal bootstrap Schottky diode.
The TPS56100 is available in a 28-pin TSSOP PowerPAD package, which increases thermal efficiency and
eliminates bulky heat sinks.
AVAILABLE OPTIONS
PACKAGES
T
J
TSSOP
†
(PWP)
EVM
0°C to 125°C TPS561000PWP TPS56100EVM–128
†
The PWP package is also available taped and reel. T o order, add an R
to the end of the part number (e.g., TPS561000PWPR).
TPS56100
HIGH-EFFICIENCY DSP POWER SUPPLY CONTROLLER
FOR 5-V INPUT SYSTEMS
SLVS201A – JUNE 1999 – REVISED JULY 1999
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
• 3
11111
Decode
VP0
VP1
VP2
VP3
VP4
SQ
R
Deglitch
Deglitch
100 mV
+
V
OVP
1.15 V
ref
V
PGD
0.93 V
ref
Rising
Edge
Delay
–
+
+
–
–
+
–
+
Hysteresis
Setting
–+
VP
MUX
and
Decoder
2x
SLOWST
OCP
INHIBIT
Bandgap Shutdown
I
VREFB
5
Shutdown
VSENSE
HIGHIN
HIGHDR
Analog
Bias
Analog Bias
Slowstart
Comp
Hysteresis
Comp
CM Filters
VREF
28 20 21 1915 7
V
CC
ANAGND PWRGD LOSENSE IOUTLO HISENSE
2 V
3.6 V
V
CC
UVLO
NOCPU
Fault
Shutdown
IOUT
BIAS
DRV
BOOT
HIGHDR
BOOTLO
LOWDR
DRVGND
1
9
14
16
17
18
13
12
6
11 104523
VP0 VP1 VP2 VP3 VP4
24252627
VREFB VHYST VSENSE LOHIB LODRV
8
3
22
I
VREFB
200 kΩ
200 kΩ
functional block diagram
TPS56100
HIGH-EFFICIENCY DSP POWER SUPPLY CONTROLLER
FOR 5-V INPUT SYSTEMS
SLVS201A – JUNE 1999 – REVISED JULY 1999
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NAME NO.
I/O
DESCRIPTION
ANAGND 7 I Analog ground
BIAS 9 I Analog BIAS pin. This terminal must be connected to 5-V supply voltage. A 1-µF ceramic capacitor should be
connected from BIAS to ANAGND.
BOOT 16 I Bootstrap. Connect a 1-µF low-ESR capacitor from BOOT to BOOTLO.
BOOTLO 18 I Bootstrap low. Connect BOOTLO to the junction of the high-side and low-side FETs for floating drive
configuration. Connect BOOTLO to PGND for ground reference drive configuration.
DRV 14 I Drive bias for the FET drivers. This terminal must be connected to 5-V supply voltage. A 1-µF ceramic capacitor
should be connected from DRV to DRVGND.
DRVGND 12 I Drive ground. Ground for FET drivers. Connect to FET PWRGND.
HIGHDR 17 O High drive. Output drive to high-side power switching FETs
HISENSE 19 I High current sense. For current sensing across high-side FETs, connect to the drain of the high-side FETs; for
optional resistor sensing scheme, connect to power supply side of current-sense resistor placed in series with
high-side FET drain.
INHIBIT 22 I Disables the drive signals to the MOSFET drivers.
IOUT 1 O Current out. Output voltage on this pin is proportional to the load current as measured across the Rds(on) of the
high-side FET s. The voltage on this pin equals 2×R
ds(on)×IOUT . In applications where very accurate current
sensing is required, a sense resistor should be connected between the input supply and the drain of the high-side
FET s.
IOUTLO 21 O Current sense low output. This is the voltage on the LOSENSE pin when the high-side FET s are on. A ceramic
capacitor should be connected from IOUTLO to HISENSE to hold the sensed voltage while the high-side FET s
are off. Capacitance range should be between 0.033 µF and 0.1 µF.
LODRV 10 I Low drive enable. Normally tied to 5 V. To activate the low-side FETs as a crowbar, pull LODRV low.
LOHIB 11 I Low side inhibit. Connect to the junction of the high and low side FETs to control the anti-cross-conduction and
eliminate shoot-through current. Disabled when configured in crowbar mode.
LOSENSE 20 I Low current sense. For current sensing across high-side FET s, connect to the source of the high-side FETs; for
optional resistor sensing scheme, connect to high-side FET drain side of current-sense resistor placed in series
with high-side FET drain.
LOWDR 13 O Low drive. Output drive to synchronous rectifier FETs
NC 2 Not connected
OCP 3 I Over current protection. Current limit trip point is set with a resistor divider between IOUT and ANAGND.
PWRGD 28 O Power good. Power Good signal goes high when output voltage is within 7% of voltage set by VID pins.
Open-drain output.
SLOWST 8 O Slow Start (soft start). A capacitor from SLOWST to ANAGND sets the slowstart time.
Slowstart current = I
VREFB
/5
V
CC
15 I 5-V supply. A 1-µF ceramic capacitor should be connected from VCC to DRVGND.
VHYST 4 I HYSTERESIS set pin. The hysteresis is set with a resistor divider from V
REFB
to ANAGND.
The hysteresis window = 2 × (V
REFB
– V
HYST
)
VP0 27 I Voltage programming input 0
VP1 26 I Voltage programming input 1
VP2 25 I Voltage programming input 2
VP3 24 I Voltage programming input 3
VP4 23 I Voltage programming input 4. Digital inputs that set the output voltage of the converter. The code pattern for
setting the output voltage is located in Table 1. Internally pulled up to 5 V.
VREFB 5 O Buffered reference voltage from VP network
VSENSE 6 I Voltage sense Input. To be connected to converter output voltage bus to sense and control output voltage. It is
recommended that an RC low pass filter be connected at this pin to filter noise.
TPS56100
HIGH-EFFICIENCY DSP POWER SUPPLY CONTROLLER
FOR 5-V INPUT SYSTEMS
SLVS201A – JUNE 1999 – REVISED JULY 1999
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
detailed description
V
REF
The reference/voltage programming (VP) section consists of a temperature-compensated bandgap reference
and a 5-bit voltage selection network. The 5 VP terminals are inputs to the VP selection network and are
TTL-compatible inputs internally pulled up to 5 V . The VP codes conform to the Intel
VRM 8.3 DC-DC Converter
Specification
for voltage settings between 1.8 V and 2.6 V, and they are decremented by 50 mV, down to 1.3
V , for the lower VP settings. V oltages higher than V
REF
can be implemented using an external resistive divider.
Refer to Table 1 for the VP code settings. The output voltage of the VP network, V
REF
, is within ±1.5% of the
nominal setting over the VP range of 1.3 V to 2.6 V, including a junction temperature range of 0°C to +125°C.
The output of the reference/VP network is indirectly brought out through a buffer to the V
REFB
pin. The voltage
on this pin will be within 2% of V
REF
. It is not recommended to drive loads with V
REFB
, other than setting the
hysteresis of the hysteretic comparator, because the current drawn from V
REFB
sets the charging current for
the slowstart capacitor. Refer to the slowstart section for additional information.
hysteretic comparator
The hysteretic comparator regulates the output voltage of the synchronous-buck converter. The hysteresis is
set by 2 external resistors and is centered about V
REF
. The 2 external resistors form a resistor divider from V
REFB
to ANAGND, with the output voltage connecting to the V
HYST
pin. The hysteresis of the comparator will be equal
to twice the voltage
difference
between the V
REFB
and V
HYST
pins. The propagation delay from the comparator
inputs to the driver outputs is 300 ns (maximum). The maximum hysteresis setting is 60 mV.
low-side driver
The low-side driver is designed to drive low-Rds(on) n-channel MOSFETs. The current rating of the driver is
2 A, source and sink. The bias to the low-side driver is derived from DRV.
high-side driver
The high-side driver is designed to drive low-Rds(on) n-channel MOSFETs. The current rating of the driver is
2 A, source and sink. The high-side driver can be configured either as a ground-referenced driver or as a floating
bootstrap driver. When configured as a floating driver , the bias voltage to the driver is developed from DRV . The
internal bootstrap diode connected between the DRV and BOOT pins is a Schottky for improved drive efficiency .
The maximum voltage that can be applied between BOOT and DRVGND is 30 V . The driver can be referenced
to ground by connecting BOOTLO to DRVGND, and connecting BOOT to a voltage supply.
deadtime control
Deadtime control prevents shoot-through current from flowing through the main power FETs during switching
transitions by actively controlling the turnon times of the MOSFET drivers. The high-side driver is not allowed
to turn on until the gate-drive voltage to the low-side FET s is below 2 V ; the low-side driver is not allowed to turn
on until the voltage at the junction of the high-side and low-side FETs (Vphase) is below 2 V.
current sensing
Current sensing is achieved by sampling and holding the voltage across the high-side power FETs while the
high-side FET s are on. The sampling network consists of an internal 85-Ω switch and an external ceramic hold
capacitor. Recommended value of the hold capacitor is between 0.033 µF and 0.1 µF. Internal logic controls
the turnon and turnoff of the sample/hold switch such that the switch does not turn on until the Vphase voltage
transitions high, and the switch turns off when the input to the high-side driver goes low . The sampling will occur
only when the high-side FETs are conducting current. The voltage on the IOUT pin equals 2 times the sensed
high-side voltage. In applications where a higher accuracy in current sensing is required, a sense resistor can
be placed in series with the high-side FETs, and the voltage across the sense resistor can be sampled by the
current sensing circuit.
TPS56100
HIGH-EFFICIENCY DSP POWER SUPPLY CONTROLLER
FOR 5-V INPUT SYSTEMS
SLVS201A – JUNE 1999 – REVISED JULY 1999
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
detailed description (continued)
inhibit
INHIBIT is a TTL-compatible digital input used to enable the controller. When INHIBIT is low , the output drivers
are low and the slowstart capacitor is discharged. When INHIBIT goes high, the short across the slowstart
capacitor is released and normal converter operation begins. The 5-V supply must be above UVLO thresholds
before the controller is allowed to start up. The inhibit start threshold is 2.1 V and the hysteresis is 100 mV for
the INHIBIT comparator.
VCC undervoltage lockout (UVLO)
The undervoltage lockout circuit disables the controller while the VCC supply is below the 4-V start threshold
during power up. When the controller is disabled, the output drivers will be low and the slowstart capacitor is
discharged. When VCC exceeds the start threshold, the short across the slowstart capacitor is released and
normal converter operation begins. There is a 0.5-V hysteresis in the undervoltage lockout circuit for noise
immunity.
slowstart
The slowstart circuit controls the rate at which VO powers up. A capacitor is connected between SLOWST and
ANAGND and is charged by an internal current source. The current source is proportional to the reference
voltage, so that the charging rate of C
SLOWST
is proportional to the reference voltage. By making the charging
current proportional to V
REF
, the power-up time for VO will be independent of V
REF
. Thus, C
SLOWST
can remain
the same value for all VP settings. The slowstart charging current is determined by the following equation:
I
slowstart
= I(V
REFB
) / 5 (amps)
Where I(V
REFB
) is the current flowing out of V
REFB
.
It is recommended that no additional loads be connected to V
REFB
, other than the resistor divider for setting the
hysteresis voltage. The maximum current that can be sourced by the V
REFB
circuit is 500 µA. The equation for
setting the slowstart time is:
t
SLOWST
= 5 × C
SLOWST
× R
VREFB
(seconds)
Where R
VREFB
is the total external resistance from V
REFB
to ANAGND.
power good
The power-good circuit monitors for an undervoltage condition on V
O
. If VO is 7% below V
REF
, then the PWRGD
pin is pulled low. PWRGD is an open-drain output.
overvoltage protection
The overvoltage protection (OVP) circuit monitors VO for an overvoltage condition. If VO is 15% above V
REF
,
then a fault latch is set and both output drivers are turned off. The latch will remain set until VCC goes below the
undervoltage lockout value or INHIBIT is low. A 3-µs deglitch timer is included for noise immunity. Refer to the
LODRV section for information on how to protect the microprocessor against overvoltages due to a shorted
high-side power FET.
TPS56100
HIGH-EFFICIENCY DSP POWER SUPPLY CONTROLLER
FOR 5-V INPUT SYSTEMS
SLVS201A – JUNE 1999 – REVISED JULY 1999
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
detailed description (continued)
overcurrent protection
The overcurrent protection (OCP) circuit monitors the current through the high-side FET. The overcurrent
threshold is adjustable with an external resistor divider between IOUT and ANAGND, with the divider voltage
connected to the OCP pin. If the voltage on OCP exceeds 100 mV , then a fault latch is set and the output drivers
are turned off. The latch will remain set until V
CC
goes below the undervoltage lockout value and back up above
3.6 V or INHIBIT is similarly brought below its stop threshold and back above its start threshold. A 3-µs deglitch
timer is included for noise immunity . The OCP circuit is also designed to protect the high-side power FET against
a short-to-ground fault on the terminal common to both power FETs.
LODRV
The LODRV circuit is designed to protect the microprocessor against overvoltages that can occur if the high-side
power FETs become shorted. External components sensing an overvoltage condition are required to use this
feature. When an overvoltage fault occurs, the low-side FET s are used as a crowbar . LODR V is pulled low and
the low-side FET will be turned on, overriding all control signals inside the TPS5210 controller. The crowbar
action will short the input supply to ground through the faulted high-side FETs and the low-side FETs. A fuse
in series with V
in
should be added to disconnect the short circuit.
T able 1. Voltage Programming Codes
VP TERMINALS
(0 = GND, 1 = floating or pull-up to 5 V)
V
REF
VP4 VP3 VP2 VP1 VP0 (Vdc)
0 1 1 1 1 1.30
0 1 1 1 0 1.35
0 1 1 0 1 1.40
0 1 1 0 0 1.45
0 1 0 1 1 1.50
0 1 0 1 0 1.55
0 1 0 0 1 1.60
0 1 0 0 0 1.65
0 0 1 1 1 1.70
0 0 1 1 0 1.75
0 0 1 0 1 1.80
0 0 1 0 0 1.85
0 0 0 1 1 1.90
0 0 0 1 0 1.95
0 0 0 0 1 2.00
0 0 0 0 0 2.05
1 1 1 1 1 No CPU
1 1 1 1 0 2.10
1 1 1 0 1 2.20
1 1 1 0 0 2.30
1 1 0 1 1 2.40
1 1 0 1 0 2.50
1 1 0 0 1 2.60
TPS56100
HIGH-EFFICIENCY DSP POWER SUPPLY CONTROLLER
FOR 5-V INPUT SYSTEMS
SLVS201A – JUNE 1999 – REVISED JULY 1999
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Table 1. Voltage Programming Codes (Continued)
VP TERMINALS
(0 = GND, 1 = floating or pull-up to 5 V)
V
REF
VP4 VP3 VP2 VP1 VP0 (Vdc)
1 1 0 0 0 2.60
1 0 1 1 1 2.60
1 0 1 1 0 2.60
1 0 1 0 1 2.60
1 0 1 0 0 2.60
1 0 0 1 1 2.60
1 0 0 1 0 2.60
1 0 0 0 1 2.60
1 0 0 0 0 2.60
absolute maximum ratings over operating virtual junction temperature (unless otherwise noted)
†
Supply voltage range, V
CC
(see Note1), BIAS, DRV –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range: BOOT to DRVGND (High-side Driver ON) –0.3 V to 30 V. . . . . . . . . . . . . . . . . . . . . . . . .
BOOT to HIGHDRV –0.3 V to 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BOOT to BOOTLO –0.3 V to 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
INHIBIT, VPx, LODRV –0.3 V to 7.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWRGD, OCP –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LOHIB, LOSENSE, IOUTLO, HISENSE –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . .
VSENSE –0.3 V to 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage difference between ANAGND and DRVGND ±0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current, V
REFB
0.5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature range, TJ 0°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Unless otherwise specified, all voltages are with respect to ANAGND.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
PWP 1150 mW 11.5 mW/°C 630 mW 460 mW
TPS56100
HIGH-EFFICIENCY DSP POWER SUPPLY CONTROLLER
FOR 5-V INPUT SYSTEMS
SLVS201A – JUNE 1999 – REVISED JULY 1999
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions
MIN MAX UNIT
Supply voltage, V
CC
4.5 6 V
Input voltage, BOOT to DRVGND 0 28 V
Input voltage, BOOT to BOOTLO 0 13 V
Input voltage, INHIBIT, VPx, LODRV, PWRGD, OCP 0 6 V
Input voltage, LOHIB, LOSENSE, IOUTLO, HISENSE, BIAS, DRV 0 6 V
Input voltage, VSENSE 0 4.5 V
Voltage dif ference between ANAGND and DRVGND 0 ±0.2 V
Output current, V
REFB
†
0 0.4 mA
†
Not recommended to load V
REFB
other than to set hystersis since I
VREFB
sets slowstart time.
electrical characteristics over recommended operating virtual junction temperature range,
V
CC
= 5 V (unless otherwise noted)
reference/voltage programming
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
REF
Cumulative voltage reference
accuracy
VCC = 4.5 to 5.5 V, 1.3 V ≤ V
REF
≤ 2.6 V,
See Note 2
–1.5% 1.5%
VPx High-level input voltage 2.25 V
VPx Low-level input voltage 1 V
Output voltage I
VREFB
= 50 µA V
REF
–10 mV V
REFVREF
+10 mV V
V
REFB
Output regulation 10 µA ≤ IO ≤ 500 µA 2 mV
VPx Input pullup resistance 190 kΩ
NOTES: 2. Cumulative reference accuracy is the combined accuracy of the reference voltage and the input offset voltage of the hysteretic
comparator. Cumulative accuracy equals the average of the high-level and low-level thresholds of the hysteretic comparator.
3. This parameter is ensured by design and is not production tested.
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