TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217 – JUNE 1999
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Independent Dual Channels
D
Hysteretic Control for Fast Transient
Response
D
4.5-V to 25-V Input Voltage Range
D
Adjustable Output Voltage Down to 1.2 V
D
Synchronous Rectifier Enables Efficiencies
of >95%
D
Minimized External Component Count
D
Separate Standby Control and Over Current
Protection
D
Low Supply Current...0.8 mA Typ
D
30-Pin TSSOP
D
Low Standby Current (1-µA maximum)
D
EVM Available (TPS5602EVM-121)
description
The TPS5602 is a dual-channel synchronous
buck switch-mode power supply controller
featuring very fast feedback control and minimized component count. By using the hysteretic control method,
it is ideal for high-transient current applications, such as ’C6000 and multiple ’C54x DSPs. The TPS5602 is
designed specifically for DSP applications that require high efficiency. Since both channels are independent,
the up and down power sequencing can be easily achieved by properly setting the standby pins. The wide input
voltage and adjustable output voltage make the TPS5602 suitable for many applications.
typical design
R4
R1
+
C3
R3
R2
D1
C2
C1
GND
5 V
C7
L1
C4
R5
R6
OUT2
C8
L2
C5
OUT1
1.8 V
3.3 V
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
INV1
NC
SOFTSTAR T1
NC
C
T
NC
GND
REF
STBY1
STBY2
V
CC
COMP
SOFTSTAR T2
NC
INV2
LH1
OUT1_u
LL1
OUT1_d
OUTGND1
TRIP1
V
CC
SENSE
TRIP2
Vref5
REG5V_IN
OUTGND2
OUT2_d
LL2
OUT2_u
LH2
DBT PACKAGE
(TOP VIEW)
NC – No internal connection
TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217 – JUNE 1999
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
AVAILABLE OPTIONS
PACKAGE
T
A
TSSOP
(DBT)
EVM
°
°
TPS5602IDBT
–
40°C to 85°C
TPS5602IDBTR
TPS5602EVM-121
functional block diagram
4.5 V
OUTGND2
Comp
Hysteretic Comp.
Current Comp.
VREF5
Current Comp.
LH1
LL1
OUT1_d
OUT1_u
OUTGND1
TRIP1
TRIP2
OUT2_d
LL2
Out2_u
LH2
VccSENSE
REG5Vin
SFT1
SOFT START2
INV1
INV2
Vref
Vcc
STBY1
STBY2
UVLO
GND
SOFT START1
1.1 V
REF
OSC
1.185 V
1.185 V
Current
Protection
Trigger
SFT2
Setup trigger
Setup trigger
Trigger on
OSC on
Fixed off–time reset
1.185 V
DLY
3.8 V
Hysteretic Comp. DLY
DLY
DLY
C
T
TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217 – JUNE 1999
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NAME NO.
I/O
DESCRIPTION
COMP 12 I/O Voltage monitor comparator input
C
T
5 I/O The oscillator frequency external capacitor connection
GND 7 Control GND
INV1 1 I CH1 hysteretic comparator inverting input
INV2 15 I CH2 hysteretic comparator inverting input
LH1 30 I/O CH2 high-side gate drive boost capacitor input
LH2 16 I/O CH1 high-side gate drive boost capacitor input
LL1 28 I/O CH1 high-side drive and current protection
LL2 18 I/O CH2 high-side drive and current protection
NC 2, 4, 6, 14
OUT1_d 27 I/O CH1 low-side gate drive output
OUT2_d 19 O CH2 low-side gate drive output
OUT1_u 29 O CH1 high-side switch output
OUT2_u 17 O CH2 high-side switch output
OUTGND1 26 Output GND 1
OUTGND2 20 Output GND 2
REF 8 O 1.185-V reference voltage output
REG5V_IN 21 I External 5-V input
SOFTSTAR T1 3 I/O CH1 soft start control external capacitor connection
SOFTSTAR T2 13 I/O CH2 soft start control external capacitor connection
STBY1 9 I CH1 standby control
STBY2 10 I CH2 standby control
TRIP1 25 I CH1 output current control input
TRIP2 23 I CH2 output current control input
V
CC
11 I Supply voltage input
Vref5 22 O 5-V internal regulator output
VCCSENSE 24 I Supply voltage sense input
detailed description
vref (1.185 V)
The reference voltage is used for the output voltage setting and the voltage protection (COMP).
vref (5 V)
An internal linear voltage regulator offers a fixed 5-V voltage as the bootstrap voltage so that the design for the
bootstrap is much easier. The tolerance is 6%. The extra current capability can also be used to power external
circuitry .
5-V switch
If the internal 5-V switch senses a 5-V input from REG5V pin, the internal 5-V linear regulator will be
disconnected from the MOSFET drivers. The external 5-V will be used for the low-side driver and the high-side
bootstrap, thus increasing the efficiency.
TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217 – JUNE 1999
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
detailed description (continued)
hysteretic comparator
Each channel has a hysteretic comparator to regulate the output voltage of the synchronous-buck converter.
The hysteresis is set internally and is typically 8.5 mV. The total delay from the comparator input to the driver
output is typically 500 ns from low to high and 350 ns from high to low.
low-side driver
The low-side driver is designed to driver low-Rds(on) n-channel MOSFET s. The maximum drive voltage is 5V
from Vref5. The current rating of the driver is typically 1 A, source and sink.
high-side driver
The high side driver is designed to drive low-Rds(on) n-channel MOSFETs. The current rating of the driver is
1 A, source and sink. When configured as a floating driver, the bias voltage to the driver is developed from the
Vref5, limiting the maximum drive voltage between OUTxU and LLx to 5 V. The maximum voltage that can be
applied between LHx and OUTGNDx is 30 V.
deadtime control
Deadtime control prevents shoot-through current from flowing through the main power FETs during switching
transitions by actively controlling the turnon time of the MOSFETs drivers. The typical deadtime from
low-side-driver-off to high-side-driver-on is 75 ns and 164 ns from high-side-driver-off to low-side-driver-on.
current protection
The current protection is achieved by sensing the high-side power MOSFET drain-to-source voltage drop during
on-time through V
CC
Sense and LLx pins. An external resistor between Vin and TRIPx pin with the internal
current source connected to the current comparator negative input adjusts the current limit. The typical internal
current source current is 15 µA. When the voltage on the positive pin is lower than the negative pin, the current
comparator turns on the trigger, and then activates the oscillator. This oscillator repeatedly resets the trigger
until the overcurrent condition is removed. The equation for the external resistor selection is:
Rclmt
+
Rds(on
) (
Itrip)Iind(p-p
)ń2)
0.000015
Where Rds(on) is the MOSFET turnon resistance; Itrip is the required trip current; Iind(p-p) is the peak-to-peak
inductor ripple current. Itrip must be greater than 0.5×Iind(p-p). The tolerance is ±30%.
COMP
COMP is an internal comparator used for any voltage protection such as the output under-voltage protection
for DSP power applications. If the core voltage is lower than the setpoint, the comparator turns off both channels
to prevent the DSP from damage.
SOFT1, SOFT2
Separate soft-start terminals make it possible to set the sequencing of each output for any possibility. The
capacitor value for a start-up time can be calculated by the following equation:
C = 2 × T (µF)
Where C is the external capacitor value, T is the required start-up time in (ms).
STBY1, STBY2
Both channels can be switched into standby mode separately by grounding the STBY pin. The standby current
is less than 1 µA. The STBY pins can be used for sequencing.
UVLO
When the input voltage rises to about 3.8 V , the IC is turned on, ready to function. When the input voltage falls
below the turnon value, the IC is turned off. The typical hysteresis is 149 mV.
TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217 – JUNE 1999
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature (see Note 1) (unless otherwise
noted)
†
Supply voltage, V
CC
–0.3 V to 27 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, V
I
, INV –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Softstart –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COMP –0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
REG5V_IN –0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
STBY –0.3 V to 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TRIP –0.3 V to 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Driver current 3 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage, LLx –0.3 V to 27 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage, OUTx_u –0.3 V to 32 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage, OUTx_d –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power dissipation (T
A
= 25°C) See Dissipation Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
–40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature range, T
J
125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages are with respect to GND terminal.
DISSIPATION RATING TABLE
PACKAGE
TA = 25°C
POWER DISSIPATION
TA ≥ 25°C
DERATING FACTOR
TA = 85°C
POWER DISSIPATION
DBT 874 mW 6.993 mW/°C 454 mW
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, V
CC
4.5 25 V
INV1/2 6
COMP 6
SOFTSTART1/2 6
Input voltage, V
I
REG5V_IN 5.5
V
STBY1/STBY2 12
TRIP1/2
V
CC_SENCE
25
Operation junction temperature range, T
A
–40 85 °C
electrical characteristics over recommended TA = –40°C to 85°C temperature range, VCC = 7 V
(unless otherwise noted)
reference voltage
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TA = 25°C, I
vref
= 50 µA 1.167 1.185 1.203
V
ref
Reference voltage
VI = 4.5 V to 25 V, I = 1 µA to 1 mA 1.155 1.215
V
VI
(Regin)
Line regulation VCC = 5.5 V to 25 V, I = 50 µA 0.2 12 mV
VI
(Regl)
Load regulation I = 1 µA to 1 mA, 0.5 10 mV
TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217 – JUNE 1999
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
quiescent current
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I
CC
Operating current without switching Both STBY >2.5 V ,
VI = 4.5 V to 25 V
No switching 0.8 1.5 mA
I
(CCS)
Stand-by current Both STBY <0.5 V , VI = 4.5 V to 25 V 1 1000 nA
hysteretic comparator
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
hys
†
Hysteresis window 5.5 8.5 11.5 mV
V
H(off)
Offset voltage 2 mV
I
H(bias)
Bias current 10 pA
t
(HLT)
, t
(LHT)
TTL input signal 230
t
(LH)
Propagation delay from INV to OUTxU
‡
500 650
ns
t
(HI)
10 mV overdrive on hysteretic band signal
350 500
†
V
hys
is assured by design.
‡
The delay time in the table includes the driver.
driver deadtime
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
(DRVLH)
Low side to high side 90
t
(DRVHL)
High side to low side 160
ns
standby
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I
H
High-level input voltage
2.5 V
I
L
Low-level input voltage
STBY1, STBY2
0.5 V
Tturn-on
p
p
7.2
Tturn-off
Pro agation delay
Staby to driver out ut
4.8
µs
5 V regulator
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
O
Output voltage I = 10 mA 4.7 5.3 V
V
I(Regin)
VCC = 5.5 V to 25 V, I = 10 mA 20
V
I(Regl)
Load regulation
I = 1 mA to 10 mA, VCC = 5.5 V 40
mV
I
OS
Short-circuit output current Vref = 0 V 80 mA
TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217 – JUNE 1999
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended free-air temperature range, VCC = 7 V (unless
otherwise noted) (continued)
5-V internal switch
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
TLH
4.2 4.9
V
THL
Threshold voltage
4.1 4.7
V
Rson On-time resistance 2.5 8 Ω
V
hys
Hysteresis 50 250 mV
current limit
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Internal current source 10 15 20 µA
Input offset voltage 2.5 mV
UVLO
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
(TLH)
3.6 4.2
V
(THL)
Threshold voltage
3.5 4.1
V
Hysteresis 50 250 mV
driver output
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OUT_u sink current VO = 3 V 0.5 1.2
OUT_u source current VO = 2 V –1 –1.7
A
OUT_d sink current VO = 3 V 0.5 1.2
OUT_d source current VO = 2 V –1 –1.7
A
High side driver is GND referenced,
p
CL = 2200 pF 25.6
Rise time
In ut: INV
= 0 V – 3 V,
tr/tf = 10 ns, Frequency = 200 kHz,
CL = 3300 pF 30.8
ns
High side driver is GND referenced,
p
CL = 2200 pF 23.2
Fall time
In ut: INV
= 0 V – 3 V,
tr/tf = 10 ns, Frequency = 200 kHz,
CL = 3300 pF 25.2
ns
Softstart
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I
(CTRL)
Softstart current 1.8 2.5 3 µA
Maximum discharge current 0.92 mA
COMP
†
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Threshold voltage 1 1.1 1.25 V
Turn on
Propagation delay 50% duty cycle,
452
Turn off
gyyy,
No capacitor on COMP or OUT_u pin,
Frequency
=
200 kHz
384
ns
†
The delay time in the table includes the drivers.
oscillator
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Frequency without Ct 202.4 kHz
Frequency with Ct Ct = 100 pF 67.5 kHz
TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217 – JUNE 1999
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 1
600
650
700
750
800
850
900
950
4.5 7.0 25.0
VCC – Supply Voltage – V
TJ = 125°C
– Quiescent Current –
QUIESCENT CURRENT (BOTH CHANNELS ON)
vs
SUPPLY VOLTAGE
Aµ
I
(qon)
TJ = 25°C
TJ = –40°C
Figure 2
0.0
20.0
40.0
60.0
80.0
100.0
120.0
140.0
160.0
4.5 7.0 10.0 15.0 20.0 25.0
– Quiescent Current – nA
QUIESCENT CURRENT (BOTH CHANNEL STANDBY)
vs
SUPPLY VOLTAGE
I
(off)
TJ = 125°C
TJ = 25°C
TJ = –40°C
VCC – Supply Voltage – V
Figure 3
0
1
2
3
4
5
6
0.1 0.5 1
I
(src)
– Driver Source Current – A
– Driver Output Voltage – V
DRIVE OUTPUT VOLTAGE
vs
DRIVE CURRENT (SOURCE)
V
(src)
TJ = 125°C
TJ = 25°C
TJ = –40°C
Figure 4
0
0.5
1
1.5
2
2.5
3
3.5
0.1 0.5 1
I
(sink)
– Driver Sink Current – A
– Driver Output Voltage – V
DRIVE VOLTAGE
vs
DRIVE CURRENT (SINK)
V
(snk)
TJ = 125°C
TJ = 25°C
TJ = –40°C
TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217 – JUNE 1999
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 5
SOFTSTART CAPACITANCE
vs
SOFTSTART TIMING
0.001
0.01
0.1
1
110
100
T
(start)
– Softstart Timing – ms
– Softstart Capacitance – Fµ
C
(start)
Figure 6
12.6
12.8
13.0
13.2
13.4
13.6
13.8
14.0
4.5 7.0 10.0 15.0 20.0 25.0
V
CC(trip)
– Supply Voltage – V
CURRENT-PROTECTION SOURCE CURRENT
vs
SUPPLY VOLTAGE
Aµ
I
(trip)
– Current-Protection Source Current –
TJ = 125°C
TJ = 25°C
TJ = –40°C
Figure 7
0.0
0.5
1.0
1.5
2.0
2.5
–40 –20 0 25 50 70 95 125
STANDBY THRESHOLD VOLTAGE (H–L)
vs
JUNCTION TEMPERATURE
TJ – Junction Temperature – °C
– Standby Threshold Voltage – V
V
(stby)
Figure 8
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
–40 –20 0 25 50 70 95 125
UVOL Hysteresis V oltage – V
UVLO HYSTERESIS VOLTAGE
vs
JUNCTION TEMPERATURE
TJ – Junction Temperature – °C
TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217 – JUNE 1999
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 9
3.60
3.62
3.64
3.66
3.68
3.70
3.72
3.74
3.76
3.78
3.80
–40 –20 0 25 50 70 95 125
UVLO Threshold Voltage – V
UVLO THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
TJ – Junction Temperature – °C
Figure 10
0.0
0.5
1.0
1.5
2.0
2.5
–40 –20 0 25 50 70 95 125
– Threshold Voltage – V
STANDBY THRESHOLD (L–H)
vs
JUNCTION TEMPERATURE
TJ – Junction Temperature – °C
V
(stby)
Figure 11
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0.0
–40 –20 0 25 50 70 95 125
TJ – Junction Temperature – °C
Softstart Charge Current –
SOFT START CHARGE CURRENT
vs
JUNCTION TEMPERATURE
Aµ
Figure 12
4.5
4.6
4.7
4.8
4.9
5.0
5.1
0 –10 –20 –30 –40 –50
V
ref5
– Current – mA
VREF5 VOLTAGE
vs
VREF5 CURRENT
VREF5 – Voltage – V
TJ = 125°C
TJ = 25°C
TJ = –40°C
TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217 – JUNE 1999
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
• 11
OUT2D
SOFTSTART2
VREF5
INV1
Ct
GND
REF
STBY1
STBY2
COMP
INV2
VCC
LH2
OUT2U
LL2
OUTGND2
5Vin
TRIP2
VCCSENSE
TRIP1
OUTGND1
OUT1D
LL1
OUT1L
LH1
NC
SOFTSTART1
NC
NC
NC
R9
15
15R8
Open
Figure 13. EVM Schematic Diagram
APPLICATION INFORMATION
V
I
V
O
5–9 V
5 A
1.8 V
4 A
3.3 V
3 A
1.8 V
3.3 V
TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217 – JUNE 1999
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
application for DSP power
The design shown in this data sheet is a reference design for a DSP application. An evaluation module (EVM),
TPS5602EVM-121 (SLVP121), is available for customer testing and evaluation. The intent is to allow a
customer to fully evaluate the given design using the plug-in EVM supply shown here. The input voltage for this
EVM is from 4.5 V to 9 V . The outputs are 1.8 V at 4 A and 3.3 V at 3 A. By changing few components this EVM
can be used for different operating specifications such as high-input voltage.
This application provides the following power supply sequence: the core power goes up before the I/O supply ,
and if the core power is brought down by abnormal condition, the I/O power will be brought down with it.
T o help the customers to design the power supply using the TPS5602, key design procedures are shown below:
switching frequency
With hysteretic control, the switching frequency is a function of the input voltage, the output voltage, the
hysteresis window, the delay of the hysteresis comparator and the driver , the output inductance, the resistance
in the output inductor, the output capacitance, the ESR and ESL in the output capacitor , the output current, and
the turn on resistance of high side and low side MOSFET . It is a very complex equation if everything is included.
To make it more useful to the designers, a simplified equation only considers the most influential factors. The
tolerance of this equation is about 30%:
ƒ
s
+
Vout
(
Vin*Vout
)
ǒ
ESR
*ǒ10 10
*
7
)
Td
Ǔ
ń
Cout
Ǔ
Vin
ǒ
Vin ESR
ǒ10 10
–
7
)
Td
Ǔ
)
0.007
Lout*ESL Vin
Ǔ
Where ƒs is the switching frequency (Hz);
Vout
is the output voltage (V);
Vin
is the input voltage (V);
Cout
is the
output capacitance;
ESR
is the equivalent series resistance in the output capacitor (Ω);
ESL
is the equivalent
series inductance in the output capacitor (H);
Lout
is the output inductance (H); and Td is the output feedback
filter time constant (S).
Example: Vin = 5 V, Vout = 1.8 V, Cout = 680 µF: ESR = 40 mΩ; ESL = 3 nH; Lout = 6 µH; Td = 0.5 µs
Then, the frequency
fs = 122 kHz
.
output inductor ripple current
The output inductor current ripple can affect not only the efficiency and the inductor saturation, but also the
output capacitor selection. The equation is exhibited below:
Iripple
+
Vin*Vout*Iout
ǒ
Rdson)R
L
Ǔ
Lout
D
Ts
Where
Iripple
is the peak-to-peak ripple current through the inductor (A); Vin is the input voltage (V); V out is the
output voltage (V); Iout is the output current; Rdson is the on-time resistance of MOSFET (Ω); D is the duty cycle;
and Ts is the switching cycle (S). From the equation, it can be seen that the current ripple can be adjusted by
changing the output inductor value.
Example: Vin = 5 V, Vout = 1.8 V, Iout = 5 A: Rdson = 10 m Ω; RL = 5 mΩ; D = 0.36; Ts = 10 mS; Lout = 6 µH
Then, the ripple current Iripple = 2 A.
TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217 – JUNE 1999
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
application for DSP power (continued)
output capacitor RMS current
Assuming the inductor ripple current totally goes through the output capacitor to ground, the RMS current in the
output capacitor can be calculated as:
Io(rms
)
+
D
I
12
Ǹ
Where
Io(rms)
is the maximum RMS current in the output capacitor (A); ∆I is the peak–to–peak inductor ripple
current (A).
Example: ∆
I = 2 A
, so
Io(rms) = 0.58 A
input capacitor RMS current
Assuming the input ripple current totally goes into the input capacitor to the power ground, the RMS current in
the input capacitor can be calculated as:
Ii(rms
)
+Io
ǒ
D
(1
*
D
)
Ǹ
)(1
*
D
)
D
Ǹ
Ǔ
Where
Ii(rms)
is the input RMS current in the input capacitor (A); Io is the output current (A); D is the duty cycle.
From the equation, it can be seen that the highest input RMS current usually occurs at lowest input voltage.
Example:
Io = 5 A; D = 0.36
Then, Ii(rms) = 3.36 A
softstart
The softstart timing can be adjusted by selecting the softstart capacitor value. The equation is
C
soft
= 2 × T
soft
Where
C
soft
is the softstart capacitance (µF); T
soft
is the start-up time pin (S).
Example:
Tsoft = 5 ms
, so
Csoft = 0.01 µF
.
current protection
The current protection in TPS5602 is set using an internal current source and an external resistor to set up the
current limit. The sensed high side MOSFET drain-to-source voltage drop is compared to the set point; if the
voltage drop exceeds the limit, the internal oscillator is activated, and continuously resets the current limit until
the over-current condition is removed. The equation below should be used for calculating the external resistor
value for current protection:
Rclmt
+
Rds(on
) (
Itrip)Iind(p-p
)ń2)
0.000015
Where Rclmt is the external current limit resistor (R10, R1 1); Rds(on) is the high side MOSFET on resistance;
Itrip is the required current limit; lind(p-p) is the peak-to-peak output inductor current.
Example: Rds(on) =
10 mΩ, Itrip = 5 A, Lind = 2 A,
so
Rclmt = 4 k
Ω.
TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217 – JUNE 1999
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
application for DSP power (continued)
sequencing and under voltage protection
The EVM design uses the standby pins to implement power sequencing. There are two ways to achieve the
protection: one uses a voltage supervisory circuit such as the TI TPS3305-18, the other uses a low cost
comparator, such as the TI TLV1391. The standby pin for the second channel is pulled low by either the
supervisory circuit or the external protection comparator until the first channel output voltage is above the
start-up threshold voltage. With the protection hysteresis, during the power down, if the core voltage is lower
than, for example, 1.3 V, the 3.3 output will be pulled down together. During the normal operation, if the core
voltage is lost, the I/O voltage will be pulled down at the same time. This protection circuit prevents the DSPs
from any damage caused by the malfunctioning power supply. The equation displayed below uses the
comparator for the protection setpoint:
Assuming R16 is much larger than R17, and R19 is 10 kΩ, and the R13 value is adjusted for the turnon setpoint:
R
13
+
(
Von
*
1.2)
ǒ
R
16
øR19
Ǔ
1.2
Where
Von
is the required turn on setpoint. For the turn-off setpoint, R16 is adjusted,
R
16
+
R
13
R19 (1.2
*
Vin
)
R
19 (
Voff
*
1.2)*1.2
R13
By solving these equations together, or using a spreadsheet to iterate, the setpoints can be easily derived. The
two equations are used for the verification:
Von
+
1.2 (R13
)
ǒ
R
16
øR19
Ǔ
ǒ
R
16
øR19
Ǔ
and
Voff+R
13
ǒ
1.2
*
Vin
R
16
)
1.2
R
19
)
1.2
R
13
Ǔ
Where
Von
and
Voff
are the turnon and turnoff setpoints respectively
Example can be found by using the numbers in the bill of materials.
layout considerations
Good power supply results will only occur when care is given to proper design and layout. Layout will affect noise
pickup and generation and can cause a good design to perform with less than expected results. With a range
of currents from milliamps to tens or even hundreds of amps, good power supply layout is much more difficult
than most general PCB designs. The general design should proceed from the switching node to the output, then
back to the driver section and, finally, placing the low-level components. Below are several specific points to
consider
before
layout of a TPS5602 design begins.
D
All sensitive analog components should be referenced to ANAGND. These include components connected
to Vref5, Vref, INV, LH, and COMP.
D
Analog ground and drive ground should be isolated as much as possible. Ideally , analog ground will connect
to the ground side of the bulk storage capacitors on V
O
, and drive ground will connect to the main ground
plane close to the source of the low-side FET.
D
Connections from the drivers to the gate of the power FETs should be as short and wide as possible to
reduce stray inductance. This becomes more critical if external gate resistors are not being used.
D
The bypass capacitor for VCC should be placed close to the TPS5602.
TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217 – JUNE 1999
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
layout considerations (continued)
D
When configuring the high-side driver as a floating driver, the connection from LL to the power FETs should
be as short and as wide as possible.
D
When configuring the high-side driver as a floating driver, the bootstrap capacitor (connected from LH to
LL) should be placed close to the TPS5602.
D
When configuring the high-side driver as a ground-referenced driver, LL should be connected to DR VGND.
D
The bulk storage capacitors across VIN should be placed close to the power FET s. High-frequency bypass
capacitors should be placed in parallel with the bulk capacitors and connected close to the drain of the
high-side FET and to the source of the low-side FET.
D
High-frequency bypass capacitors should be placed across the bulk storage capacitors on VO.
D
LH and LL should be connected very close to the drain and source, respectively , of the high-side FET. LH
and LL should be routed very close to each other to minimize differential-mode noise coupling to these
traces. Ceramic decoupling capacitors should be placed close to where HISENSE connects to V
IN
, to
reduce high-frequency noise coupling on HISENSE.
D
The output voltage sensing trace should be isolated from the switching node and/or inductor pulses by the
use of a ground trace or plane.
test results
The tests are conducted at TA = 25°C, the input voltage is 5 V (if not specifically noted).
Figure 14
3.3-V OUTPUT EFFICIENCY
76
78
80
82
84
86
88
90
92
94
96
98
0.1 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
IO – Output Current – A
Efficiency – %
Figure 15
1.8-V OUTPUT EFFICIENCY
60
65
70
75
80
85
90
95
0.1 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
IO – Output Current – A
Efficiency – %
TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217 – JUNE 1999
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Figure 16
COMBINED SYSTEM EFFICIENCY
86
87
88
89
90
91
92
93
94
10 20 30 40 50 60 70 80 90 100
Percentage of Output Current on Both Channels – %
I(1.8) = 4 A
I(3.3) = 3 A
Efficiency
%
Figure 17
3.3-V OUTPUT LOAD REGULATION
3.3
3.305
3.31
3.315
3.32
0 0.1 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
IO – Output Current – A
– Output Voltage – VV
O
Figure 18
1.8-V OUTPUT LOAD REGULATION
1.78
1.785
1.79
1.795
1.8
0 0.1 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
IO – Output Current – A
– Output Voltage – VV
O
Figure 19
3.3-V LINE REGULATION
3.29
3.3
3.31
3.32
3.33
3.34
3.35
4.55 7 91113151719212325
VI – Input Voltage – V
– Output Voltage – VV
O
TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217 – JUNE 1999
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Figure 20
1.8-V OUTPUT LINE REGULATION
1.775
1.78
1.785
1.79
1.795
1.8
1.805
4.5 5 7 9 11 13 15 17 19 21 23 25
VI – Input Voltage – V
– Output Voltage – VV
O
Figure 21
50 mV/div
∆V = 48 mV
VI = 5 V
5 µs/div
OUTPUT VOLTAGE RIPPLE
Figure 22
3.3 V
200 ms
1.8 V
1 V/div
VI = 5 V
100 ms/div
POWER-UP SEQUENCING
Figure 23
3.3 V
1.8 V
1 ms/div
1 V/div
POWER-DOWN SEQUENCING
TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217 – JUNE 1999
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Figure 24
90 A/µs
5 µs/div
1 A/div
100 mV/div
∆ = 100 mV
TRANSIENT RESPONSE (OVERSHOOT)
Figure 25
6.5 A/µs
∆V = 75 mV
5 µs/div
100 mV/div
1 A/div
TRANSIENT RESPONSE (UNDERSHOOT)
TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217 – JUNE 1999
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Table 1. SLVP121 Bill of Materials
REF. PART NUMBER MFR. DESCRIPTION SIZE
C1
†
Open
C2 Std Capacitor, ceramic, 470 pF,16 V, X7R, 20% 805
C3 Std Capacitor, ceramic, 2200 pF,16 V, X7R, 20% 805
C4 GRM235Y5V106Z016A muRata Capacitor, ceramic, 10 µF, 16 V, Y5V 1210
C5
†
Open 805
C6 Std Capacitor, ceramic, 1 µF, 16 V, X7R, 20% 1206
C7 Std Capacitor, ceramic, 2200 pF, 16 V, X7R, 20% 805
C8 Std Capacitor, ceramic, 2200 pF, 16 V, X7R, 20% 805
C9 GRK316F225ZG Taiyo Yuden Capacitor, ceramic, 2.2 µF, 35 V, X7R, 20% 1206
C11 GRK316F225ZG Taiyo Yuden Capacitor, ceramic, 2.2 µF, 35 V, X7R, 20% 1206
C12 GRK316F225ZG Taiyo Yuden Capacitor, ceramic, 2.2 µF, 35 V, X7R, 20% 1206
C13†Std Open 805
C14†Std Open 805
C15 10TPB220M SANYO Capacitor, electrolytic, 220 µF, 10 V, 20% 10×10 mm
C16 2R5TPB680M SANYO Capacitor, POSCAP, 680 µF, 2.5 V, 20% 7.3×4.3 mm
C17 4TPB470M SANYO Capacitor, POSCAP, 470 µF, 4 V, 20% 7.3×4.3 mm
C18 GMK325F106ZH Taiyo Yuden Capacitor , ceramic, 10 µF, 35 V 1210
C21 GMK325F106ZH Taiyo Yuden Capacitor , ceramic, 10 µF, 35 V 1210
D1 SD103-AWDICT-ND Digikey Diode, Schottky, 40 mA, 200 mA, 400 mW 3.5×1.5 mm
D2 SD103-AWDICT-ND Digikey Diode, Schottky, 40 mA, 200 mA, 400 mW 3.5×1.5 mm
J1 S1132-12-ND Sullins Header, right angle, 12-pin, 0.1 ctrs, 0.3” pins Digikey, S1132–12–ND
L2 DO3316P-682 Coilcraft Inductor, 6.8 µH, 4.4 A 0.5x0.37 in
L3 DO3316P-103 Coilcraft Inductor 10 µH, 3.9 A 0.5x0.37 in
Q1–Q4 Si441DY Rev. A Siliconix MOSFET, N-Ch, 30 V , 10-A, 0.013 Ω SO–8
R1 Std Resistor, SMD, MF, 1.74 kΩ, 1/8W, 1% 805
R4 Std Resistor, SMD, MF, 680 Ω, 1/8W, 1% 805
R6 Std Resistor, SMD, MF, 910 Ω, 1/8W, 1% 805
R7 Std Resistor, SMD, MF, 1.21 kΩ, 1/8W, 1% 805
R8 Std Resistor, SMD, MF, 15 Ω, 1/8W, 5% 805
R9 Std Resistor, SMD, MF, 15 Ω, 1/8W, 5% 805
R10 Std Resistor, SMD, MF, 5.1 kΩ, 1/8W, 5% 805
R11 Std Resistor, SMD, MF, 5.1 kΩ, 1/8W, 5% 805
R13†Std Open, resistor, SMD, MF, 3.3 kΩ, 1/8W, 5% 805
R14 Std Open, resistor, SMD, MF, kΩ, 1/8W, 5% 805
R15†Std Open, resistor, SMD, MF, 1 kΩ, 1/8W, 5% 805
R16†Std Open, resistor, SMD, MF, 200 kΩ, 1/8W, 5% 805
R17†Std Open, resistor, SMD, MF, 10 kΩ, 1/8W, 5% 805
R18†Std Open, resistor, SMD, MF, 1 kΩ, 1/8W, 5% 805
R19†Std Open, resistor, SMD, MF, 10 kΩ, 1/8W, 5% 805
R20†Std Open, resistor, SMD, MF, 0 kΩ 805
U1 TPS5602DBT TI Dual channel controller TSSOP 30-pin
U2
†
TLV1391 TI Open, single Comparator SOT-23
U3 TPS3305-18D TI Supervisor D
NOTE: This table is for 5–9 V input voltage and 3.3 V/1.8 V only.
†
Any components with † are for optional test purpose only.
TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217 – JUNE 1999
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
To change the EVM operating specifications, several suggestions are shown in the following table.
HIGH INPUT VOLTAGE
(TO 25 V)
2.5 V OUTPUT VOLTAGE
LOW-COST POWER
SEQUENCING
COMPONENT SECOND SOURCE
Change R1 to 1 kΩ Remove U3 Q1–4 IR7811 for higher efficiency
Add R15 (1 kΩ) Change Rt to 1.2 kΩ Add U2
Change C15 to ELNA
RV-35V221MH10-R (35 V, 220 µF)
Change U3 to TPS3305-25D Add R13, R16, R17, R19
TOP SIDE
BOTTOM SIDE
TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217 – JUNE 1999
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
BOARD ASSEMBLY
TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217 – JUNE 1999
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
+
–
Power Supply
5–V, 5–A Supply
NOTE: All wire pairs should be twisted.
Load
0 – 5 A
Load
0 – 5 A
Figure 26. Test Setup
TPS5602
DUAL, FAST, HIGH EFFICIENCY CONTROLLER FOR DSP POWER
SLVS217 – JUNE 1999
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
DBT (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
30 PINS SHOWN
0,75
0,25
0,50
0,15 NOM
Gage Plane
50
12,60
38
9,80 11,10
44
12,409,60 10,90
4073252/D 09/97
4,30
4,50
0,27
0,17
16
15
30
A
1
7,90
30
DIM
A MAX
PINS **
7,70
A MIN
1,20 MAX
6,60
6,20
Seating Plane
0,10
0,50
M
0,08
0°–8°
7,90
28
7,70
0,15
0,05
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC MO-153 except for pin count and body length
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