TPS5510
3-CHANNEL POWER SUPPLY SUPERVISOR
SLVS168 – JULY 1998
D
Over Voltage Protection and Lock Out for
5 V, 3.3 V, and 12 V
D
Under Voltage Protection and Lock Out for
5 V and 3.3 V
D
Fault Protection Output with Open Drain
Output Stage
D
Open Drain Power Good Output Signal for
D OR P PACKAGE
(TOP VIEW)
PGI
1
GND
FPO
PSON
2
3
4
PGO
8
V
7
CC
VS5
6
5
VS33
Power Good Input, 5 V and 3.3 V
D
300 ms Power Good Delay
D
75 ms Delay for 5-V and 3.3-V Short-Circuit
Turn On Protection
D
38 ms PSON Control Debounce
D
73 µs Width Noise Deglitches
D
Wide Power Supply Voltage Range
from 4 V to 15 V
description
The TPS5510 is designed to minimize external components of personal computer switching power supply
systems. It provides protection circuits, power good indicator, fault protection output (FPO
OVP (Over Voltage Protection) monitors 5 V, 3.3 V, and 12 V (12 V OV detects via V
Voltage Protection) monitors 5 V and 3.3 V. When an OV or UV condition is detected, the PGO (power good
output) is asserted low and FPO
will be enabled 75 ms after PSON
is latched high. PSON from low to high resets the protection latch. UVP function
is set low and debounced.
), and a PSON control.
terminal). UVP (Under
CC
Power good feature monitors PGI, 5 V and 3.3 V and issues a power good signal when they are ready.
The TPS5510 is characterised for operation from T
5 V
SB
TPS5510
1
PGI
2
GND
3
FPO
PSON
4
PSON
= –40°C to 125°C junction temperature.
J
0.5 V
Drop
PGO
V
CC
VS5
VS33
8
7
6
5
PGI
PGO
12 V
V
SB
5 V
3.3 V
Figure 1. TPS5510 Typical Application
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1998, Texas Instruments Incorporated
1
TPS5510
3-CHANNEL POWER SUPPLY SUPERVISOR
SLVS168 – JULY 1998
functional block diagram
V
CC
VS5
VS33
Vref
Vref
RI = 100 kΩ
Vref
RI = 100 kΩ
Vref
Vref
–
+
RI = 200 kΩ
5 OV
–
+
3.3 OV
–
+
–
3.3 UV
+
–
5 UV
+
12 OV
RST
73 µs
Debounce
R
75 ms
Delay
Counter
Reset
R
73 µs
Debounce
Reset
OSC
EN
73 µs
Debounce
POR Vreg
V
CCI
R
Derminent
RTT
RST
R
R
EN
= 3.6 V
R
S
Reset
Latch
300 ms
Delay
Counter
RTT
Q
Reset
38 ms
Debounce
Bandgap
Reference
Vref
1.192 V
V
150 µA
CCI
V
V
CC
Pull-High
Resistor
FPO
CC
PSON
PGO
RST
Vref
PGI
2
–
+
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265