Texas Instruments TPS54810 User Manual
www.ti.com
6,4 mm X 9,7 mm
SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005
4-V TO 6-V INPUT, 8-A OUTPUT SYNCHRONOUS BUCK PWM
SWITCHER WITH INTEGRATED FETS (SWIFT™)
TPS54810
FEATURES
D 30-mΩ MOSFET Switches for High Efficiency
at 8-A Continuous Output
D 0.9-V to 3.3-V Adjustable Output Voltage
Range With 1% Accuracy
D Externally Compensated
D Fast Transient Response
D Wide PWM Frequency:
Fixed 350 kHz, 550 kHz or
Adjustable 280 kHz to 700 kHz
D Load Protected by Peak Current Limit and
Thermal Shutdown
D Integrated Solution Reduces Board Area and
Total Cost
APPLICATIONS
D Low-Voltage, High-Density Systems With
Power Distributed at 5 V
D Point of Load Regulation for High
Performance DSPs, FPGAs, ASICs and
Microprocessors
D Broadband, Networking, and Optical
Communications Infrastructure
D Portable Computing/Notebook PCs
DESCRIPTION
As a member of the SWIFT™ family of dc/dc regulators,
the TPS54810 low-input voltage high-output current
synchronous buck PWM converter integrates all
required active components. Included on the substrate
with the listed features are a true, high performance,
voltage error amplifier that enables maximum
performance under transient conditions and flexibility in
choosing the output filter L and C components; an
under-voltage-lockout circuit to prevent start-up until
the input voltage reaches 3.8 V; an internally or
externally set slow-start circuit to limit in-rush currents;
and a power good output useful for processor/logic
reset, fault signaling, and supply sequencing.
The TPS54810 is available in a thermally enhanced
28-pin TSSOP (PWP) PowerPAD™ package, which
eliminates bulky heatsinks. TI provides evaluation
modules and the SWIFT™ designer software tool to aid
in quickly achieving high-performance power supply
designs to meet aggressive equipment development
cycles.
SIMPLIFIED SCHEMATIC
Input
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD and SWIFT are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
VIN PH
TPS54810
BOOT
PGND
VBIAS
VSENSE
COMP
VSENSE
AGND
Compensation Network
Output
100
Efficiency − %
EFFICIENCY AT 700 HZ
95
90
85
80
75
70
65
60
55
50
012345678910
IL − Load Current − A
Copyright © 2002, Texas Instruments Incorporated
VI = 5 V
VO = 3.3 V
TPS54810
Sink current, I
S
SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
www.ti.com
T
A
−40°C to 85°C 0.9 V to 3.3 V PLASTIC HTSSOP (PWP)
(1)
The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS54810PWPR). See the application section
OUTPUT VOLTAGE PACKAGE PART NUMBER
(1)
TPS54810PWP
of the data sheet for PowerPAD™ drawing and layout information.
(2)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website
at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
VIN, SS/ENA, SYNC −0.3 to 7
Input voltage range, V
I
RT −0.3 to 6
VSENSE −0.3 to 4
BOOT −0.3 to 17
Output voltage range, V
Source current, I
O
O
VBIAS, COMP, PWRGD −0.3 to 7
PH −0.6 to 10
PH Internally Limited
COMP, VBIAS 6 mA
PH 12 A
Sink current, I
S
COMP 6
SS/ENA, PWRGD 10
Voltage differential AGND to PGND ±0.3 V
Operating virtual junction temperature range, T
Storage temperature, T
stg
J
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300 °C
(1)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(1)
TPS54810 UNIT
−40 to 125 °C
−65 to 150 °C
V
V
mA
RECOMMENDED OPERATING CONDITIONS
Input voltage range, V
Operating junction temperature, T
DISSIPATION RATINGS
28-Pin PWP with solder 18.2 °C/W 5.49 W
28-Pin PWP without solder 40.5 °C/W 2.48 W 1.36 W 0.99 W
(1)
For more information on the PWP package, refer to TI technical brief, literature number SLMA002.
(2)
Test Board Conditions:
1. 3” x 3”, 4 layers, thickness: 0.062”
2. 1.5 oz. copper traces located on the top of the PCB
3. 1.5 oz. copper ground plane on the bottom of the PCB
4. 0.5 oz. copper ground planes on the 2 internal layers
5. 12 thermal vias (see “Recommended Land Pattern” in applications section of this data sheet)
(3)
Maximum power dissipation may be limited by over current protection.
2
I
PACKAGE
J
(1) (2)
THERMAL IMPEDANCE
JUNCTION-TO-AMBIENT
TA ≤ 25°C
POWER RATING
MIN NOM MAX UNIT
4 6 V
−40 125 °C
TA = 70°C
POWER RATING
(2)
3.02 W 2.20 W
TA = 85°C
POWER RATING
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(1) (3)
(1) (3)
Externally set free running frequency range
kHz
ELECTRICAL CHARACTERISTICS
TJ = −40°C to 125°C, VI = 4 V to 6 V unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE, VIN
Input voltage range, VIN 4.0 6.0 V
I
(Q)
UNDER VOLTAGE LOCK OUT
BIAS VOLTAGE
CUMULATIVE REFERENCE
V
REGULATION
OSCILLATOR
(1)
(2)
(3)
Quiescent current
Start threshold voltage, UVLO 3.8 3.85 V
Stop threshold voltage, UVLO 3.40 3.50 V
Hysteresis voltage, UVLO 0.14 0.16 V
Rising and falling edge deglitch, UVLO
(1)
Output voltage, VBIAS I
Output current, VBIAS
Accuracy 0.882 0.891 0.900 V
ref
(2)
Line regulation
Load regulation
Internally set—free running frequency range
Externally set—free running frequency range
High level threshold, SYNC 2.5 V
Low level threshold, SYNC 0.8 V
Pulse duration, external sychronization, SYNC
Frequency range, SYNC
Ramp valley
(1)
Ramp amplitude (peak-to-peak)
Minimum controllable on time
Maximum duty cycle
(1)
(1)
(1)
(1)
(1)
Specified by design
Static resistive loads only
Specified by the circuit used in Figure 9
TPS54810
SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005
fs = 350 kHz, SYNC ≤ 0.8 V, RT open,
PH pin open
fs = 550 kHz, SYNC ≥ 2.5 V, RT open,
PH pin open
Shutdown, SS/ENA = 0 V 1.0 1.4
= 0 2.70 2.80 2.90 V
(VBIAS)
IL = 4 A, fs = 350 kHz, TJ = 85°C 0.04
IL = 4 A, fs = 550 kHz, TJ = 85°C 0.04
IL = 0 A to 8 A, fs = 350 kHz, TJ = 85°C 0.03
IL = 0 A to 8 A, fs = 550 kHz, TJ = 85°C 0.03
SYNC ≤ 0.8 V, RT open 280 350 420
SYNC ≥ 2.5 V, RT open 440 550 660
RT = 180 kΩ (1% resistor to AGND) 252 280 308
RT = 100 kΩ (1% resistor to AGND) 460 500 540
RT = 68 kΩ (1% resistor to AGND) 663 700 762
50 ns
330 700 kHz
90%
11 15.8
16 23.5
2.5 µs
100 µA
0.75 V
1 V
200 ns
mA
%/V
%/A
kHz
kHz
3
TPS54810
SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005
www.ti.com
ELECTRICAL CHARACTERISTICS CONTINUED
TJ = −40°C to 125°C, VI = 4 V to 6 V unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ERROR AMPLIFIER
Error amplifier open loop voltage gain 1 kΩ COMP to AGND
Error amplifier unity gain bandwidth Parallel 10 kΩ, 160 pF COMP to AGND
Error amplifier common mode input voltage
range
Powered by internal LDO
Input bias current, VSENSE VSENSE = V
Output voltage slew rate (symmetric), COMP 1.0 1.4 V/µs
PWM COMPARATOR
PWM comparator propagation delay time, PWM
comparator input to PH pin (excluding dead-
10-mV overdrive
time)
SLOW-START/ENABLE
Enable threshold voltage, SS/ENA 0.82 1.20 1.40 V
Enable hysteresis voltage, SS/ENA
Falling edge deglitch, SS/ENA
(1)
(1)
Internal slow-start time 2.6 3.35 4.1 ms
Charge current, SS/ENA SS/ENA = 0V 3 5 8 µA
Discharge current, SS/ENA SS/ENA = 1.3 V, VI = 1.5 V 1.5 2.3 4.0 mA
POWER GOOD
Power good threshold voltage VSENSE falling 90 %V
Power good hysteresis voltage
Power good falling edge deglitch
Output saturation voltage, PWRGD I
Leakage current, PWRGD V
(1)
(1)
= 2.5 mA 0.18 0.3 V
(sink)
= 3.6 V 1 µA
I
CURRENT LIMIT
(1)
V
Current limit
I
V
I
= 4.5 V
= 6 V
, output shorted 9 11
(1)
, output shorted 10 12
Current limit leading edge blanking time 100 ns
Current limit total response time 200 ns
THERMAL SHUTDOWN
Thermal shutdown trip point
Thermal shutdown hysteresis
(1)
(1)
OUTPUT POWER MOSFETS
(2)
r
DS(on)
(1)
(2)
Power MOSFET switches
Specified by design
Matched MOSFETs, low-side r
production tested, high-side r
DS(on)
VI = 6 V
VI = 4.5 V
(2)
DS(on)
(1)
(1)
ref
(1)
production tested.
90 110 dB
(1)
3 5 MHz
0 VBIAS V
60 250 nA
70 85 ns
0.03 V
2.5 µs
3 %V
35 µs
135 150 165 _C
10 _C
26 47
30 60
ref
ref
A
mΩ
4
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TPS54810
SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005
PWP PACKAGE
(TOP VIEW)
AGND
VSENSE
COMP
PWRGD
BOOT
PH
PH
PH
PH
PH
PH
PH
PH
PH
1
2
3
4
5
6
7
8
9
10
11
12
13
14
THERMAL
PAD
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RT
SYNC
SS/ENA
VBIAS
VIN
VIN
VIN
VIN
VIN
PGND
PGND
PGND
PGND
PGND
Terminal Functions
TERMINAL
NAME NO.
AGND 1 Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT resistor and
SYNC pin. Connect PowerPAD to AGND.
BOOT 5 Bootstrap input. 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating drive for the
high-side FET driver.
COMP 3 Error amplifier output. Connect frequency compensation network from COMP to VSENSE.
PGND 15−19 Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper areas
to the input and output supply returns, and negative terminals of the input and output capacitors. A single point
connection to AGND is recommended.
PH 6−14 Phase input/output. Junction of the internal high-side and low-side power MOSFETs, and output inductor.
PWRGD 4 Power good open drain output. High-Z when VSENSE ≥ 90% V
when SS/ENA is low or the internal shutdown signal is active.
RT 28 Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency. When using the
SYNC pin, set the RT value for a frequency at or slightly lower than the external oscillator frequency.
SS/ENA 26 Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device operation and
capacitor input to externally set the start-up time.
SYNC 27 Synchronization input. Dual function pin which provides logic input to synchronize to an external oscillator or pin select
between two internally set switching frequencies. When used to synchronize to an external signal, a resistor must be
connected to the RT pin.
VBIAS 25 Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a
high quality, low-ESR 0.1-µF to 1.0-µF ceramic capacitor.
VIN
VSENSE 2 Error amplifier inverting input. Connect to output voltage through compensation network/output divider.
20−24 Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to
device package with a high quality, low-ESR 10-µF ceramic capacitor.
DESCRIPTION
ref
, otherwise PWRGD is low. Note that output is low
5
TPS54810
SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005
FUNCTIONAL BLOCK DIAGRAM
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SS/ENA
VIN
Enable
Comparator
1.2 V
Hysteresis: 0.03 V
VIN UVLO
Comparator
VIN
3.8 V
Hysteresis: 0.16 V
Internal/External
VREF = 0.891 V
TPS54810
Slow-Start
Reference
(Internal Slow-Start Time = 3.35 ms)
Falling
Edge
Deglitch
2.5 µs
Falling
and
Rising
Edge
Deglitch
2.5 µs
Thermal
Shutdown
150°C
+
−
Error
Amplifier
SS_DIS
PWM
Comparator
OSC
RTCOMPVSENSE
SHUTDOWN
Leading
Edge
Blanking
100 ns
RQ
S
Powergood
Comparator
VSENSE
0.90 V
ref
Hysteresis: 0.03 Vref
SYNC
AGND
VBIAS
ILIM
Comparator
SHUTDOWN
Adaptive Dead-Time
Control Logic
SHUTDOWN
and
VIN
VBIAS
Falling
Deglitch
REG
Edge
35 µs
30 mΩ
30 mΩ
VIN
BOOT
PH
PGND
PWRGD
3 − 6 V
L
OUT
C
V
O
O
RELATED DC/DC PRODUCTS
D TPS56300—dc/dc controller
D PT6600 series—9-A plugin modules
6
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g
TPS54810
SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005
TYPICAL CHARACTERISTICS
DRAIN-SOURCE
ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
60
Ω
VI = 5 V,
IO = 8 A
50
40
30
20
10
Drain Source On-State Reststance − m
0
−40 −15 10 35 60 85 110 135
TJ − Junction Temperature − °C
Figure 1
EXTERNALLY SET
OSCILLATOR FREQUENCY
vs
JUNCTION TEMPERATURE
800
700
600
500
400
300
f − Externally Set Oscillator Frequency − kHz
200
−40 0 25 85 125
RT = 68 k
RT = 100 k
RT = 180 k
TJ − Junction Temperature − °C
Figure 3
f − Internally Set Oscillator Frequency − kHz
VOLTAGE REFERENCE
vs
JUNCTION TEMPERATURE
0.895
0.893
0.891
0.889
− Voltage Reference − V
ref
0.887
V
0.885
−40 0 25 85 125
TJ − Junction Temperature − °C
Figure 4
INTERNALLY SET
OSCILLATOR FREQUENCY
vs
JUNCTION TEMPERATURE
750
650
SYNC ≥ 2.5 V
550
450
SYNC ≤ 0.8 V
350
250
−40 0 25 85 125
TJ − Junction Temperature − °C
Figure 2
DEVICE POWER LOSSES
5
4.5
4
3.5
3
2.5
2
1.5
Device Power Losses − W
1
0.5
0
012345678
LOAD CURRENT
TJ = 125°C
fs = 700 kHz
IL − Load Current − A
vs
VI = 5 V
Figure 5
OUTPUT VOLTAGE REGULATION
vs
INPUT VOLTAGE
4.5 4.8 5.1 5.4 5.7 6
V
− Input Voltage − V
I
− Output Voltage Regulation − V
V
0.895
0.893
0.891
0.889
0.887
O
0.885
Figure 6
ERROR AMPLIFIER
OPEN LOOP RESPONSE
140
120
100
80
60
Gain − dB
40
20
0
−20
1 100 1 k 1 M
10 10 k 100 k 10 M
f − Frequency − Hz
RL = 10 kΩ,
CL = 160 pF,
TA = 25°C
Phase
Gain
Figure 7
0
−20
−40
−60
−80
−100
−120
−140
−160
−180
−200
rees
Phase − De
INTERNAL SLOW-START TIME
vs
JUNCTION TEMPERATURE
3.80
3.65
3.50
3.35
3.20
3.05
Internal Slow-Start Time − ms
2.90
2.75
−40 0 25 85 125
TJ − Junction Temperature − °C
Figure 8
7
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