TEXAS INSTRUMENTS TPS54620 Technical data

100

95

90

85

80

75

70

65

60

55

50

Efficiency-%

0 1 2 3 4 5 6

LoadCurrent- A

8V

12V

17V

VOUT =3.3V
Fsw=480kHz

PH

PVIN

GND

BOOT

VSENSE

COMP

TPS54620

EN

RT/CLK

SS/TR

PowerPAD

Css

Rrt

R3

C1

Cboot

Co

Lo

R1

R

2

Cin

C2

VIN

VIN

VOUT

PWRGD

TPS54620

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........................................................................................................................................................................................................ SLVS949 – MAY 2009

17V Input, 6A Output, Synchronous Step Down Switcher

With Integrated FET in 3.5mm x 3.5mm Package( SWIFT™)

1

FEATURES

2

• Integrated 26m Ω / 19m Ω MOSFETs

• Split Power Rail: 1.6V to 17V on PVIN

• 200kHz to 1.6MHz Switching Frequency

• Synchronizes to External Clock

• 0.8V ± 1% Voltage Reference Over Temperature

• Low 2uA Shutdown Quiscent Current

• Monotonic Start-Up into Prebiased Outputs

• – 40 ° C to 150 ° C Operating Junction

Temperature Range

• Adjustable Slow Start/Power Sequencing

DESCRIPTION

The TPS54620 in thermally enhanced 3.5mm x 3.5mm QFN package is a full featured 17V, 6A synchronous step
down converter which is optimized for small designs through high efficiency and integrating the high-side and
low-side MOSFETs. Further space savings are achieved through current mode control, which reduces
component count, and by selecting a high switching frequency, reducing the inductor ' s footprint.

The output voltage startup ramp is controlled by the SS/TR pin which allows operation as either a stand alone
power supply or in tracking situations. Power sequencing is also possible by correctly configuring the enable and
the open drain power good pins.

Cycle by cycle current limiting on the high-side fet protects the device in overload situations and is enhanced by
a low-side sourcing current limit which prevents current runaway. There is also a low-side sinking current limit
which turns off the low-side MOSFET to prevent excessive reverse current. Thermal shutdown disables the part
when die temperature rises too high.

WHITE SPACE

SIMPLIFIED SCHEMATIC

• Power Good Output Monitor for Undervoltage

& Overvoltage

• Adjustable Input Undervoltage Lockout

• Supported by SwitcherPro™ Software Tool

• For SWIFT™ Documentation and

SwitcherPro™, visit http://www.ti.com/swift

APPLICATIONS

• High Density Distributed Power Systems

• High Peformance Point of Load Regulation

• Broadband, Networking and Optical

Communications Infrastructure

1

2 SWIFT, PowerPAD are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright © 2009, Texas Instruments Incorporated

TPS54620

SLVS949 – MAY 2009 ........................................................................................................................................................................................................

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

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ORDERING INFORMATION

T

J

– 40 ° C to 150 ° C 14 Pin QFN TPS54620RGY

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com .

(2) The RGY package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS54620RGYR). See applications

section of data sheet for layout information

ABSOLUTE MAXIMUM RATINGS

over operating temperature range (unless otherwise noted)

VIN – 0.3 to 20 V
PVIN – 0.3 to 20 V
EN – 0.3 to 3 V
BOOT – 0.3 to 27 V

Input Voltage VSENSE – 0.3 to 3 V

COMP – 0.3 to 3 V
PWRGD – 0.3 to 6 V
SS/TR – 0.3 to 3 V
RT/CLK – 0.3 to 6 V
BOOT-PH 0 to 7 V

Output Voltage PH – 1 to 20 V

PH 10ns Transient – 3 to 20 V

Vdiff(GND to PowerPAD) – 0.2 to 0.2 V

Source Current

Sink Current

Electrostatic Discharge (HBM) QSS 009-105 (JESD22-A114A) 2 kV
Electrostatic Discharge (CDM) QSS 009-147 (JESD22-C101B.01) 500 V
Operating Junction Temperature – 40 to 150 ° C
Storage Temperature – 65 to 150 ° C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

RT/CLK ± 100 µ A
PH Current Limit A
PH Current Limit A
PVIN Current Limit A
COMP ± 200 µ A
PWRGD – 0.1 to 5 mA

(1)

PACKAGE PART NUMBER

(1)

(2)

VALUE UNIT

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........................................................................................................................................................................................................ SLVS949 – MAY 2009

PACKAGE DISSIPATION RATINGS

PACKAGE

RGY 32 ° C/W 5 ° C/W

(1) Maximum power dissipation may be limited by overcurrent protection
(2) Power rating at a specific ambient temperature TAshould be determined with a junction temperature of 150 ° C. This is the point where

distortion starts to substantially increase. Thermal management of the PCB should strive to keep the junction temperature at or below
150 ° C for best performance and long-term reliability. See power dissipation estimate in application section of this data sheet for more
information.

(3) Test board conditions:

a. 2.5 inches × 2.5 inches, 4 layers, thickness: 0.062 inch
b. 2 oz. copper traces located on the top of the PCB
c. 2 oz. copper ground planes on the 2 internal layers and bottom layer
d. 4 thermal vias located under the device package

(1) (2) (3)

THERMAL IMPEDANCE ψ

JUNCTION TO AMBIENT JUNCTION TO TOP

THERMAL CHARACTERISTIC

JT

ELECTRICAL CHARACTERISTICS

TJ= – 40 ° C to 150 ° C, VIN = 4.5V to 17V, PVIN = 1.6V to 17V (unless otherwise noted)

DESCRIPTION CONDITIONS MIN TYP MAX UNIT

SUPPLY VOLTAGE (VIN AND PVIN PINS)

PVIN operating input voltage 1.6 17 V
VIN operating input voltage 4.5 17 V
VIN internal UVLO threshold VIN rising 4.0 4.5 V
VIN internal UVLO hysterisis 150 mV
VIN shutdown supply Current EN = 0 V 2 5 µ A
VIN operating – non switching supply current VSENSE = 810 mV 600 800 µ A

ENABLE AND UVLO (EN PIN)

Enable threshold Rising 1.21 1.26 V
Enable threshold Falling 1.10 1.17
Input current EN = 1.1 V 1.15 µ A
Hysteresis current EN = 1.3 V 3.4 µ A

VOLTAGE REFERENCE

Voltage reference 0 A ≤ Iout ≤ 6 A 0.792 0.800 0.808 V

MOSFET

High-side switch resistance BOOT-PH = 3 V 32 60 m Ω
High-side switch resistance
Low-side Switch Resistance

ERROR AMPLIFIER

Error amplifier Transconductance (gm) – 2 µ A < ICOMP < 2 µ A, V(COMP) = 1 V 1300 µ Mhos
Error amplifier dc gain VSENSE = 0.8 V 1000 3100 V/V
Error amplifier source/sink V(COMP) = 1 V, 100 mV input overdrive ± 110 µ A
Start switching threshold 0.25 V
COMP to Iswitch gm 16 A/V

CURRENT LIMIT

High-side switch current limit threshold 8 11 A
Low-side switch sourcing current limit 7 10 A
Low-side switch sinking current limit 2.3 A

(1) Measured at pins

(1)

(1)

BOOT-PH = 6 V 26 40 m Ω
VIN = 12 V 19 30 m Ω

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TPS54620

SLVS949 – MAY 2009 ........................................................................................................................................................................................................

ELECTRICAL CHARACTERISTICS (continued)

TJ= – 40 ° C to 150 ° C, VIN = 4.5V to 17V, PVIN = 1.6V to 17V (unless otherwise noted)

DESCRIPTION CONDITIONS MIN TYP MAX UNIT

THERMAL SHUTDOWN

Thermal shutdown 160 175 ° C
Thermal shutdown hysterisis 10 ° C

TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)

Minimum switching frequency Rrt = 240 k Ω (1%) 180 200 220 kHz
Switching frequency Rrt = 100 k Ω (1%) 400 480 560 kHz
Maximum switching frequency Rrt = 29 k Ω (1%) 1440 1600 1760 kHz
Minimum pulsewidth 20 ns
RT/CLK high threshold 2 V
RT/CLK low threshold 0.8 V
RT/CLK falling edge to PH rising edge delay Measure at 500 kHz with RT resistor in series 66 ns
Switching frequency range (RT mode set point 200 1600 kHz

and PLL mode)

PH (PH PIN)

Minimum on time Measured at 90% to 90% of VIN, 25 ° C, IPH= 2A 94 135 ns
Minimum off time BOOT-PH ≥ 3 V 0 ns

BOOT (BOOT PIN)

BOOT-PH UVLO 2.1 3 V

SLOW START AND TRACKING (SS/TR PIN)

SS charge current 2.3 µ A
SS/TR to VSENSE matching V(SS/TR) = 0.4 V 29 60 mV

POWER GOOD (PWRGD PIN)

VSENSE threshold VSENSE falling (Fault) 91 % Vref

VSENSE rising (Good) 94 % Vref
VSENSE rising (Fault) 109 % Vref

VSENSE falling (Good) 106 % Vref
Output high leakage VSENSE = Vref, V(PWRGD) = 5.5 V 30 100 nA
Output low I(PWRGD) = 2 mA 0.3 V
Minimum VIN for valid output V(PWRGD) < 0.5V at 100 µ A 0.6 1 V
Minimum SS/TR voltage for PWRGD 1.4 V

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1

2

3

4

5

6

7

9

8

10

PowerPAD

RGY (TopView )

EN

GND

VIN

VSENSE

RT/CLK

SS/TR

PH

BOOT

PWRGD

COMP

(15)

PVIN

PVIN

PH

GND

11

12

13

14

TPS54620

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PIN ASSIGNMENTS

........................................................................................................................................................................................................ SLVS949 – MAY 2009

DEVICE INFORMATION

PIN FUNCTIONS

PIN DESCRIPTION

NAME No.

RT/CLK 1 Automatically selects between RT mode and CLK mode. An external timing resistor adjusts the switching

GND 2, 3 Return for control circuitry and low-side power MOSFET.
PVIN 4, 5 Power input. Supplies the power switches of the power converter.
VIN 6 Supplies the control circuitry of the power converter.
VSENSE 7 Inverting input of the gm error amplifier.
COMP 8 Error amplifier output, and input to the output switch current comparator. Connect frequency compensation to this

SS/TR 9 Slow-start and tracking. An external capacitor connected to this pin sets the internal voltage reference rise time.

EN 10 Enable pin. Float to enable. Adjust the input undervoltage lockout with two resistors.
PH 11, 12 The switch node.
BOOT 13 A bootstrap cap is required between BOOT and PH. The voltage on this cap carries the gate drive voltage for the

PWRGD 14 Power Good fault pin. Asserts low if output voltage is low due to thermal shutdown, dropout, over-voltage, EN

PowerPAD 15 Thermal pad of the package and signal ground. It must be soldered down for proper operation.

frequency of the device; In CLK mode, the device synchronizes to an external clock.

pin.

The voltage on this pin overrides the internal reference. It can be used for tracking and sequencing.

high-side MOSFET.

shutdown or during slow start.

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ERROR

AMPLIFIER

Boot

Charge

UVLO

Current

Sense

Oscillator

withPLL

Slope

Compensation

and

Clamp

Voltage

Reference

VSENSE

SS/TR

COMP

RT/CLK

PH

BOOT

VIN

GND

Thermal

Shutdown

EN

Enable

Comparator

Shutdown

Logic

Shutdown

Enable

Threshold

Logic

Shutdown

PWRGD

POWERPAD

PowerStage

& Deadtime

Control

Logic

LSMOSFET
CurrentLimit

OV

MinimumClamp

PulseSkip

Ip Ih

PVIN

UV

HSMOSFET

Current

Comparator

Current

Sense

RegulatorVIN

Boot

UVLO

PH

GND

PVIN

OverloadRecovery

TPS54620

SLVS949 – MAY 2009 ........................................................................................................................................................................................................

FUNCTIONAL BLOCK DIAGRAM

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TJ − Junction Temperature − °C

20

25

30

35

40

−50 −25 0 25 50 75 100 125 150

VIN = 12 V

R

DS(on)

− On Resistance − mΩ

TJ − Junction Temperature − °C

15

18

21

24

27

30

−50 −25 0 25 50 75 100 125 150

VIN = 12 V

R

DS(on)

− On Resistance − mΩ

TJ − Junction Temperature − °C

0.795

0.797

0.799

0.801

0.803

0.805

−50 −25 0 25 50 75 100 125 150

V

ref

− Voltage Resistance − V

TJ − Junction Temperature − °C

470

475

480

485

490

−50 −25 0 25 50 75 100 125 150

RT = 100 kΩ

f

O

− Oscillator Frequency − kHz

VI − Input Voltage − V

0

1

2

3

4

3 6 9 12 15 18

EN = 0 V

I

sd

− Shutdown Quescent − µA

TJ = 150°C

TJ = 25°C

TJ = −40°C

TJ − Junction Temperature − °C

3.30

3.35

3.40

3.45

3.50

−50 −25 0 25 50 75 100 125 150

VIN = 12 V
EN = 1.3 V

En Pin Hysterisis Current − µA

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........................................................................................................................................................................................................ SLVS949 – MAY 2009

CHARACTERISTIC CURVES

TPS54620

TYPICAL CHARACTERISTICS

HIGH-SIDE Rdson vs TEMPERATURE LOW-SIDE Rdson vs TEMPERATURE

Figure 1. Figure 2.

VOLTAGE REFERENCE vs TEMPERATURE OSCILLATOR FREQUENCY vs TEMPERATURE

Figure 3. Figure 4.

SHUTDOWN QUIESCENT CURRENT vs INPUT VOLTAGE PIN HYSTERISIS CURRENT vs TEMPERATURE

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Figure 5. Figure 6.

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TJ − Junction Temperature − Deg

1.10

1.15

1.20

−50 −25 0 25 50 75 100 125 150

VIN = 12 V
EN = 1.1 V

I

P

− En Pin On Pullup − uA

TJ − Junction Temperature − °C

1.200

1.205

1.210

1.215

1.220

−50 −25 0 25 50 75 100 125 150

VIN = 12 V

En Pin UVLO Threshold − V

TJ − Junction Temperature − °C

2.1

2.2

2.3

2.4

2.5

−50 −25 0 25 50 75 100 125 150

I

SS

− Slow Start Charge Current − µA

VI − Input Voltage − V

400

500

600

700

800

3 6 9 12 15

TJ = −40°C

Non-Switching Operating Quiescent Current − µA

TJ = −25°C

TJ = 150°C

TJ − Junction Temperature − °C

0.01

0.02

0.03

0.04

0.05

−50 −25 0 25 50 75 100 125 150

(SS/TR - Vsense) Offset − V

TJ − Junction Temperature − °C

80

90

100

110

120

−50 −25 0 25 50 75 100 125 150

VIN = 12 V

PWRGD Threshold Current − µA

VSENSE Rising

VSENSE Falling

VSENSE Rising

VSENSE Falling

TPS54620

SLVS949 – MAY 2009 ........................................................................................................................................................................................................

TYPICAL CHARACTERISTICS (continued)

PIN PULLUP CURRENT vs TEMPERATURE PIN UVLO THRESHOLD vs TEMPERATURE

Figure 7. Figure 8.

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NON-SWITCHING OPERATING QUIESCENT CURRENT

(VIN) vs INPUT VOLTAGE SLOW START CHARGE CURRENT vs TEMPERATURE

Figure 9. Figure 10.

(SS/TR - VSENSE) OFFSET vs TEMPERATURE PWRGD THRESHOLD vs TEMPERATURE

8 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated

Figure 11. Figure 12.

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VI − Input Voltage − V

5

6

7

8

9

10

11

12

13

1 5 9 13 17

TJ = 150°C

IcI − Current Limit Threshold − A

TJ = 25°C

TJ = −40°C

TJ − Junction Temperature − °C

70

80

90

100

110

120

−50 −25 0 25 50 75 100 125 150

VIN = 12 V
IOUT = 2A

Minimum Controllable On Time − ns

TJ − Junction Temperature − °C

2.0

2.1

2.2

−50 −25 0 25 50 75 100 125 150

BOO-PH UVLO Threshold − V

TJ − Junction Temperature − Deg

3.0

4.0

5.0

6.0

−50 −25 0 25 50 75 100 125 150

RT = 100 kΩ
VIN =12 V
IOUT = 2 A

Dmin − Minimum Controllable Duty Ratio − %

TPS54620

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........................................................................................................................................................................................................ SLVS949 – MAY 2009

TYPICAL CHARACTERISTICS (continued)

HIGH-SIDE CURRENT LIMIT THRESHOLD vs INPUT

VOLTAGE MINIMUM CONTROLLABLE ON TIME vs TEMPERATURE

Figure 13. Figure 14.

MINIMUM CONTROLLABLE DUTY RATIO vs JUNCTION

TEMPERATURE BOOT-PH UVLO THRESHOLD vs TEMPERATURE

Figure 15. Figure 16.

OVERVIEW

The device is a 17-V, 6-A, synchronous step-down (buck) converter with two integrated n-channel MOSFETs. To
improve performance during line and load transients the device implements a constant frequency, peak current
mode control which also simplifies external frequency compensation. The wide switching frequency of 200 kHz to
1600 kHz allows for efficiency and size optimization when selecting the output filter components. The switching
frequency is adjusted using a resistor to ground on the RT/CLK pin. The device also has an internal phase lock
loop (PLL) controlled by the RT/CLK pin that can be used to synchronize the switching cycle to the falling edge
of an external system clock.

The device has been designed for safe monotonic startup into pre-biased loads. The default start up is when VIN
is typically 4.0V. The EN pin has an internal pull-up current source that can be used to adjust the input voltage
under voltage lockout (UVLO) with two external resistors. In addition, the EN pin can be floating for the device to
operate with the internal pull up current. The total operating current for the device is approximately 600 µ A when
not switching and under no load. When the device is disabled, the supply current is typically less than 2 µ A.

The integrated MOSFETs allow for high efficiency power supply designs with continuous output currents up to 6
amperes. The MOSFETs have been sized to optimize efficiency for lower duty cycle applications.

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TPS54620

SLVS949 – MAY 2009 ........................................................................................................................................................................................................

TYPICAL CHARACTERISTICS (continued)

The device reduces the external component count by integrating the boot recharge circuit. The bias voltage for
the integrated high-side MOSFET is supplied by a capacitor between the BOOT and PH pins. The boot capacitor
voltage is monitored by a BOOT to PH UVLO (BOOT-PH UVLO) circuit allowing PH pin to be pulled low to
recharge the boot capacitor. The device can operate at 100% duty cycle as long as the boot capacitor voltage is
higher than the preset BOOT-PH UVLO threshold which is typically 2.1V. The output voltage can be stepped
down to as low as the 0.8V voltage reference (Vref).

The device has a power good comparator (PWRGD) with hysteresis which monitors the output voltage through
the VSENSE pin. The PWRGD pin is an open drain MOSFET which is pulled low when the VSENSE pin voltage
is less than 91% or greater than 109% of the reference voltage Vref and asserts high when the VSENSE pin
voltage is 94% to 106% of the Vref.

The SS/TR (slow start/tracking) pin is used to minimize inrush currents or provide power supply sequencing
during power up. A small value capacitor or resistor divider should be coupled to the pin for slow start or critical
power supply sequencing requirements.

The device is protected from output overvoltage, overload and thermal fault consitions. The device minimizes
excessive output overvoltage transients by taking advantage of the overvoltage circuit power good comparator.
When the overvoltage comparator is activated, the high-side MOSFET is turned off and prevented from turning
on until the VSENSE pin voltage is lower than 106% of the Vref. The device implements both high-side MOSFET
overload protection and bidirectional low-side MOSFET overload protections which help control the inductor
current and avoid current runaway. The device also shuts down if the junction temperature is higher than thermal
shutdown trip point. The device is restarted under control of the slow start circuit automatically when the junction
temperature drops 10 ° C typically below the thermal shutdown trip point.

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DETAILED DESCRIPTION

Fixed Frequency PWM Control

The device uses a adjustable fixed frequency, peak current mode control. The output voltage is compared
through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives
the COMP pin. An internal oscillator initiates the turn on of the high-side power switch. The error amplifier output
is converted into a current reference which compares to the high-side power switch current. When the power
switch current reaches current reference generated by the COMP voltage level the high-side power switch is
turned off and the low-side power switch is turned on.

Continuous Current Mode Operation (CCM)

As a synchronous buck converter, the device normally works in CCM (Continuous Conduction Mode) under all
load conditions.

VIN and Power VIN Pins (VIN and PVIN)

The device allows for a variety of applications by using the VIN and PVIN pins together or separately. The VIN
pin voltage supplies the internal control circuits of the device. The PVIN pin voltage provides the input voltage to
the power converter system.

If tied together, the input voltage for VIN and PVIN can range from 4.5V to 17V. If using the VIN separately from
PVIN, the VIN pin must be between 4.5V and 17V, and the PVIN pin can range from as low as 1.6V to 17V. A
voltage divider connected to the EN pin can adjust the either input voltage UVLO appropriately. Adjusting the
input voltage UVLO on the PVIN pin helps to provide consistant power up behavior.

Voltage Reference

The voltage reference system produces a precise ± 1% voltage reference over temperature by scaling the output
of a temperature stable bandgap circuit.

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-

=

Vo Vref

R5 R6

Vref

TPS54620

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Adjusting the Output Voltage

The output voltage is set with a resistor divider from the output (VOUT) to the VSENSE pin. It is recommended to
use 1% tolerance or better divider resistors. Referring to the application schematic of Figure 34 , start with a 10
k Ω for R6 and use Equation 1 to calculate R5. To improve efficiency at light loads consider using larger value
resistors. If the values are too high the regulator is more susceptible to noise and voltage errors from the
VSENSE input current are noticeable.

Where Vref = 0.8V
The minimum output voltage and maximum output voltage can be limited by the minimum on time of the

high-side MOSFET and bootstrap voltage (BOOT-PH voltage) respectively. More discussions are located in

Minimum Output Voltage and Bootstrap Voltage (BOOT) and Low Dropout Operation .

Safe Start-up into Pre-Biased Outputs

The device has been designed to prevent the low-side MOSFET from diacharging a prebiased output. During
monotonic pre-biased startup, the low-side MOSFET is not allowed to sink current until the SS/TR pin voltage is
higher than 1.4V.

Error Amplifier

The device uses a transconductance error amplifier. The error amplifier compares the VSENSE pin voltage to the
lower of the SS/TR pin voltage or the internal 0.8V voltage reference. The transconductance of the error amplifier
is 1300 µ A/V during normal operation. The frequency compensation network is connected between the COMP
pin and ground.

........................................................................................................................................................................................................ SLVS949 – MAY 2009

(1)

Slope Compensation

The device adds a compensating ramp to the switch current signal. This slope compensation prevents
sub-harmonic oscillations. The available peak inductor current remains constant over the full duty cycle range.

Enable and Adjusting Under-Voltage Lockout

The EN pin provides electrical on/off control of the device. Once the EN pin voltage exceeds the threshold
voltage, the device starts operation. If the EN pin voltage is pulled below the threshold voltage, the regulator
stops switching and enters low Iq state.

The EN pin has an internal pullup current source, allowing the user to float the EN pin for enabling the device. If
an application requires controlling the EN pin, use open drain or open collector output logic to interface with the
pin.

The device implements internal UVLO circuitry on the VIN pin. The device is disabled when the VIN pin voltage
falls below the internal VIN UVLO threshold. The internal VIN UVLO threshold has a hysteresis of 150mV.

If an application requires either a higher UVLO threshold on the VIN pin or a secondary UVLO on the PVIN, in
split rail applications, then the EN pin can be configured as shown in Figure 17 , Figure 18 and Figure 19 . When
using the external UVLO function it is recommended to set the hysteresis to be greater than 500mV.

The EN pin has a small pull-up current Ip which sets the default state of the pin to enable when no external
components are connected. The pull-up current is also used to control the voltage hysteresis for the UVLO
function since it increases by Ihonce the EN pin crosses the enable threshold. The UVLO thresholds can be
calculated using Equation 2 and Equation 3 .

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EN

ip

i

h

VIN

TPS54620

R 1

R 2

EN

ip

i

h

PVIN

TPS54620

R 1

R 2

EN

ip

i

h

VIN

TPS54620

R 1

R 2

PVIN

1

æ ö

-

ç ÷
è ø

æ ö

- +

ç ÷
è ø

ENFALLING

START STOP

ENRISING

ENFALLING

p h

ENRISING

V

V V

V

R1 =

V

I I

V

( )

´

- + +

ENFALL ING

ST OP ENFALL ING p h

R1 V

R2 =

V V R1 I I

TPS54620

SLVS949 – MAY 2009 ........................................................................................................................................................................................................

Figure 17. Adjustable VIN Under Voltage Lock Out

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Where Ih= 3.4 µ A, Ip= 1.15 µ A, V

Adjustable Switching Frequency and Synchronization (RT/CLK)

The RT/CLK pin can be used to set the switching frequency of the device in two mode.

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Figure 18. Adjustable PVIN Under Voltage Lock Out, VIN ≥ 4.5V

Figure 19. Adjustable VIN and PVIN Under Voltage Lock Out

ENRISING

= 1.21 V, V

ENFALLING

= 1.17 V

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(2)

(3)