Texas Instruments TPS5450DDARG4, TPS5450 Datasheet

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VIN

NC

NC

ENA

GND

VSENSE

BOOT

PH

VIN VOUT

SimplifiedSchematic

EfficiencyvsOutputCurrent

50

55

60

65

70

75

80

85

90

95

100

I - Output Current - A

O

Efficiency-%

0 1 2 3 4 5 6

V =12V,
V =5V,
f =500kHz,
T =25°C

I

O

s

A

5-A, WIDE INPUT RANGE, STEP-DOWN SWIFT™ CONVERTER

FEATURES APPLICATIONS

• Wide Input Voltage Range: 5.5 V to 36 V

• Up to 5-A Continuous (6-A Peak) Output

Current

• High Efficiency Greater than 90% Enabled by
110-m Ω Integrated MOSFET Switch

• Wide Output Voltage Range: Adjustable Down
to 1.22 V with 1.5% Initial Accuracy

• Internal Compensation Minimizes External
Parts Count

• Fixed 500 kHz Switching Frequency for Small
Filter Size

• 18 µ A Shut Down Supply Current

• Improved Line Regulation and Transient

Response by Input Voltage Feed Forward

• System Protected by Overcurrent Limiting,
Overvoltage Protection and Thermal
Shutdown

• –40 ° C to 125 ° C Operating Junction
Temperature Range

• Available in Small Thermally Enhanced 8-Pin
SOIC PowerPAD™ Package

• For SWIFT™ Documentation, Application
Notes and Design Software, See the TI
Website at www.ti.com/swift

TPS5450

SLVS757 – MARCH 2007

• High Density Point-of-Load Regulators

• LCD Displays, Plasma Displays

• Battery Chargers

• 12-V/24-V Distributed Power Systems

DESCRIPTION

As a member of the SWIFT™ family of DC/DC
regulators, the TPS5450 is a high-output-current
PWM converter that integrates a low resistance high
side N-channel MOSFET. Included on the substrate
with the listed features are a high performance
voltage error amplifier that provides tight voltage
regulation accuracy under transient conditions; an
undervoltage-lockout circuit to prevent start-up until
the input voltage reaches 5.5 V; an internally set
slow-start circuit to limit inrush currents; and a
voltage feed-forward circuit to improve the transient
response. Using the ENA pin, shutdown supply
current is reduced to 18 µ A typically. Other features
include an active-high enable, overcurrent limiting,
overvoltage protection and thermal shutdown. To
reduce design complexity and external component
count, the TPS5450 feedback loop is internally
compensated.

The TPS5450 device is available in a thermally
enhanced, 8-pin SOIC PowerPAD™ package. TI
provides evaluation modules and software tool to aid
in achieving high-performance power supply designs
to meet aggressive equipment development cycles.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SWIFT, PowerPAD are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Copyright © 2007–, Texas Instruments Incorporated

www.ti.com

TPS5450

SLVS757 – MARCH 2007

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION

T

J

INPUT VOLTAGE OUTPUT VOLTAGE PACKAGE

–40 ° C to 125 ° C 5.5 V to 36 V Adjustable to 1.22 V Thermally Enhanced SOIC (DDA)

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com .

(2) The DDA package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS5450DDAR). See applications section

of data sheet for PowerPAD™ drawing and layout information.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

VIN –0.3 to 40

V

I

O

I

lkg

T
T

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

(2) All voltage values are with respect to network ground terminal.
(3) Approaching the absolute maximum rating for the VIN pin may cause the voltage on the PH pin to exceed the absolute maximum rating.

Input voltage range BOOT –0.3 to 50

I

PH (steady-state) –0.6 to 40
ENA –0.3 to 7 V
BOOT-PH 10
VSENSE –0.3 to 3

PH (transient < 10 ns) –1.2
Source current PH Internally Limited
Leakage current PH 10 µ A
Operating virtual junction temperature range –40 to 150 ° C

J

Storage temperature –65 to 150 ° C

stg

only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(1) (2)

(1)

VALUE UNIT

PART NUMBER

(2)

TPS5450DDA

(3)

(3)

DISSIPATION RATINGS

8 Pin DDA (4-layer board with solder)

(1) (2)

PACKAGE

(3)

THERMAL IMPEDANCE

JUNCTION-TO-AMBIENT

30 ° C/W

(1) Maximum power dissipation may be limited by overcurrent protection.
(2) Power rating at a specific ambient temperature TAshould be determined with a junction temperature of 125 ° C. This is the point where

distortion starts to substantially increase. Thermal management of the final PCB should strive to keep the junction temperature at or
below 125 ° C for best performance and long-term reliability. See Thermal Calculations in applications section of this data sheet for more
information.

(3) Test board conditions:

a. 2 in x 1.85 in, 4 layers, thickness: 0.062 inch (1,57 mm).
b. 2 oz. copper traces located on the top and bottom of the PCB.
c. 2 oz. copper ground planes on the 2 internal layers.
d. 4 thermal vias in the PowerPAD area under the device package.

RECOMMENDED OPERATING CONDITIONS

MIN NOM MAX UNIT

V
T

2

Input voltage range 5.5 36 V

I

Operating junction temperature –40 125 ° C

J

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ELECTRICAL CHARACTERISTICS

TJ= –40 ° C to 125 ° C, VIN = 5.5 V - 36 V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SUPPLY VOLTAGE (VIN PIN)

VSENSE = 2 V, Not switching,

I

Q

UNDERVOLTAGE LOCK OUT (UVLO)

VOLTAGE REFERENCE

OSCILLATOR

ENABLE (ENA PIN)

CURRENT LIMIT

THERMAL SHUTDOWN

OUTPUT MOSFET

r

DS(on)

Quiescent current

Start threshold voltage, UVLO 5.3 5.5 V
Hysteresis voltage, UVLO 330 mV

Voltage reference accuracy V

Internally set free-running frequency 400 500 600 kHz
Minimum controllable on time 150 200 ns
Maximum duty cycle 87 89 %

Start threshold voltage, ENA 1.3 V
Stop threshold voltage, ENA 0.5 V
Hysteresis voltage, ENA 450 mV
Internal slow-start time (0~100%) 6.6 8 10 ms

Current limit 6.0 7.5 9.0 A
Current limit hiccup time 13 16 20 ms

Thermal shutdown trip point 135 162 ° C
Thermal shutdown hysteresis 14 ° C

High-side power MOSFET switch m Ω

PH pin open
Shutdown, ENA = 0 V 18 50 µ A

TJ= 25 ° C 1.202 1.221 1.239
IO= 0 A – 5 A 1.196 1.221 1.245

VIN = 5.5 V 150

TPS5450

SLVS757 – MARCH 2007

3 4.4 mA

110 230

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1

2

3

4

8

7

6

5

PowerPAD

(Pin9)

BOOT

NC

NC

VSENSE

PH

VIN

GND

ENA

DDAPACKAGE

(TOPVIEW)

TPS5450

SLVS757 – MARCH 2007

PIN ASSIGNMENTS

TERMINAL FUNCTIONS

TERMINAL

NAME NO.

BOOT 1 Boost capacitor for the high-side FET gate driver. Connect 0.01 µ F low ESR capacitor from BOOT pin to PH pin.
NC 2, 3 Not connected internally.
VSENSE 4 Feedback voltage for the regulator. Connect to output voltage divider.
ENA 5 On/off control. Below 0.5 V, the device stops switching. Float the pin to enable.
GND 6 Ground. Connect to PowerPAD.

VIN 7
PH 8 Source of the high side power MOSFET. Connected to external inductor and diode.

PowerPAD 9 GND pin must be connected to the exposed pad for proper operation.

Input supply voltage. Bypass VIN pin to GND pin close to device package with a high quality, low ESR ceramic
capacitor.

DESCRIPTION

4

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2.5

2.75

3

3.25

3.5

−50 −25 0 25 50 75 100 125

T

J

−JunctionT emperature − °C

I

Q

−QuiescentCurrent

−mA

V =12V

I

460

470

480

490

500

510

520

530

−50 −25 0 25 50 75 100 125

f − OscillatorFrequency − kHz

T − JunctionTemperature − °C

1.210

1.215

1.220

1.225

1.230

-50 -25 0 25 50 75 100 125

T -JunctionTemperature-°C

J

V -VoltageReference-V

REF

5

10

15

20

25

0 5 10 15 20 25 30 35 40

T

J

=125

°C

T

J

=27°C

TJ=

– °40 C

ENA=0V

VI−InputV oltage −V

I

SD

−ShutdownCurrent

−

Aµ

7

7.5

8

8.5

9

−50 −25 0 25 50 75 100 125
T

J

− JunctionTemperature − °C

T

S

S

− InternalSlowStartT

ime − ms

80

90

100

110

120

130

140

150

160

170

180

−50 −25 0 25 50 75 100 125

mΩ

−OnResistance

−

r

DS(on)

TJ−JunctionTemperature − °C

VI=12V

TPS5450

SLVS757 – MARCH 2007

TYPICAL CHARACTERISTICS

OSCILLATOR FREQUENCY NON-SWITCHING QUIESCENT CURRENT

vs vs

JUNCTION TEMPERATURE JUNCTION TEMPERATURE

Figure 1. Figure 2.

SHUTDOWN QUIESCENT CURRENT VOLTAGE REFERENCE

vs vs

INPUT VOLTAGE JUNCTION TEMPERATURE

JUNCTION TEMPERATURE JUNCTION TEMPERATURE

Figure 3. Figure 4.

ON RESISTANCE INTERNAL SLOW START TIME

vs vs

Figure 5. Figure 6.

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7

7.25

7.50

7.75

8

-50 -25 0 25

50

75 100 125

T -JunctionTemperature-°C

J

MinimumDutyRatio-%

120

130

140

150

160

170

180

−50 −25 0 25 50 75 100 125
T

J

− JunctionTemperature − °C

MinimumControllableOnT

ime

− ns

TPS5450

SLVS757 – MARCH 2007

TYPICAL CHARACTERISTICS (continued)

MINIMUM CONTROLLABLE ON TIME MINIMUM CONTROLLABLE DUTY RATIO

vs vs

JUNCTION TEMPERATURE JUNCTION TEMPERATURE

Figure 7. Figure 8.

6

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FUNCTIONAL BLOCK DIAGRAM

VIN

UVLO

ENABLE

Thermal

Protection

Reference

Overcurrent

GateDrive

Oscillator

Ramp

Generator

VREF

PH

ENA

GND

BOOT

Z1

Z2

SHDN

SHDN

SHDN

SHDN

SHDN

SHDN

SHDN

SHDN

VIN

112.5%VREF

VSENSE

OVP

HICCUP

HICCUP

SHDN

NC

FeedForward

BOOT

NC

POWERPAD

VIN

VOUT

5 µA

1.221VBandgap
SlowStart

Boot

Regulator

Error

Amplifier

Gain=25

PWM

Comparator

Protection

Gate
Driver

Control

VSENSE

TPS5450

SLVS757 – MARCH 2007

APPLICATION INFORMATION

DETAILED DESCRIPTION

Oscillator Frequency

The internal free running oscillator sets the PWM switching frequency at 500 kHz. The 500 kHz switching
frequency allows less output inductance for the same output ripple requirement resulting in a smaller output
inductor.

Voltage Reference

The voltage reference system produces a precision reference signal by scaling the output of a temperature
stable bandgap circuit. The bandgap and scaling circuits are trimmed during production testing to an output of

1.221 V at room temperature.

Enable (ENA) and Internal Slow Start

The ENA pin provides electrical on/off control of the regulator. Once the ENA pin voltage exceeds the threshold
voltage, the regulator starts operation and the internal slow start begins to ramp. If the ENA pin voltage is pulled
below the threshold voltage, the regulator stops switching and the internal slow start resets. Connecting the pin
to ground or to any voltage less than 0.5 V will disable the regulator and activate the shutdown mode. The
quiescent current of the TPS5450 in shutdown mode is typically 18 µ A.

The ENA pin has an internal pullup current source, allowing the user to float the ENA pin. If an application
requires controlling the ENA pin, use open drain or open collector output logic to interface with the pin. To limit
the start-up inrush current, an internal slow-start circuit is used to ramp up the reference voltage from 0 V to its
final value, linearly. The internal slow start time is 8 ms typically.

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