Texas Instruments TPS54386EVM User Manual
Using the TPS54386EVM
User's Guide
March 2008 Power Supply MAN
SLUU286
Using the TPS54386EVM
User's Guide
Literature Number: SLUU286
March 2008
User's Guide
SLUU286 – March 2008
A 12-V Input, 5.0-V and 3.3-V Output, 2-A
Non-Synchronous Buck Converter
1 Introduction
The TPS54386EVM evaluation module (EVM) is a dual non-synchronous buck converter providing fixed
5.0-V and 3.3-V output at up to 2 A each from a 12-V input bus. The EVM is designed to start up from a
single supply, so no additional bias voltage is required for start-up. The module uses the TPS54386 Dual
Non-Synchronous Buck Converter with Integral High-Side FET.
1.1 Description
TPS54386EVM is designed to use a regulated 12-V (+10% / -20%) bus to produce two regulated power
rails, 5.0 V and 3.3 V at up to 2 A of load current each. TPS54386EVM is designed to demonstrate the
TPS54386 in a typical 12-V bus system while providing a number of test points to evaluate the
performance of the TPS54386 in a given application. The EVM can be modified to other input or output
voltages by changing some of the components.
1.2 Applications
• Non-Isolated Low Current Point of Load and Voltage Bus Converters
• Consumer Electronics
• LCD TV
• Computer Peripherals
• Digital Set Top Box
1.3 Features
• 12-V (+10% / -20%) Input Range
• 5.0-V and 3.3-V Fixed Output Voltage, Adjustable with Resistor Change
• 2-A
• 600-kHz Switching Frequency (fixed by TPS54386)
• Internal Switching MOSFET and External Rectifier Diode
• Double Sided 2 Active Layer PCB (all components on top side, test point signals routed on internal
• Active Converter Area Less than 1.8 Square Inches (0.89” x 1.97”)
• Convenient Test Points (used for probing switching waveforms and non-invasive loop response testing)
Steady State Output Current (3 A Peak)
DC
layers)
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TPS54386EVM Electrical Performance Specifications
2 TPS54386EVM Electrical Performance Specifications
SYMBOL PARAMETER MIN TYP MAX UNITS
Input Characterstics
V
IN
I
IN
V
IN_UVLO
Output Characterstics
V
OUT1
V
OUT2
V
OUT_ripple
I
OUT1
I
OUT2
I
OCP1
I
OCP2
Systems Characterstics
F
SW
η pk Peak efficiency VIN= nom - 90% η Full load efficiency VIN= nom, I
Top VIN= min to max, I
Input coltage 9.6 12 13.2 V
Input current VIN= nom, I
No load input current VIN= nom, I
Input UVLO I
Output voltage 1 VIN= nom, I
Output voltage 2 VIN= nom, I
Line regulation VIN= min to max - - 1%
Load regulation IOUT = min to max - - 1%
Output voltage ripple VIN= nom, I
Output current 1 VIN= min to max 0 2.0
Output current 2 VIN= min to max 0 2.0
Output over current
Channel 1
Output over current
Channel 2
Switching frequency 510 630 750 kHz
Operating temperature ° C
range
Table 1. Electrical Performance Specifications
OUT
OUT
= min to max 4.0 4.2 4.4 V
OUT
OUT
OUT
OUT
VIN= nom, V
VIN= nom, V
OUT
OUT
OUT
= max - 1.6 2.0 A
= 0 A - 12 20 mA
= nom 4.85 5.0 5.15
= nom 3.20 3.3 3.40
= max - - 30 mV
= V
= V
- 5% 3.1 3.7 4.5
OUT1
- 5% 3.1 3.7 4.5
OUT2
= max - 85% -
= min to max 0 25 60
OUT
V
pp
A
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+
Schematic
3 Schematic
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Note: For reference only, see Table 3 , List of Materials for specific values.
Figure 1. TPS54386EVM Schematic
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Schematic
3.1 Sequencing Jump (JP3)
The TPS54386EVM provides a 3-pin, 100-mil header and shunt for programming the TPS54386’s
sequencing function. Placing the JP3 shunt in the left position connects the sequence pin to BP and sets
the TPS54386 controller to sequence Channel 2 prior to Channel 1 when Enable 2 is activated. Placing
the JP3 shunt in the right position connects the sequence pin to GND and sets the TPS54386 converter to
sequence Channel 1 prior to Channel 1 when Enable 1 is activated. Removing the JP3 shunt disables
sequencing and allows Channel 1 and Channel 2 to be enabled independently.
3.2 Enable Jumpers (JP1 and JP2)
TPS54386EVM provides separate 3-pin, 100-mil headers and shunts for exercising the TPS54386 Enable
functions. When JP3 is removed placing the JP1 shunt in the left position connects EN1 to ground and
turns on Output 1 and placing the JP2 shunt in the left position connects EN2 to ground and turns on
Output 2.
When the JP3 shunt is in the LEFT position, placing the JP2 shunt in the left position connects EN2 to
ground and turns on first Output 2 and then Output 1.
When the JP3 shunt is in the RIGHT position, placing the JP1 shunt in the left position connects EN1 to
ground and turns on first Output 1 and then Output 2.
3.3 Test Point Descriptions
TEST POINT LABLE USE SECTION
TP1 VIN Monitor input voltage Section 3.3.1
TP2 GND Ground for input voltage Section 3.3.1
TP3 VOUT1 Monitor VOUT1 Voltage Section 3.3.2
TP4 GND Ground for VOUT1 voltage Section 3.3.2
TP5 GND Ground for Channel B loop monitoring Section 3.3.3
TP6 CHB Channel B for loop monitoring Section 3.3.3
TP7 GND Ground for Channel A loop monitoring Section 3.3.3
TP8 CHA Channel A for loop monitoring Section 3.3.3
TP9 SW1 Monitor switching node of Channel 1 Section 3.3.4
TP10 GND Ground for switch node of Channel 1 Section 3.3.4
TP11 IC_GND Monitor device ground Section 3.3.5
TP12 SW2 Monitor switching node of Channel 2 Section 3.3.6
TP13 GND Ground for switch node of Channel 2 Section 3.3.6
TP14 CHA Channel A for loop monitoring Section 3.3.7
TP15 GND Ground for Channel A loop monitoring Section 3.3.7
TP16 CHB Channel B for loop monitoring Section 3.3.7
TP17 GND Ground for Channel B loop monitoring Section 3.3.7
TP18 VOUT2 Monitor VOUT2 voltage Section 3.3.8
TP19 GND Ground for VOUT2 voltage Section 3.3.8
Table 2. Test Point Descriptions
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