Texas Instruments TPS54332DDAR Schematic [ru]

PH

VIN

GND

BOOT

VSENSE

COMP

SS

C

SS

D1

VIN

VOUT

EN

TPS54332

C

I

C

BOOT

L

O

C

O

Ren1

R

O2

C

1

C

2

R

3

Ren2

R

O1

60

65

70

75

80

85

90

95

100

0 0.5 1 1.5 2 2.5 3 3.5

I -OutputCurrent- A

O

Efficiency-%

V =2.5V

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V =5V

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SLVS875C –JANUARY 2009–REVISED NOVEMBER 2014

TPS54332 3.5-A, 28-V, 1-MHz, Step-Down DC-DC Converter With Eco-Mode™

1 Features 3 Description

1

• 3.5-V to 28-V Input Voltage Range

• Adjustable Output Voltage Down to 0.8 V

• Integrated 80-mΩ High-Side MOSFET Supports
up to 3.5-A Continuous Output Current

• High Efficiency at Light Loads With a Pulse­Skipping Eco-Mode™

• Fixed 1-MHz Switching Frequency

• Typical 1-μA Shutdown Quiescent Current

• Adjustable Slow-Start Limits Inrush Currents

• Programmable UVLO Threshold

• Overvoltage Transient Protection

• Cycle-by-Cycle Current Limit, Frequency Foldback
and Thermal Shutdown Protection

• Available in Thermally Enhanced 8-Pin SOIC
PowerPAD™ Package

• Supported by WEBENCH™ Tool
(http://www.ti.com/lsds/ti/analog/webench/overvie

w.page)

2 Applications

• Consumer Applications such as Set-Top Boxes,
CPE Equipment, LCD Displays, Peripherals, and
Battery Chargers

• Industrial and Car Audio Power Supplies

• 5-V, 12-V and 24-V Distributed Power Systems

The TPS54332 is a 28-V, 3.5-A non-synchronous
buck converter that integrates a low-R
MOSFET. To increase efficiency at light loads, a
pulse-skipping Eco-Mode feature is automatically
activated. Furthermore, the 1-μA shutdown supply
current allows the device to be used in battery­powered applications. Current mode control with
internal slope compensation simplifies the external
compensation calculations and reduces component
count while allowing the use of ceramic output
capacitors. A resistor divider programs the hysteresis
of the input undervoltage lockout. An overvoltage
transient protection circuit limits voltage overshoots
during start-up and transient conditions. A cycle-by­cycle current limit scheme, frequency foldback and
thermal shutdown protect the device and the load in
the event of an overload condition. The TPS54332 is
available in an 8-pin SOIC PowerPAD™ package.

Device Information

PART NUMBER PACKAGE BODY SIZE (NOM)

TPS54332 SO PowerPAD (8) 4.90 mm× 3.90 mm
(1) For all available packages, see the orderable addendum at

the end of the datasheet.

DS(on)

(1)

TPS54332

high-side

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

Simplified Schematic Efficiency

TPS54332

SLVS875C –JANUARY 2009–REVISED NOVEMBER 2014

www.ti.com

Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description............................................................. 1

4 Revision History..................................................... 2

5 Pin Configuration and Functions......................... 3

6 Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 Handling Ratings....................................................... 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics........................................... 6

6.6 Switching Characteristics.......................................... 6

6.7 Typical Characteristics: Characterization Curves ..... 7

6.8 Typical Characteristics: Supplemental Application

Curves........................................................................ 8

7 Detailed Description .............................................. 9

7.1 Overview ................................................................... 9

7.2 Functional Block Diagram....................................... 10

7.3 Feature Description................................................. 10

7.4 Device Functional Modes........................................ 13

8 Application and Implementation ........................ 14

8.1 Application Information............................................ 14

8.2 Typical Application.................................................. 14

9 Power Supply Recommendations...................... 24

10 Layout................................................................... 24

10.1 Layout Guidelines ................................................. 24

10.2 Layout Example .................................................... 25

10.3 Estimated Circuit Area .......................................... 25

10.4 Electromagnetic Interference (EMI)

Considerations......................................................... 25

11 Device and Documentation Support ................. 26

11.1 Device Support...................................................... 26

11.2 Trademarks........................................................... 26

11.3 Electrostatic Discharge Caution............................ 26

11.4 Glossary................................................................ 26

12 Mechanical, Packaging, and Orderable

Information........................................................... 26

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision B (Feburary 2013) to Revision C Page

• Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout

section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information

section ................................................................................................................................................................................... 1

Changes from Revision A (January 2013) to Revision B Page

• Deleted Swift™ from the data sheet title................................................................................................................................ 1

• Deleted feature Item: For SWIFT™ Documentation, See the TI Website at www.ti.com/swift.............................................. 1

2 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated

Product Folder Links: TPS54332

1

2

3

4

5

6

7

8BOOT

VIN

EN

SS

PH

GND

COMP

VSENSE

PowerPAD

(Pin 9)

DDA PACKAGE

(TOP VIEW)

TPS54332

www.ti.com

Changes from Original (March 2007) to Revision A Page

• Changed the ABSOLUTE MAXIMUM RATINGS table, Input Voltage - EN pin max value From: 5V to 6V.......................... 4

SLVS875C –JANUARY 2009–REVISED NOVEMBER 2014

5 Pin Configuration and Functions

Pin Functions

PIN I/O DESCRIPTION

NAME NO.

BOOT 1 O A 0.1-μF bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor falls below the

VIN 2 I Input supply voltage, 3.5 V to 28 V.
EN 3 I Enable pin. Pull below 1.25 V to disable. Float to enable. Programming the input undervoltage lockout with two

SS 4 I Slow-start pin. An external capacitor connected to this pin sets the output rise time.
VSENS 5 I Inverting node of the gm error amplifier.

E
COMP 6 O Error amplifier output, and input to the PWM comparator. Connect frequency compensation components to this

GND 7 - Ground.
PH 8 O The source of the internal high-side power MOSFET.
PowerP 9 - GND pin must be connected to the exposed pad for proper operation.

AD

minimum requirement, the high-side MOSFET is forced to switch off until the capacitor is refreshed.

resistors is recommended.

pin.

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SLVS875C –JANUARY 2009–REVISED NOVEMBER 2014

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

Input Voltage VIN –0.3 30 V

EN –0.3 6
BOOT 38
VSENSE –0.3 3
COMP –0.3 3
SS –0.3 3

Output Voltage BOOT-PH 8 V

PH –0.6 30
PH (10 ns transient from ground to negative peak) –5

Source Current EN 100 μA

BOOT 100 mA
VSENSE 10 μA
PH 9.25 A

Sink Current VIN 9.25 A

COMP 100 μA
SS 200

Operating Junction –40 150 °C
Temperature

(1) Stresses beyond those listed under Absolute Maxmium Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(1)

MIN MAX UNIT

6.2 Handling Ratings

MIN MAX UNIT

T

stg

V

(ESD)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

Storage Temperature –65 150 °C
Electrostatic Discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS- 2 kV

001, all pins
Charged device model (CDM), per JEDEC specification 500 V

JESD22-C101, all pins

(1)

(2)

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN MAX UNIT

Operating Input Voltage on (VIN pin) 3.5 28 V
Operating junction temperature, T

J

–40 150 °C

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TPS54332

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SLVS875C –JANUARY 2009–REVISED NOVEMBER 2014

6.4 Thermal Information

TPS54332

THERMAL METRIC

R

θJA

R

θJC(top)

R

θJB

ψ

JT

ψ

JB

R

θJC(bot)

Junction-to-ambient thermal resistance 48.7
Junction-to-case (top) thermal resistance 52.4
Junction-to-board thermal resistance 25.3
Junction-to-top characterization parameter 8.4
Junction-to-board characterization parameter 25.2
Junction-to-case (bottom) thermal resistance 2.3

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(1)

HSOP UNIT

8 PINS

°C/W

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SLVS875C –JANUARY 2009–REVISED NOVEMBER 2014

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6.5 Electrical Characteristics

TJ= –40°C to 150°C, VIN = 3.5 V to 28 V (unless otherwise noted)

DESCRIPTION TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN PIN)

Internal undervoltage lockout threshold Rising and Falling 3.5 V
Shutdown supply current EN = 0 V, VIN = 12 V, –40°C to 85°C 1 4 μA
Operating – non switching supply current VSENSE = 0.85 V 82 120 μA

ENABLE AND UVLO (EN PIN)

Enable threshold Rising and Falling 1.25 1.35 V
Input current Enable threshold – 50 mV -1 μA
Input current Enable threshold + 50 mV -4 μA

VOLTAGE REFERENCE

Voltage reference 0.772 0.8 0.828 V

HIGH-SIDE MOSFET

On resistance mΩ

ERROR AMPLIFIER

Error amplifier transconductance (gm) –2 μA < I
Error amplifier DC gain
Error amplifier unity gain bandwidth

(1)

(1)

Error amplifier source/sink current V
Switch current to COMP transconductance VIN = 12 V 12 A/V

PULSE-SKIPPING ECO-MODE

Pulse-skipping Eco-Mode switch current threshold 160 mA

CURRENT LIMIT

Current limit threshold VIN = 12 V 4.2 6.5 A

THERMAL SHUTDOWN

Thermal Shutdown 165 °C

SLOW-START (SS PIN)

Charge current V
SS to VSENSE matching V

(1) Specified by design

BOOT-PH = 3 V, VIN = 3.5 V 115 200
BOOT-PH = 6 V, VIN = 12 V 80 150

< 2 μA, V(COMP) = 1 V 92 μmhos

COMP

VSENSE = 0.8 V 800 V/V
5 pF capacitance from COMP to GND pins 2.7 MHz

= 1.0 V, 100-mV overdrive ±7 μA

(COMP)

= 0.4 V 2 μA

(SS)

= 0.4 V 10 mV

(SS)

6.6 Switching Characteristics

PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT

TPS54332 Switching Frequency VIN = 12 V, 25°C 800 1000 1200 kHz
Minimum controllable on time VIN = 12 V, 25°C 110 135 ns
Maximum controllable duty ratio

(1) Specified by design

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(1)

BOOT-PH = 6 V 90% 93%

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9

9.5

10

10.5

11

11.5

12

12.5

13

13.5

14

-50 -25 0 25 50 75 100 125 150

Dmin-MinimumControllableDutyRatio-%

T -JunctionTemperature-°C

J

VIN=12V

90

100

110

120

130

140

-50 -25 0 25 50 75 100 125 150

Tonmin-MinimumControllableOnTime-ns

T -JunctionTemperature-°C

J

VIN=12V

980

990

1000

1010

1020

-50 -25 0 25 50 75 100 125 150

T -JunctionTemperature-°C

J

fsw-OscillatorFrequency-kHz

VIN=12V

0.776

0.782

0.788

0.794

0.8

0.806

0.812

0.818

0.824

-50 -25 0 25 50 75 100 125 150

Vref-VoltageReference-V

T -JunctionTemperature-°C

J

VIN=12V

0

2

4

6

8

3

8

13

18

23

28

V -InputVoltage-V

I

Isd-ShutdownCurrent- Am

T =150°C

J

T =-40°C

J

T =25°C

J

EN=0V

T -JunctionTemperature-°C

J

Rdson-OnResistance-mW

60

70

80

90

100

110

120

-50 -25 0 25 50 75 100 125 150

VIN=12V

www.ti.com

6.7 Typical Characteristics: Characterization Curves

TPS54332

SLVS875C –JANUARY 2009–REVISED NOVEMBER 2014

Figure 1. On Resistance vs Junction Temperature

Figure 3. Switching Frequency vs Junction Temperature

Figure 2. Shutdown Quiescent Current vs Input Voltage

Figure 4. Voltage Reference vs Junction Temperature

Copyright © 2009–2014, Texas Instruments Incorporated Submit Documentation Feedback 7

Figure 5. Minimum Controllable on Time vs Junction

Temperature

Figure 6. Minimum Controllable Duty Ratio vs Junction

Temperature

Product Folder Links: TPS54332

3

8

13

18

23 28

0.75

1.25

1.75

2.25

2.75

3.25

3.75

I =3.5 A

O

V -OutputVoltage-V

O

V -InputVoltage-V

I

3 8 13 18

23 28

0

5

10

15

20

25

30

I =3.5 A

O

V -InputVoltage-V

I

V -OutputVoltage-V

O

1.9

1.95

2

2.05

2.1

-50 -25 0 25 50 75 100 125 150

I -SSChargeCurrent- A

SS

m

T -JunctionTemperature-°C

J

VIN=12V

3

3.5

4

4.5

5

5.5

6

6.5

7

3 8 13 18 23 28

V -InputVoltage-V

I

CurrentLimitThreshold- A

T =150°C

J

T =-40°C

J

T =25°C

J

TPS54332

SLVS875C –JANUARY 2009–REVISED NOVEMBER 2014

Typical Characteristics: Characterization Curves (continued)

www.ti.com

Figure 7. SS Charge Current vs Junction Temperature

Figure 8. Current Limit Threshold vs Input Voltage

6.8 Typical Characteristics: Supplemental Application Curves

Figure 9. Typical Minimum Output Voltage vs Input Voltage

Figure 10. Typical Maximum Output Voltage vs Input

Voltage

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SLVS875C –JANUARY 2009–REVISED NOVEMBER 2014

7 Detailed Description

7.1 Overview

The TPS54332 is a 28-V, 3.5-A, step-down (buck) converter with an integrated high-side, N-channel MOSFET.
To improve performance during line and load transients, the device implements a constant-frequency, current
mode control, which reduces output capacitance and simplifies external frequency compensation design. The
TPS54332 has a pre-set switching frequency of 1 MHz.

The TPS54332 needs a minimum input voltage of 3.5 V to operate normally. The EN pin has an internal pullup
current source that can be used to adjust the input voltage undervoltage lockout (UVLO) with two external
resistors. In addition, the pullup current provides a default condition when the EN pin is floating for the device to
operate. The operating current is 82 μA typically when not switching and under no load. When the device is
disabled, the supply current is 1 μA typically.

The integrated 80-mΩ high-side MOSFET allows for high-efficiency power supply designs with continuous output
currents up to 3.5 A.

The TPS54332 reduces the external component count by integrating the boot recharge diode. The bias voltage
for the integrated high-side MOSFET is supplied by an external capacitor on the BOOT to PH pin. The boot
capacitor voltage is monitored by an UVLO circuit and will turn the high-side MOSFET off when the voltage falls
below a preset threshold of 2.1 V typically. The output voltage can be stepped down to as low as the reference
voltage.

By adding an external capacitor, the slow-start time of the TPS54332 can be adjustable which enables flexible
output filter selection.

To improve the efficiency at light load conditions, the TPS54332 enters a special pulse-skipping Eco-Mode when
the peak inductor current drops below 160 mA typically.

The frequency foldback reduces the switching frequency during start-up and over current conditions to help
control the inductor current. The thermal shutdown gives the additional protection under fault conditions.

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Error

Amplifier

RQ

S

Boot

Charge

Boot

UVLO

Current

Sense

Oscillator

Frequency

Shift

Gate
Drive
Logic

Slope

Compensation

PWM
Latch

PWM

Comparator

ECO-MODE

MinimumClamp

™

Maximum

Clamp

Voltage

Reference

Discharge

Logic

VSENSE

COMP

PH

BOOT

VIN

GND

Thermal

Shutdown

EN

Enable

Comparator

Shutdown

Logic

Shutdown

Enable

Threshold

S

1.25V

0.8V

80mW

165C

2.1V
12 A/V

SS

Shutdown

VSENSE

1 Am

3 Am

gm=92 A/V

DCgain=800V/V

BW=2.7MHz

m

2kW

2 Am

TPS54332

SLVS875C –JANUARY 2009–REVISED NOVEMBER 2014

7.2 Functional Block Diagram

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7.3 Feature Description

7.3.1 Fixed Frequency PWM Control

The TPS54332 uses a fixed-frequency, peak-current mode control. The internal switching frequency of the
TPS54332 is fixed at 1 MHz.

7.3.2 Voltage Reference (V

ref

The voltage reference system produces a ±2% initial accuracy voltage reference (±3.5% over temperature) by
scaling the output of a temperature stable band-gap circuit. The typical voltage reference is designed at 0.8 V.

7.3.3 Bootstrap Voltage (BOOT)

The TPS54332 has an integrated boot regulator and requires a 0.1-μF ceramic capacitor between the BOOT and

)

PH pin to provide the gate drive voltage for the high-side MOSFET. A ceramic capacitor with an X7R or X5R
grade dielectric is recommended because of the stable characteristics over temperature and voltage. To improve
dropout, the TPS54332 is designed to operate at 100% duty cycle as long as the BOOT to PH pin voltage is
greater than 2.1 V typically.

7.3.4 Enable and Adjustable Input Undervoltage Lockout (VIN UVLO)

The EN pin has an internal pullup current source that provides the default condition of the TPS54332 operating
when the EN pin floats.

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( )

( ) ( )

( )

SS ref

SS

SS

C nF V V

T ms =

I A

´

m

EN

START EN

V

Ren2 =

V - V

+ 1 A

Ren1

m

START STOP

V - V

Ren1 =

3 Am

EN

1.25V

VIN

+

-

Ren1

Ren2

TPS54332

1 Am 3 Am

TPS54332

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SLVS875C –JANUARY 2009–REVISED NOVEMBER 2014

Feature Description (continued)

The TPS54332 is disabled when the VIN pin voltage falls below internal VIN UVLO threshold. TI recommends
using an external VIN UVLO to add Hysteresis unless VIN is greater than (V
with Hysteresis, use the external circuitry connected to the EN pin as shown in Figure 11. Once the EN pin
voltage exceeds 1.25 V, an additional 3 μA of hysteresis is added. Use Equation 1 and Equation 2 to calculate
the resistor values needed for the desired VIN UVLO threshold voltages. The V
voltage, the V
V

should always be greater than 3.5 V.

STOP

is the input stop threshold voltage and the VENis the enable threshold voltage of 1.25 V. The

STOP

Figure 11. Adjustable Input Undervoltage Lockout

+ 2 V). To adjust the VIN UVLO

OUT

is the input start threshold

START

(1)

(2)

7.3.5 Programmable Slow-Start Using SS Pin

TI highly recommends programing the slow-start time externally because no slow-start time is implemented
internally. The TPS54332 effectively uses the lower voltage of the internal voltage reference or the SS pin
voltage as the power supply’s reference voltage fed into the error amplifier and will regulate the output
accordingly. A capacitor (CSS) on the SS pin-to-ground implements a slow-start time. The TPS54332 has an
internal pullup current source of 2 μA that charges the external slow-start capacitor. The equation for the slow­start time (10% to 90%) is shown in Equation 3 . The V

is 0.8V and the ISScurrent is 2 μA.

ref

(3)

The slow-start time should be set between 1 ms to 10 ms to ensure good start-up behavior. The slow-start
capacitor should be no more than 27 nF.

If during normal operation, the input voltage drops below the VIN UVLO threshold, or the EN pin is pulled below

1.25 V, or a thermal shutdown event occurs, the TPS54332 stops switching.

7.3.6 Error Amplifier

The TPS54332 has a transconductance amplifier for the error amplifier. The error amplifier compares the
VSENSE voltage to the internal effective voltage reference presented at the input of the error amplifier. The
transconductance of the error amplifier is 92 μA/V during normal operation. Frequency compensation
components are connected between the COMP pin and ground.

7.3.7 Slope Compensation

In order to prevent the sub-harmonic oscillations when operating the device at duty cycles greater than 50%, the
TPS54332 adds a built-in slope compensation which is a compensating ramp to the switch current signal.

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