0
10
20
30
40
50
60
70
80
90
100
0.01 0.1 1 10
Efficiency-%
I -LoadCurrent- A
L
V =5V
I
V =12V
I
V =18V
I
V =24V
I
V =28V
I
PH
VIN
GND
BOOT
VSENSE
COMP
SS
C
SS
D1
VIN
VOUT
EN
TPS54331
C
I
C
BOOT
L
O
C
O
Ren1
R
O2
C
1
C
2
R
3
Ren2
R
O1
TPS54331
www.ti.com
....................................................................................................................................................................................................... SLVS839 – JULY 2008
3A, 28V INPUT, STEP DOWN SWIFT™ DC/DC CONVERTER WITH Eco-mode™
1
FEATURES
2
• 3.5V to 28V Input Voltage Range
• Adjustable Output Voltage Down to 0.8V
• Integrated 80 m Ω High Side MOSFET Supports
up to 3A Continuous Output Current
• High Efficiency at Light Loads with a Pulse
Skipping Eco-mode™
• Fixed 570kHz Switching Frequency
• Typical 1 µ A Shutdown Quiescent Current
• Adjustable Slow Start Limits Inrush Currents
• Programmable UVLO Threshold
• Overvoltage Transient Protection
• Cycle by Cycle Current Limit, Frequency Fold
Back and Thermal Shutdown Protection
• Available in Easy-to-Use SOIC8 Package
• Supported by SwitcherPro™ Software Tool
(http://focus.ti.com/docs/toolsw/folders/print/s
witcherpro.html )
• For SWIFT™ Documentation, See the TI
Website at www.ti.com/swift
DESCRIPTION
The TPS54331 is a 28-V, 3-A non-synchronous buck
converter that integrates a low Rds(on) high side
MOSFET. To increase efficiency at light loads, a
pulse skipping Eco-mode™ feature is automatically
activated. Furthermore, the 1 µ A shutdown supply
current allows the device to be used in battery
powered applications. Current mode control with
internal slope compensation simplifies the external
compensation calculations and reduces component
count while allowing the use of ceramic output
capacitors. A resistor divider programs the hysterisis
of the input under-voltage lockout. An overvoltage
transient protection circuit limits voltage overshoots
during startup and transient conditions. A cycle by
cycle current limit scheme, frequency fold back and
thermal shutdown protect the device and the load in
the event of an overload condition. The TPS54331 is
available in an 8-pin SOIC package that has been
internally optimized to improve thermal performance.
APPLICATIONS
• Consumer Applications such as Set-Top
Boxes, CPE Equipment, LCD Displays,
Peripherals, and Battery Chargers
• Industrial and Car Audio Power Supplies
• 5V, 12V and 24V Distributed Power Systems
1
2 SWIFT, Eco-mode, SwitcherPro are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SIMPLIFIED SCHEMATIC EFFICIENCY
Copyright © 2008, Texas Instruments Incorporated
TPS54331
SLVS839 – JULY 2008 .......................................................................................................................................................................................................
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
T
J
– 40 ° C to 150 ° C 8 pin SOIC 570 kHz TPS54331D
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) The D package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS54331DR). See applications section of
data sheet for layout information.
ABSOLUTE MAXIMUM RATINGS
PACKAGE SWITCHING FREQUENCY PART NUMBER
(1)
(1)
www.ti.com
(2)
over operating free-air temperature range (unless otherwise noted)
VALUE UNIT
VIN – 0.3 to 30
EN – 0.3 to 5
Input Voltage V
Output Voltage PH – 0.6 to 30 V
Source Current
Sink Current COMP 100
Electrostatic Discharge (HBM) 2 kV
Electrostatic Discharge (CDM) 500 V
Operating Junction Temperature – 40 to 150 ° C
Storage Temperature – 65 to 150 ° C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliabiltiy.
BOOT 38
VSENSE – 0.3 to 3
COMP – 0.3 to 3
SS – 0.3 to 3
BOOT-PH 8
PH (10 ns transient from ground to negtive peak) – 5
EN 100 µ A
BOOT 100 mA
VSENSE 10 µ A
PH 9 A
VIN 9 A
SS 200
µ A
PACKAGE DISSIPATION RATINGS
PACKAGE THERMAL IMPEDANCE JUNCTION TO PSEUDO THERMAL IMPEDANCE JUNCTION TO
SOIC8 100 ° C/W 5 ° C/W
(1) Maximum power dissipation may be limited by overcurrent protection
(2) Power rating at a specific ambient temperature TAshould be determined with a junction temperature of 150 ° C. This is the point where
distortion starts to substantially increase. Thermal management of the PCB should strive to keep the junction temperature at or below
150 ° C for best performance and long-term reliability. See power dissipation estimate in application section of this data sheet for more
information.
(3) Test board conditions:
a. 2 inches x 1.5 inches, 2 layers, thickness: 0.062 inch
b. 2-ounce copper traces located on the top and bottom of the PCB
c. 6 thermal vias located under the device package
2 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
(1) (2) (3)
AMBIENT TOP
Product Folder Link(s): TPS54331
TPS54331
www.ti.com
....................................................................................................................................................................................................... SLVS839 – JULY 2008
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN TYP MAX UNIT
Operating Input Voltage on (VIN pin) 3.5 28 V
Operating junction temperature, T
J
– 40 150 ° C
ELECTRICAL CHARACTERISTICS
TJ= – 40 ° C to 150 ° C, VIN = 3.5V to 28V (unless otherwise noted)
DESCRIPTION TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN PIN)
Internal undervoltage lockout threshold Rising and Falling 3.5 V
Shutdown supply current EN = 0V, VIN = 12V, 25 ° C 1 10 µ A
Operating – non switching supply current VSENSE = 0.85 V 110 190 µ A
ENABLE AND UVLO (EN PIN)
Enable threshold Rising and Falling 1.25 1.35 V
Input current Enable threshold – 50 mV 1 µ A
Input current Enable threshold + 50 mV 4 µ A
VOLTAGE REFERENCE
Voltage reference 0.772 0.8 0.828 V
HIGH-SIDE MOSFET
On resistance BOOT-PH = 3 V, VIN = 3.5 V 115 200 m Ω
BOOT-PH = 6 V, VIN = 12 V 80 150
ERROR AMPLIFIER
Error amplifier transconductance (gm) – 2 µ A < ICOMP < 2 µ A, V(COMP) = 1 V 92 µ mhos
Error amplifier DC gain
Error amplifier unity gain bandwidth
Error amplifier source/sink current V(COMP) = 1.0 V, 100 mV overdrive ± 7 µ A
Switch current to COMP transconductance VIN = 12 V 12 A/V
SWITCHING FREQUENCY
TPS54331 Switching Frequency VIN = 12V 400 570 740 kHz
Minimum controllable on time Measured at 90% to 90% of VIN, VIN = 12V 110 160 ns
Maximum controllable duty ratio
PULSE SKIPPING ECO-MODE™
Pulse skipping Eco-mode™ switch current threshold 160 mA
CURRENT LIMIT
Current limit threshold VIN = 12 V 3.5 5.8 A
THERMAL SHUTDOWN
Thermal Shutdown 165 ° C
SLOW START (SS PIN)
Charge current V(SS) = 0.4 V 2 µ A
SS to VSENSE matching V(SS) = 0.4 V 10 mV
(1) Specified by design
(1)
(1)
(1)
VSENSE = 0.8 V 800 V/V
5 pF capacitance from COMP to GND pins 2.7 MHz
BOOT-PH = 6 V 90 93 %
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): TPS54331
1
2
3
4
5
6
7
8
BOOT
VIN
EN
SS
PH
GND
COMP
VSENSE
TPS54331
SLVS839 – JULY 2008 .......................................................................................................................................................................................................
DEVICE INFORMATION
PIN ASSIGNMENTS
TERMINAL FUNCTIONS
TERMINAL DESCRIPTION
NAME NO.
BOOT 1 A 0.1 µ F bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor falls below the
minimum requirement, the high-side MOSFET is forced to switch off until the capacitor is refreshed.
VIN 2 Input supply voltage, 3.5 V to 28 V.
EN 3 Enable pin. Pull below 1.25V to disable. Float to enable. Programming the input undervoltage lockout with two
resistors is recommended.
SS 4 Slow start pin. An external capacitor connected to this pin sets the output rise time.
VSENSE 5 Inverting node of the gm error amplifier.
COMP 6 Error amplifier output, and input to the PWM comparator. Connect frequency compensation components to this pin.
GND 7 Ground.
PH 8 The source of the internal high-side power MOSFET.
www.ti.com
4 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS54331
Error
Amplifier
RQ
S
Boot
Charge
Boot
UVLO
Current
Sense
Oscillator
Frequency
Shift
Gate
Drive
Logic
Slope
Compensation
PWM
Latch
PWM
Comparator
ECO-MODE
MinimumClamp
™
Maximum
Clamp
Voltage
Reference
Discharge
Logic
VSENSE
COMP
PH
BOOT
VIN
GND
Thermal
Shutdown
EN
Enable
Comparator
Shutdown
Logic
Shutdown
Enable
Threshold
S
1.25V
0.8V
80mW
165C
2.1V
12 A/V
SS
Shutdown
VSENSE
1 Am
3 Am
gm=92 A/V
DCgain=800V/V
BW=2.7MHz
m
2kW
2 Am
60
65
70
75
80
85
90
95
100
105
110
-50 -25 0 25 50 75 100 125 150
T -JunctionTemperature-°C
J
Rdson-OnResistance-mW
VIN=12V
0
1
2
3
4
3 8 13 18 23 28
V -InputVoltage-V
I
Isd-ShutdownCurrent-
Am
EN=0V
T =150°C
J
T =25°C
J
T =-40°C
J
550
555
560
565
570
575
580
585
590
-50 -25 0 25 50 75 100 125 150
fsw-OscillatorFrequency-kHz
T -JunctionTemperature-°C
J
VIN=12V
TPS54331
www.ti.com
....................................................................................................................................................................................................... SLVS839 – JULY 2008
FUNCTIONAL BLOCK DIAGRAM
CHARACTERIZATION CURVES
ON RESISTANCE SHUTDOWN QUIESCENT CURRENT SWITCHING FREQUENCY
JUNCTION TEMPERATURE INPUT VOLTAGE JUNCTION TEMPERATURE
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 5
Figure 1. Figure 2. Figure 3.
TYPICAL CHARACTERISTICS
vs vs vs
Product Folder Link(s): TPS54331
0.7760
0.7820
0.7880
0.7940
0.8000
0.8060
0.8120
0.8180
0.8240
-50 -25 0 25 50 75 100 125 150
Vref-VoltageReference-V
T -JunctionTemperature-°C
J
5.50
5.75
6
6.25
6.50
6.75
7
7.25
7.50
-50 -25 0 25 50 75 100 125 150
MinimumControllableDutyRatio-%
T -JunctionTemperature-°C
J
VIN=12V
100
110
120
130
140
-50 -25 0 25 50 75 100 125 150
Tonmin-MinimumControllableOnTime-ns
T -JunctionTemperature-°C
J
VIN=12V
1.90
2
2.10
-50 -25 0 25 50 75 100 125 150
I
-SlowStartChargeCurrent- A
SS
m
T -JunctionTemperature-°C
J
3
4
5
6
3 8 13 18 23 28
V -InputVoltage-V
I
CurrentLimitThreshold-
A
T =150°C
J
T =25°C
J
T =-40°C
J
3 8 13 18 23 28
0.5
0.75
1
1.25
1.5
1.75
V
-OutputVoltage-V
O
V -InputVolatage-V
I
I =2 A
O
I =3 A
O
3 8 13 18 23 28
0
5
10
15
20
25
30
I =3 A
O
I =2 A
O
V -OutputVoltage-V
O
V -InputVoltage-V
I
25
50
75
100
125
150
0 0.2 0.4 0.6 0.8 1 1.2
P -PowerDissipation-W
D
T -JunctionTemperature-°C
J
TPS54331
SLVS839 – JULY 2008 .......................................................................................................................................................................................................
www.ti.com
TYPICAL CHARACTERISTICS (continued)
VOLTAGE REFERENCE TIME RATIO
vs vs vs
JUNCTION TEMPERATURE JUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 4. Figure 5. Figure 6.
SS CHARGE CURRENT CURRENT LIMIT THRESHOLD
JUNCTION TEMPERATURE INPUT VOLTAGE
MINIMUM CONTROLLABLE ON MINIMUM CONTROLLABLE DUTY
vs vs
SUPPLEMENTAL APPLICATION CURVES
TYPICAL MINIMUM OUTPUT TYPICAL MAXIMUM OUTPUT
6 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
VOLTAGE VOLTAGE MAXIMUM POWER DISSIPATION
INPUT VOLTAGE INPUT VOLTAGE JUNCTION TEMPERATURE
Figure 9. Figure 10. Figure 11.
Figure 7. Figure 8.
vs vs vs
Product Folder Link(s): TPS54331
TPS54331
www.ti.com
....................................................................................................................................................................................................... SLVS839 – JULY 2008
TYPICAL CHARACTERISTICS (continued)
OVERVIEW
The TPS54331 is a 28-V, 3-A, step-down (buck) converter with an integrated high-side n-channel MOSFET. To
improve performance during line and load transients, the device implements a constant frequency, current mode
control which reduces output capacitance and simplifies external frequency compensation design. The
TPS54331 has a pre-set switching frequency of 570kHz.
The TPS54331 needs a minimum input voltage of 3.5V to operate normally. The EN pin has an internal pull-up
current source that can be used to adjust the input voltage under-voltage lockout (UVLO) with two external
resistors. In addition, the pull-up current provides a default condition when the EN pin is floating for the device to
operate. The operating current is 110 µ A typically when not switching and under no load. When the device is
disabled, the supply current is 1 µ A typically.
The integrated 80 m Ω high-side MOSFET allows for high efficiency power supply designs with continuous output
currents up to 3A.
The TPS54331 reduces the external component count by integrating the boot recharge diode. The bias voltage
for the integrated high-side MOSFET is supplied by an external capacitor on the BOOT to PH pin. The boot
capacitor voltage is monitored by an UVLO circuit and will turn the high-side MOSFET off when the voltage falls
below a preset threshold of 2.1V typically. The output voltage can be stepped down to as low as the reference
voltage.
By adding an external capacitor, the slow start time of the TPS54331 can be adjustable which enables flexible
output filter selection.
To improve the efficiency at light load conditions, the TPS54331 enters a special pulse skipping Eco-mode
when the peak inductor current drops below 160mA typically.
The frequency foldback reduces the switching frequency during startup and over current conditions to help
control the inductor current. The thermal shut down gives the additional protection under fault conditions.
TM
DETAILED DESCRIPTION
FIXED FREQUENCY PWM CONTROL
The TPS54331 uses a fixed frequency, peak current mode control. The internal switching frequency of the
TPS54331 is fixed at 570kHz.
ECO-MODE
The TPS54331 is designed to operate in pulse skipping Eco-mode
efficiency. When the peak inductor current is lower than 160 mA typically, the COMP pin voltage falls to 0.5V
typically and the device enters Eco-mode
clamped at 0.5V internally which prevents the high side integrated MOSFET from switching. The peak inductor
current must rise above 160mA for the COMP pin voltage to rise above 0.5V and exit Eco-mode
integrated current comparator catches the peak inductor current only, the average load current entering
Eco-mode
TM
TM
. When the device is in Eco-mode
TM
varies with the applications and external output filters.
TM
at light load currents to boost light load
TM
, the COMP pin voltage is
TM
. Since the
VOLTAGE REFERENCE (Vref)
The voltage reference system produces a ± 2% initial accuracy voltage reference ( ± 3.5% over temperature) by
scaling the output of a temperature stable bandgap circuit. The typical voltage reference is designed at 0.8V.
BOOTSTRAP VOLTAGE (BOOT)
The TPS54331 has an integrated boot regulator and requires a 0.1 µ F ceramic capacitor between the BOOT and
PH pin to provide the gate drive voltage for the high-side MOSFET. A ceramic capacitor with an X7R or X5R
grade dielectric is recommended because of the stable characteristics over temperature and voltage. To improve
drop out, the TPS54331 is designed to operate at 100% duty cycle as long as the BOOT to PH pin voltage is
greater than 2.1V typically.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): TPS54331
EN
1.25V
VIN
+
-
Ren1
Ren2
TPS54331
1 Am 3 Am
START STOP
V - V
Ren1 =
3 Am
EN
START EN
V
Ren2 =
V - V
+ 1 A
Ren1
m
( )
( ) ( )
( )
SS ref
SS
SS
C nF V V
T ms =
I A´m
TPS54331
SLVS839 – JULY 2008 .......................................................................................................................................................................................................
www.ti.com
ENABLE AND ADJUSTABLE INPUT UNDER-VOLTAGE LOCKOUT (VIN UVLO)
The EN pin has an internal pull-up current source that provides the default condition of the TPS54331 operating
when the EN pin floats.
The TPS54331 is disabled when the VIN pin voltage falls below internal VIN UVLO threshold. It is recommended
to use an external VIN UVLO to add hysterisis unless VIN is greater than (VOUT + 2V). To adjust the VIN UVLO
with hysterisis, use the external circuitry connected to the EN pin as shown in Figure 12 . Once the EN pin
voltage exceeds 1.25V, an additional 3 µ A of hysteresis is added. Use Equation 1 and Equation 2 to calculate the
resistor values needed for the desired VIN UVLO threshold voltages. The V
voltage, the V
V
should always be greater than 3.5V.
STOP
is the input stop threshold voltage and the V
STOP
is the enable threshold voltage of 1.25V. The
EN
Figure 12. Adjustable Input Under-Voltage Lockout
START
is the input start threshold
PROGRAMMABLE SLOW START USING SS PIN
It is highly recommended to program the slow start time externally because no slow start time is implemented
internally. The TPS54331 effectively uses the lower voltage of the internal voltage reference or the SS pin
voltage as the power supply ’ s reference voltage fed into the error amplifier and will regulate the output
accordingly. A capacitor (Css) on the SS pin to ground implements a slow start time. The TPS54331 has an
internal pull-up current source of 2 µ A that charges the external slow start capacitor. The equation for the slow
start time (10% to 90%) is shown in Equation 3 . The Vref is 0.8V and the Iss current is 2 µ A.
The slow start time should be set between 1ms to 10ms to ensure good start-up behavior. The slow start
capacitor should be no more than 27nF.
If during normal operation, the input voltage drops below the VIN UVLO threshold, or the EN pin is pulled below
1.25V, or a thermal shutdown event occurs, the TPS54331 stops switching.
ERROR AMPLIFIER
The TPS54331 has a transconductance amplifier for the error amplifier. The error amplifier compares the
VSENSE voltage to the internal effective voltage reference presented at the input of the error amplifier. The
transconductance of the error amplifier is 92 µ A/V during normal operation. Frequency compensation
components are connected between the COMP pin and ground.
SLOPE COMPENSATION
In order to prevent the sub-harmonic oscillations when operating the device at duty cycles greater than 50%, the
TPS54331 adds a built-in slope compensation which is a compensating ramp to the switch current signal.
8 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS54331
(1)
(2)
(3)
TPS54331
www.ti.com
....................................................................................................................................................................................................... SLVS839 – JULY 2008
CURRENT MODE COMPENSATION DESIGN
To simplify design efforts using the TPS54331, the typical designs for common applications are listed in Table 1 .
For designs using ceramic output capacitors, the voltage ratings of ceramic output capacitors are recommended
to be at least twice of the output voltages. Advanced users may refer to the Step by Step Design Procedure in
the Application Information section for the detailed guidelines or use SwitcherPro™ Software tool
(http://focus.ti.com/docs/toolsw/folders/print/switcherpro.html ).
Table 1. Typical Designs (Referring to Simplified Schematic on page 1)
VIN VOUT F
(V) (V) (kHz) ( µ H) (k Ω ) (k Ω ) (pF) (pF) (k Ω )
12 5 570 6.8 Ceramic 33 µ Fx2 10 1.91 39 4700 49.9
12 3.3 570 6.8 Ceramic 47 µ Fx2 10 3.24 47 1000 29.4
12 1.8 570 4.7 Ceramic 100 µ F 10 8.06 68 5600 29.4
12 0.9 570 3.3 Ceramic 100 µ Fx2 10 80.6 56 5600 29.4
12 5 570 6.8 Aluminum 330 µ F/160 m Ω 10 1.91 68 120 29.4
12 3.3 570 6.8 Aluminum 470 µ F/160 m Ω 10 3.24 82 220 10
12 1.8 570 4.7 SP 100 µ F/15 m Ω 10 8.06 68 5600 29.4
12 0.9 570 3.3 SP 330 µ F/12 m Ω 10 80.6 100 1200 49.9
sw
L
o
C
o
R
R
O1
O2
C
C
2
1
R
3
OVERCURRENT PROTECTION AND FREQUENCY SHIFT
The TPS54331 implements current mode control that uses the COMP pin voltage to turn off the high-side
MOSFET on a cycle by cycle basis. Every cycle the switch current and the COMP pin voltage are compared;
when the peak inductor current intersects the COMP pin voltage, the high-side switch is turned off. During
overcurrent conditions that pull the output voltage low, the error amplifier responds by driving the COMP pin high,
causing the switch current to increase. The COMP pin has a maximum clamp internally, which limit the output
current.
The TPS54331 provides robust protection during short circuits. There is potential for overcurrent runaway in the
output inductor during a short circuit at the output. The TPS54331 solves this issue by increasing the off time
during short circuit conditions by lowering the switching frequency. The switching frequency is divided by 8, 4, 2,
and 1 as the voltage ramps from 0V to 0.8V on VSENSE pin. The relationship between the switching frequency
and the VSENSE pin voltage is shown in Table 2 .
Table 2. Switching Frequency Conditions
SWITCHING FREQUENCY VSENSE PIN VOLTAGE
570 kHz VSENSE ≥ 0.6 V
570 kHz / 2 0.6 V > VSENSE ≥ 0.4 V
570 kHz / 4 0.4 V > VSENSE ≥ 0.2 V
570 kHz / 8 0.2 V > VSENSE
OVERVOLTAGE TRANSIENT PROTECTION
The TPS54331 incorporates an overvoltage transient protection (OVTP) circuit to minimize output voltage
overshoot when recovering from output fault conditions or strong unload transients. The OVTP circuit includes an
overvoltage comparator to compare the VSENSE pin voltage and internal thresholds. When the VSENSE pin
voltage goes above 109% × Vref, the high-side MOSFET will be forced off. When the VSENSE pin voltage falls
below 107% × Vref, the high-side MOSFET will be enabled again.
THERMAL SHUTDOWN
The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 165 ° C.
The thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal
trip threshold. Once the die temperature decreases below 165 ° C, the device reinitiates the power up sequence.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): TPS54331
0.01 µF
4.7µF
4.7µF
Vin7V 28V –
0.01 μF
0.1 μF
332kΩ
68.1kΩ
47pF
0Ω
47 µF
Vout3.3V
IoutMax3 A
6.8 µH
10.2kΩ
3.24kΩ
29.4kΩ
1000pF
47 µF
TPS54331
SLVS839 – JULY 2008 .......................................................................................................................................................................................................
www.ti.com
APPLICATION INFORMATION
Figure 13. Typical Application Schematic
STEP BY STEP DESIGN PROCEDURE
The following design procedure can be used to select component values for the TPS54331. Alternately, the
SwitcherPro™Software may be used to generate a complete design. The SwitcherPro™ Software uses an
iterative design procedure and accesses a comprehensive database of components when generating a design.
This section presents a simplified discussion of the design process.
To begin the design process a few parameters must be decided upon. The designer needs to know the following:
• Input voltage range
• Output voltage
• Input ripple voltage
• Output ripple voltage
• Output current rating
• Operating frequency
For this design example, use the following as the input parameters
Table 3. Design Parameters
DESIGN PARAMETER EXAMPLE VALUE
Input voltage range 7 V to 28V
Output voltage 3.3 V
Input ripple voltage 300 mV
Output ripple voltage 30 mV
Output current rating 3 A
Operating Frequency 570 kHz
SWITCHING FREQUENCY
The switching frequency for the TPS54331 is fixed at 570 kHz.
10 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS54331
REF
OUT REF
R5 V
R6 =
V V´-
OUT REF
R5
V = V +1
R6
é ù
´
ê ú
ë û
( )
OUT(MAX)
IN OUT(MAX) MAX
BULK SW
I 0.25
V = + I ESR
C f
´
D ´
´
TPS54331
www.ti.com
....................................................................................................................................................................................................... SLVS839 – JULY 2008
OUTPUT VOLTAGE SET POINT
The output voltage of the TPS54331 is externally adjustable using a resistor divider network. In the application
circuit of Figure 13 , this divider network is comprised of R5 and R6. The relationship of the output voltage to the
resistor divider is given by Equation 4 and Equation 5 :
Choose R5 to be approximately 10.0 k Ω . Slightly increasing or decreasing R5 can result in closer output voltage
matching when using standard value resisitors. In this design, R4 = 10.2 k Ω and R = 3.24 k Ω , resulting in a 3.31
V output voltage. The zero ohm resistor R4 is provided as a convenient place to break the control loop for
stability testing.
INPUT CAPACITORS
The TPS54331 requires an input decoupling capacitor and depending on the application, a bulk input capacitor.
The typical recommended value for the decoupling capacitor is 10 µ F. A high-quality ceramic type X5R or X7R is
recommended. The voltage rating should be greater than the maximum input voltage. A smaller value may be
used as long as all other requirements are met; however 10 µ F has been shown to work well in a wide variety of
circuits. Additionally, some bulk capacitance may be needed, especially if the TPS54331 circuit is not located
within about 2 inches from the input voltage source. The value for this capacitor is not critical but should be rated
to handle the maximum input voltage including ripple voltage, and should filter the output so that input ripple
voltage is acceptable. For this design two 4.7 µ F capacitors are used for the input decoupling capacitor. They are
X7R dielectric rated for 50 V. The equivalent series resistance (ESR) is approximately 2m Ω , and the current
rating is 3 A. Additionally, a small 0.01 µ F capacitor is included for high frequency filtering.
This input ripple voltage can be approximated by Equation 6
(4)
(5)
Where I
and ESR
OUT(MAX)
MAX
is the maximum load current, f
is the maximum series resistance of the bulk capacitor.
is the switching frequency, C
SW
is the bulk capacitor value
BULK
The maximum RMS ripple current also needs to be checked. For worst case conditions, this can be
approximated by Equation 7
In this case, the input ripple voltage would be 143 mV and the RMS ripple current would be 1.5 A. It is also
important to note that the actual input voltage ripple will be greatly affected by parasitics associated with the
layout and the output impedance of the voltage source. The actual input voltage ripple for this circuit is shown in
Design Parameters and is larger than the calculated value. This measured value is still below the specified input
limit of 300 mV. The maximum voltage across the input capacitors would be VIN max plus Δ VIN/2. The chosen
bulk and bypass capacitors are each rated for 50 V and the ripple current capacity is greater than 3 A, both
providing ample margin. It is very important that the maximum ratings for voltage and current are not exceeded
under any circumstance.
OUTPUT FILTER COMPONENTS
Two components need to be selected for the output filter, L1 and C2. Since the TPS54331 is an externally
compensated device, a wide range of filter component types and values can be supported.
Inductor Selection
To calculate the minimum value of the output inductor, use Equation 8
(6)
(7)
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): TPS54331
( )
OUT(MAX) IN(MAX) OUT
MIN
IN(MAX) IND OUT SW
V V V
L =
V K I F
´ -
´ ´ ´
( )
2
OUT IN(MAX) OUT
2
L(RMS) OUT(MAX)
IN(MAX) OUT SW
V × V V
1
I = I + ×
12 V × L × F × 0.7
æ ö
-
ç ÷
ç ÷
è ø
( )
OUT IN(MAX) OUT
L(PK) OUT(MAX)
IN(MAX) OUT SW
V × V V
I = I +
1.4 V × L × F
-
´
) 2 /( 1
max _ min _ CO O O
F R C ´ ´ ´ = p
ú
û
ù
ê
ë
é
+
´ ´
-
=
E SR
O SW
LP P O PP
R
C F
D
I V
4
) 5. 0 (
TPS54331
SLVS839 – JULY 2008 .......................................................................................................................................................................................................
K
is a coefficient that represents the amount of inductor ripple current relative to the maximum output current.
IND
www.ti.com
In general, this value is at the discretion of the designer; however, the following guidelines may be used. For
designs using low ESR output capacitors such as ceramics, a value as high as K
using higher ESR output capacitors, K
For this design example, use K
IND
= 0.2 yields better results.
IND
= 0.3 and the minimum inductor value is calculated to be 5.7 µ H. For this
= 0.3 may be used. When
IND
design, a large value was chosen: 6.8 µ H.
For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded.
The RMS inductor current can be found from Equation 9
and the peak inductor current can be determined with Equation 10
For this design, the RMS inductor current is 3.02 A and the peak inductor current is 3.54 A. The chosen inductor
is a Sumida CDRH103-6R8 6.8 µ H. It has a saturation current rating of 3.84 A and an RMS current rating of 3.60
A, meeting these requirements. Smaller or larger inductor values can be used depending on the amount of ripple
current the designer wishes to allow so long as the other design requirements are met. Larger value inductors
will have lower ac current and result in lower output voltage ripple, while smaller inductor values will increase ac
curent and output voltage ripple. In general, inductor values for use with the TPS54331 are in the range of
6.8 µ H to 47 µ H.
(8)
(9)
(10)
Capacitor Selection
The important design factors for the output capacitor are dc voltage rating, ripple current rating, and equivalent
series resistance (ESR). The dc voltage and ripple current ratings cannot be exceeded. The ESR is important
because along with the inductor current it determines the amount of output ripple voltage. The actual value of the
output capacitor is not critical, but some practical limits do exist. Consider the relationship between the desired
closed loop crossover frequency of the design and LC corner frequency of the output filter. In general, it is
desirable to keep the closed loop crossover frequency at less than 1/5 of the switching frequency. With high
switching frequencies such as the 570-kHz frequency of this design, internal circuit limitations of the TPS54331
limit the practical maximum crossover frequency to about 25 kHz. In general, the the closed loop crossover
frequency should be higher than the corner frequency determined by the load impedance and the output
capacitor. This limits the minimum capacitor value for the output filter to:
Where R
is the output load impedance (V
O
O/IO
) and f
is the desired crossover frequency. For a desired
CO
maximum crossover of 25 kHz the minimum value for the output capacitor is around 5.8 µ F. This may not satisfy
the output ripple voltage requirement. The output ripple voltage can be estimated by:
Where N
is the number of output capacitors in parallel.
C
The maximum ESR of the output capacitor is determined by the amount of allowable output ripple as specified in
the initial design parameters. The output ripple voltage is the inductor ripple current times the ESR of the output
filter, so the maximum specified ESR as listed in the capacitor data sheet is given by Equation 13
(11)
(12)
12 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS54331
( )
12
OUT IN(MAX) OUT
COUT(RMS)
IN(MAX) OUT SW C
V × V V
1
I = ×
V × L × F × N
æ ö
-
ç ÷
ç ÷
è ø
( )
PO OO Z
V = 1/ 2 R Cp ´ ´ ´
( )
Z1 Z Z
F = 1/ 2 R Cp ´ ´ ´
( )
P1 Z P
F = 1/ 2 R Cp ´ ´ ´
( )
SENSE CO O
Gain = 20 log 2 R F Cp - ´ ´ ´ ´
TPS54331
www.ti.com
Where Δ V
....................................................................................................................................................................................................... SLVS839 – JULY 2008
is the desired peak-to-peak output ripple. For this design example, two 100- µ F ceramic output
p-p
capacitors are chosen for C2 and C10. These are TDK C3225X5R0J107M, rated at 6.3 V with a maximum ESR
of 2 m Ω and a ripple current rating in excess of 3 A. The calculated total RMS ripple current is 161 mA ( 80.6 mA
each) and the maximum total ESR required is 43 m Ω . These output capacitors exceed the requirements by a
wide margin and will result in a reliable, high-performance design. it is important to note that the actual
capacitance in circuit may be less than the catalog value when the output is operating at the desired output of
3.3 V The selected output capacitor must be rated for a voltage greater than the desired output voltage plus 1/2
the ripple voltage. Any derating amount must also be included. The maximum RMS ripple current in the output
capacitor is given by Design Parameters .
Other capacitor types work well with the TPS54331, depending on the needs of the application.
COMPENSATION COMPONENTS
The external compensation used with the TPS54331 allows for a wide range of output filter configurations. A
large range of capacitor values and types of dielectric are supported. The design example uses ceramic X5R
dielectric output capacitors, but other types are supported.
A Type II compensation scheme is recommended for the TPS54331. The compensation components are chosen
to set the desired closed loop cross over frequency and phase margin for output filter components. The type II
compensation has the following characteristics; a dc gain component, a low frequency pole, and a mid frequency
zero / pole pair.
The dc gain is determined by Equation 14 :
(13)
Where:
V
= 800
ggm
V
= 0.8 V
REF
The low-frequency pole is determined by Equation 15 :
The mid-frequency zero is determined by Equation 16 :
And, the mid-frequency pole is given by Equation 17 :
The first step is to choose the closed loop crossover frequency. In general, the closed-loop crossover frequency
should be less than 1/8 of the minimum operating frequency, but for the TPS54331it is recommended that the
maximum closed loop crossover frequency be not greater than 25 kHz. Next, the required gain and phase boost
of the crossover network needs to be calculated. By definition, the gain of the compensation network must be the
inverse of the gain of the modulator and output filter. For this design example, where the ESR zero is much
higher than the closed loop crossover frequency, the gain of the modulator and output filter can be approximated
by Equation 18 :
Where:
R
F
C
= 1 Ω /11
SENSE
= Closed-loop crossover frequency
CO
= Output capacitance
O
The phase loss is given by Equation 19 :
(14)
(15)
(16)
(17)
(18)
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): TPS54331
( ) ( )
CO ESR O CO O O
PL = tan 2 F R C tan 2 F R Ca ap p ´ ´ ´ ´ - ´ ´ ´ ´
÷
ø
ö
ç
è
æ
+ = deg 45
2
tan
PB
k
CO O O OA
Z
ICOMP ggm REF
2 × × F × V × C × R
R =
GM × V × V
p
TPS54331
SLVS839 – JULY 2008 .......................................................................................................................................................................................................
www.ti.com
Where:
R
= Equivalent series resistance of the output capacitor
ESR
R
= VO/I
O
O
The measured overall loop response for the circuit is given in Figure 20. Note that the actual closed loop
crossover frequency is higher than intended at about 25 kHz. This is primarily due to variation in the actual
values of the output filter components and tolerance variation of the internal feed-forward gain circuitry. Overall
the design has greater than 60 degrees of phase margin and will be completely stable over all combinations of
line and load variability.
Now that the phase loss is known the required amount of phase boost to meet the phase margin requirement
can be determined. The required phase boost is given by Equation 20 :
Where PM = the desired phase margin.
A zero / pole pair of the compensation network will be placed symmetrically around the intended closed loop
frequency to provide maximum phase boost at the crossover point. The amount of separation can be determined
by Equation 21 and the resultant zero and pole frequencies are given by Equation 22 and Equation 23
(19)
(20)
(21)
The low-frequency pole is set so that the gain at the crossover frequency is equal to the inverse of the gain of the
modulator and output filter. Due to the relationships established by the pole and zero relationships, the value of
R
can be derived directly by Equation 24 :
Z
Where:
V
= Output voltage
O
C
= Output capacitance
O
F
= Desired crossover frequency
CO
R
= 8 M Ω
OA
With R
GM
V
ggm
V
REF
COMP
= 800
= 0.8 V
known, C
Z
= 12 A/V
and C
Z
can be calculated using Equation 25 and Equation 26 :
P
(22)
(23)
(24)
(25)
For this design, the two 47- µ F output capacitors are used. For ceramic capacitors, the actual output capacitance
is less than the rated value when the capacitors have a dc bias voltage applied. This is the case in a dc/dc
converter. The actual output capacitance may be as low as 54 µ F. The combined ESR is approximately .001 Ω .
14 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS54331
(26)
-6 6
2 25000 3.3 54 10 8 10
Rz = = 29.2 k
12 800 0.8
p ´ ´ ´ ´ ´ ´ ´
W
´ ´
1
= = 928 pF
2 6010 29200
Cz
p ´ ´ ´
1
= = 51 pF
2 103900 29200
Cp
p ´ ´ ´
( )
( )
( )
Omax IN min O max DSo n max D O m ax L D
V = 0.91 × V I × R + V I × R V - - -
TPS54331
www.ti.com
....................................................................................................................................................................................................... SLVS839 – JULY 2008
Using Equation 18 and Equation 19 , the ouptut stage gain and phase loss are equivalent as:
Gain = – 2.26 dB
and
PL - – 83.52 degrees
For 70 degrees of phase margin, Equation 20 requires 63.52 degrees of phase boost.
Equation 21 , Equation 22 , and Equation 23 are used to find the zero and pole frequencies of:
F
= 5883 Hz
Z1
And
F
= 106200 Hz
P1
RZ, CZ, and C
are calculated using Equation 24 , Equation 25 , and Equation 26 :
P
Using standard values for R3, C6, and C7 in the application schematic of Figure 13 :
R3 = 29.4 k Ω
C6 = 1000 pF
C7 = 47 pF
(27)
(28)
(29)
BOOTSTRAP CAPACITOR
Every TPS54331 design requires a bootstrap capacitor, C4. The bootstrap capacitor must be 0.1 µ F. The
bootstrap capacitor is located between the PH pins and BOOT pin. The bootstrap capacitor should be a
high-quality ceramic type with X7R or X5R grade dielectric for temperature stability.
CATCH DIODE
The TPS54331 is designed to operate using an external catch diode between PH and GND. The selected diode
must meet the absolute maximum ratings for the application: Reverse voltage must be higher than the maximum
voltage at the PH pin, which is VINMAX + 0.5 V. Peak current must be greater than IOUTMAX plus on half the
peak to peak inductor current. Forward voltage drop should be small for higher efficiencies. It is important to note
that the catch diode conduction time is typically longer than the high-side FET on time, so attention paid to diode
parameters can make a marked improvement in overall efficiency. Additionally, check that the device chosen is
capable of dissipating the power losses. For this design, a Diodes, Inc. B340A is chosen, with a reverse voltage
of 40 V, forward current of 3 A, and a forward voltage drop of 0.5 V.
OUTPUT VOLTAGE LIMITATIONS
Due to the internal design of the TPS54331, there are both upper and lower output voltage limits for any given
input voltage. The upper limit of the output voltage set point is constrained by the maximum duty cycle of 91%
and is given by Equation 30 :
Where:
V
I
V
R
= Minimum input voltage
IN min
= Maximum load current
O max
= Catch diode forward voltage
D
= Output inductor series resistance
L
(30)
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): TPS54331
( )
( )
( )
Omin IN max Omin D O min L D
V = 0.118 × V I × Rin + V I × R V - - -
TPS54331
SLVS839 – JULY 2008 .......................................................................................................................................................................................................
www.ti.com
The equation assumes maximum on resistance for the internal high-side FET.
The lower limit is constrained by the minimum controllable on time which may be as high as 160 ns. The
approximate minimum output voltage for a given input voltage and minimum load current is given by Equation 31 :
(31)
Where:
V
I
O min
V
R
= Maximum input voltage
IN max
= Minimum load current
= Catch diode forward voltage
D
= Output inductor series resistance
L
This equation assumes nominal on-resistance for the high-side FET and accounts for worst case variation of
operating frequency set point. Any design operating near the operational limits of the device should be carefully
checked to assure proper functionality.
POWER DISSIPATION ESTIMATE
The following formulas show how to estimate the device power dissipation under continuous conduction mode
operations. They should not be used if the device is working in the discontinuous conduction mode (DCM) or
pulse skipping Eco-mode
The device power dissipation includes:
1) Conduction loss: Pcon = IOUT
2) Switching loss: Psw = 0.5 x 10
3) Gate charge loss: Pgc = 22.8 x 10
4) Quiescent current loss: Pq = 0.11 x 10
Where:
IOUT is the output current (A).
Rds(on) is the on-resistance of the high-side MOSFET ( Ω ).
VOUT is the output voltage (V).
VIN is the input voltage (V).
Fsw is the switching frequency (Hz).
So
Ptot = Pcon + Psw + Pgc + Pq
For given T
For given T
, TJ= TA+ Rth x Ptot.
A
= 150 ° C, T
JMAX
Where:
Ptot is the total device power dissipation (W).
TAis the ambient temperature ( ° C).
TJis the junction temperature ( ° C) .
Rth is the thermal resistance of the package ( ° C/W).
T
is maximum junction temperature ( ° C).
JMAX
T
is maximum ambient temperature ( ° C).
AMAX
TM
.
2
x Rds(on) x VOUT/VIN
-9
= T
AMAX
2
x VIN
x IOUT x Fsw
-9
x Fsw
-3
x VIN
– Rth x Ptot.
JMAX
16 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS54331
BOOT
VSENSE
PH
VIN
GND
EN
Vout
PH
Vin
TOPSIDE
GROUND
AREA
OUTPUT
INDUCTOR
OUTPUT
FILTER
CAPACITOR
BOOT
CAPACITOR
INPUT
BYPASS
CAPACITOR
CATCH
DIODE
SignalVIA
RouteBOOT CAPACITOR
traceonotherlayertoprovide
widepathfortopsideground
RESISTOR
DIVIDER
Feedback Trace
COMP
SS
COMPENSATION
NETWORK
ThermalVIA
SLOWSTART
CAPACITOR
UVLO
RESISTOR
DIVIDER
TPS54331
www.ti.com
....................................................................................................................................................................................................... SLVS839 – JULY 2008
PCB LAYOUT
The VIN pin should be bypassed to ground with a low ESR ceramic bypass capacitor. Care should be taken to
minimize the loop area formed by the bypass capacitor connections, the VIN pin, and the anode of the catch
diode. The typical recommended bypass capacitance is 10- µ F ceramic with a X5R or X7R dielectric and the
optimum placement is closest to the VIN pins and the source of the anode of the catch diode. See Figure 14 for
a PCB layout example. The GND D pin should be tied to the PCB ground plane at the pin of the IC. The source
of the low-side MOSFET should be connected directly to the top side PCB ground area used to tie together the
ground sides of the input and output capacitors as well as the anode of the catch diode. The PH pin should be
routed to the cathode of the catch diode and to the output inductor. Since the PH connection is the switching
node, the catch diode and output inductor should be located very close to the PH pins, and the area of the PCB
conductor minimized to prevent excessive capacitive coupling. For operation at full rated load, the top side
ground area must provide adequate heat dissipating area. The TPS54331 uses a fused lead frame so that the
GND pin acts as a conductive path for heat dissipation from the die. Many applications have larger areas of
internal or back side ground plane available, and the top side ground area can be connected to these areas
using multiple vias under or adjacent to the device to help dissipate heat. The additional external components
can be placed approximately as shown. It may be possible to obtain acceptable performance with alternate
layout schemes, however this layout has been shown to produce good results and is intended as a guideline.
ELECTROMAGNETIC INTERFERENCE (EMI) CONSIDERATIONS
As EMI becomes a rising concern in more and more applications, the internal design of the TPS54331 takes
measures to reduce the EMI. The high-side MOSFET gate drive is designed to reduce the PH pin voltage
ringing. The internal IC rails are isolated to decrease the noise sensitivity. A package bond wire scheme is used
to lower the parasitics effects.
To achieve the best EMI performance, external component selection and board layout are equally important.
Follow the Step by Step Design Procedure above to prevent potential EMI issues.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 17
Figure 14. TPS54331 Board Layout
Product Folder Link(s): TPS54331
0
10
20
30
40
50
60
70
80
90
100
0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2
I -OutputCurrent- A
O
Efficiency-%
V =7V
IN
V =14V
IN
V =21V
IN
V =28V
IN
0
10
20
30
40
50
60
70
80
90
100
0 0.5
1
1.5
2
2.5
3
I -OutputCurrent- A
O
Efficiency-%
V =7V
IN
V =14V
IN
V =21V
IN
V =28V
IN
0.9985
0.999
0.9995
1
1.0005
1.001
1.0015
1.002
1.0025
1.003
1.0035
1.004
0 0.5 1 1.5 2 2.5 3 3.5
V =14V
IN
V =21V
IN
V =28V
IN
V =7V
IN
I -OutputCurrent- A
O
OutputRegulation-%
OutputRegulation-%
3.28
3.29
3.3
3.31
3.32
3.33
3.34
3.35
3.36
3.37
3.38
0 5 10 15 20 25 30
V -InputVoltage-V
I
I =0 A
O
I =1.5 A
O
I =3 A
O
TPS54331
SLVS839 – JULY 2008 .......................................................................................................................................................................................................
APPLICATION CURVES
www.ti.com
Figure 15. TPS54331 Efficiency Figure 16. TPS54331 Low Current Efficiency
Figure 17. TPS54331 Load Regulation Figure 18. TPS54331 Line Regulation
18 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS54331
-30
-20
-10
0
10
20
30
40
50
60
70
f-Frequency-Hz
-90
-60
-30
0
30
60
90
120
150
180
210
Phase-deg
10 100
1k 10k
100k
1M
Gain-dB
V
OUT
OutputCurrent
t-Time-200 s/divm
V
OUT
PH
t-Time-1 s/divm
V
IN
PH
t-Time-1 s/divm
TPS54331
www.ti.com
....................................................................................................................................................................................................... SLVS839 – JULY 2008
Figure 19. TPS54331 Transient Response Figure 20. TPS54331 Loop Response
Figure 21. TPS54331 Output Ripple Figure 22. TPS54331 Input Ripple
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): TPS54331
V
IN
V
OUT
t-Time-5ms/div
ENA
V
OUT
t-Time-5ms/div
TPS54331
SLVS839 – JULY 2008 .......................................................................................................................................................................................................
www.ti.com
Figure 23. TPS54331 Start Up Figure 24. TPS54331 Start-up Relative to Enable
20 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS54331
PACKAGE MATERIALS INFORMATION
www.ti.com
TAPE AND REEL INFORMATION
29-Jul-2008
*All dimensions are nominal
Device Package
TPS54331DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
Type
Package
Drawing
Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm)W(mm)
Pin1
Quadrant
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Jul-2008
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS54331DR SOIC D 8 2500 346.0 346.0 29.0
Pack Materials-Page 2
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