TEXAS INSTRUMENTS TPS54319 Technical data

PH

VIN

POWERPAD

BOOT

VSENSE

COMP

TPS54319

EN

RT /CLK

SS/TR

PWRGD

C

ss

R

T

R

3

C

1

C

BOOT

C

O

L

O

R

1

R

2

C

I

VOUT

VIN

AGND

GND

40

50

60

70

80

90

0

10

20

30

100

Efficiency - %

0 0.5 2 2.5 3

Output Current - A

1 1.5

5 Vin, 1.8 Vout

3.3 Vin,1.8 Vout

TPS54319

www.ti.com

2.95-V to 6-V Input, 3-A Output, 2-MHz, Synchronous Step-Down
Switcher With Integrated FETs ( SWIFT™)

Check for Samples: TPS54319

1

FEATURES

2

• Two 45-mΩ (typical) MOSFETs for High
Efficiency at 3-A Loads

• 300kHz to 2MHz Switching Frequency

• 0.8 V ± 3.0% Voltage Reference Over
Temperature (0°C to 85°C)

• Synchronizes to External Clock

• Adjustable Slow Start/Sequencing

• UV and OV Power Good Output

• –40°C to 150°C Operating Junction
Temperature Range

• Thermally Enhanced 3mm × 3mm 16-pin QFN

• Pin Compatible to TPS54318

APPLICATIONS

• Low-Voltage, High-Density Power Systems

• Point-of-Load Regulation for Consumer
Applications such as Set Top Boxes, LCD
Displays, CPE Equipment

SIMPLIFIED SCHEMATIC

vertical spacer
vertical spacer

SLVSA83 –JUNE 2010

DESCRIPTION

The TPS54319 device is a full featured 6 V, 3 A,
synchronous step down current mode converter with
two integrated MOSFETs.

The TPS54319 enables small designs by integrating
the MOSFETs, implementing current mode control to
reduce external component count, reducing inductor
size by enabling up to 2 MHz switching frequency,
and minimizing the IC footprint with a small 3mm x
3mm thermally enhanced QFN package.

The TPS54319 provides accurate regulation for a
variety of loads with an accurate ±3.0% Voltage
Reference (VREF) over temperature.

Efficiency is maximized through the integrated 45mΩ
MOSFETs and 360mA typical supply current. Using
the enable pin, shutdown supply current is reduced to
2 µA by entering a shutdown mode.

Under voltage lockout is internally set at 2.6 V, but
can be increased by programming the threshold with
a resistor network on the enable pin. The output
voltage startup ramp is controlled by the slow start
pin. An open drain power good signal indicates the
output is within 93% to 107% of its nominal voltage.

Frequency fold back and thermal shutdown protects
the device during an over-current condition.

The TPS54319 is supported in the SwitcherPro™
Software Tool at www.ti.com/switcherpro.

For more SWIFTTMdocumentation, see the TI
website at www.ti.com/swift.

1

2SWIFT, SwitcherPro are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright © 2010, Texas Instruments Incorporated

TPS54319

SLVSA83 –JUNE 2010

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION

T

J

PACKAGE PART NUMBER

(1)

–40°C to 150°C 3 × 3 mm QFN TPS54319RTE

(1) For the most current package and ordering information, see the Package Option Addendum at the end

of this document, or see the TI website at www.ti.com

ABSOLUTE MAXIMUM RATINGS

(1)

VALUE UNIT

MIN MAX

Input voltage VIN –0.3 7

EN –0.3 7
BOOT PH + 7
VSENSE –0.3 3
COMP –0.3 3

V

PWRGD –0.3 7
SS/TR –0.3 3
RT/CLK –0.3 6

Output voltage BOOT-PH 7

PH –0.6 7 V
PH 10 ns Transient –2 10

Source current EN 100 µA

RT/CLK 100 µA

Sink current COMP 100 µA

PWRGD 10 mA
SS/TR 100 µA

Electrostatic discharge (HBM) QSS 009-105 (JESD22-A114A)

(2)

1 kV
Electrostatic discharge (CDM) QSS 009-147 (JESD22-C101B.01) 500 V
Temperature T

j

T

stg

–40 150 °C
–65 150 °C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under ELECTRICAL
SPECIFICATIONS is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin. The machine model is a 200-pF

capacitor discharged directly into each pin.

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TPS54319

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SLVSA83 –JUNE 2010

THERMAL INFORMATION

(1)(2)

(3)

q

JA

q

JA

y

JT

y

JB

q

JC(top)

q

JC(bottom)

q

JB

THERMAL METRIC

Junction-to-ambient thermal resistance (standard board) 51.7
Junction-to-ambient thermal resistance (custom board)
Junction-to-top characterization parameter 0.8
Junction-to-board characterization parameter 19.2 °C/W
Junction-to-case(top) thermal resistance 69.3
Junction-to-case(bottom) thermal resistance 6.2
Junction-to-board thermal resistance 22

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) Power rating at a specific ambient temperature TAshould be determined with a junction temperature of 150°C. This is the point where

distortion starts to substantially increase. See power dissipation estimate in application section of this data sheet for more information.

(3) Test boards conditions:

(a) 2 inches x 2 inches, 4 layers, thickness: 0.062 inch
(b) 2 oz. copper traces located on the top of the PCB
(c) 2 oz. copper ground planes on the 2 internal layers and bottom layer
(d) 4 thermal vias (10mil) located under the device package

TPS54319

RTE (16-PINS)

37.0

UNITS

ELECTRICAL CHARACTERISTICS

TJ= –40°C to 150°C, VIN = 2.95 to 6 V (unless otherwise noted)

DESCRIPTION CONDITIONS MIN TYP MAX UNIT

SUPPLY VOLTAGE (VIN PIN)

Operating input voltage 2.95 6 V
Internal under voltage lockout threshold 2.6 2.8 V
Shutdown supply current EN = 0 V, 25°C, 2.95 V ≤ VIN ≤ 6 V 2 5 mA
Quiescent Current - I

q

ENABLE AND UVLO (EN PIN)

Enable threshold Rising 1.25 V

Input current mA

VOLTAGE REFERENCE (VSENSE PIN)

Voltage Reference 2.95 V ≤ VIN ≤ 6 V, 0°C <TJ< 85°C 0.802 0.827 0.852 V

MOSFET

High side switch resistance mΩ

Low side switch resistance mΩ

ERROR AMPLIFIER

Input current 7 nA
Error amplifier transconductance (gm) –2 mA < I(COMP) < 2 mA, V(COMP) = 1 V 245 mmhos
Error amplifier transconductance (gm) during –2 mA < I(COMP) < 2 mA, V(COMP) = 1 V, 79 mmhos

slow start Vsense = 0.4 V
Error amplifier source/sink V(COMP) = 1 V, 100 mV overdrive +20 mA

COMP to Iswitch gm 18 A/V

CURRENT LIMIT

Current limit threshold 3V 4.2 6.6 A

THERMAL SHUTDOWN

Thermal Shutdown 165 °C
Hysteresis 15 °C

VSENSE = 0.9 V, VIN = 5 V, 25°C, RT = 400 kΩ 360 575 mA

Falling 1.18
Enable threshold + 50 mV –4.6
Enable threshold – 50 mV –1.2

BOOT-PH= 5 V 45 81
BOOT-PH= 2.95 V 64 110
VIN= 5 V 42 81
VIN= 2.95 V 59 110

–20

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SLVSA83 –JUNE 2010

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ELECTRICAL CHARACTERISTICS (continued)

TJ= –40°C to 150°C, VIN = 2.95 to 6 V (unless otherwise noted)

DESCRIPTION CONDITIONS MIN TYP MAX UNIT

TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)

Switching frequency range using RT mode 300 2000 kHz
Switching frequency Rt = 400 kΩ 400 500 600 kHz
Switching frequency range using CLK mode 300 2000 kHz
Minimum CLK pulse width 75 ns
RT/CLK voltage R(RT/CLK)= 400kΩ 0.5 V
RT/CLK high threshold 1.6 2.2 V
RT/CLK low threshold 0.4 0.6 V
RT/CLK falling edge to PH rising edge delay Measure at 500 kHz with RT resistor in series 90 ns
PLL lock in time Measure at 500 kHz 14 ms

PH (PH PIN)

Minimum On time Measured at 50% points on PH, IOUT = 3 A 65

Measured at 50% points on PH, VIN = 5 V, 120
IOUT = 0 A

Minimum Off time Prior to skipping off pulses, BOOT-PH = 2.95 V, 60 ns

Rise Time 2.5
Fall Time 2

BOOT (BOOT PIN)

BOOT Charge Resistance VIN = 5 V 16 Ω
BOOT-PH UVLO VIN = 2.95 V 2.2 V

SLOW START AND TRACKING (SS/TR PIN)

Charge Current V(SS/TR) = 0.4 V 2.2 mA
SS/TR to VSENSE matching V(SS/TR) = 0.4 V 35 mV
SS/TR to reference crossover 98% normal 1.1 V
SS/TR discharge voltage (Overload) VSENSE = 0 V 46 mV
SS/TR discharge current (Overload) VSENSE = 0 V, V(SS/TR) = 0.4 V 325 µA

POWER GOOD (PWRGD PIN)

VSENSE threshold

Hysteresis VSENSE falling 2 % Vref
Output high leakage VSENSE = VREF, V(PWRGD) = 5.5 V 2 nA
On resistance 100 200 Ω
Output low I(PWRGD) = 3.0 mA 0.3 0.6 V
Minimum VIN for valid output V(PWRGD) < 0.5 V at 100 mA 1.2 1.6 V

IOUT = 3 A

VIN = 5 V, 3 A V/ns

VSENSE falling (Fault) 91 % Vref
VSENSE rising (Good) 93 % Vref
VSENSE rising (Fault) 107 % Vref
VSENSE falling (Good) 105 % Vref

ns

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Product Folder Link(s): TPS54319

PWRGD

BOOT

PH

RT/CLK

EN

AGND

VIN

VSENSE

COMP

15 14 13

GND

12

11

10

9

8

765

16

GND

VIN

VIN

PH

PH

1

2

3

4

SS/TR

PowerPAD

(17)

QFN16

RTE PACKAGE

(TOP VIEW)

TPS54319

www.ti.com

PIN CONFIGURATION

SLVSA83 –JUNE 2010

DEVICE INFORMATION

PIN FUNCTIONS

PIN

NAME NO.

AGND 5 Analog Ground should be electrically connected to GND close to the device.
BOOT 13 A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the minimum

required by the BOOT UVLO, the output is forced to switch off until the capacitor is refreshed.

COMP 7 Error amplifier output, and input to the output switch current comparator. Connect frequency compensation

components to this pin.

EN 15 Enable pin, internal pull-up current source. Pull below 1.2 V to disable. Float to enable. Can be used to set the

on/off threshold (adjust UVLO) with two additional resistors.
GND 3, 4 Power Ground. This pin should be electrically connected directly to the power pad under the IC.
PH 10, 11, The source of the internal high side power MOSFET, and drain of the internal low side (synchronous) rectifier

12 MOSFET.

PowerPAD 17 GND pin should be connected to the exposed power pad for proper operation. This power pad should be

PWRGD 14 An open drain output; asserts low if output voltage is low due to thermal shutdown, overcurrent,

connected to any internal PCB ground plane using multiple vias for good thermal performance.

over/under-voltage or EN shut down.
RT/CLK 8 Resistor Timing or External Clock input pin.
SS/TR 9 Slow start and tracking. An external capacitor connected to this pin sets the output voltage rise time.

This pin can also be used for tracking.
VIN 1, 2, 16 Input supply voltage, 2.95 V to 6 V.
VSENSE 6 Inverting node of the transconductance (gm) error amplifier.

DESCRIPTION

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ERROR

AMPLIFIER

Boot

Charge

Boot

UVLO

UVLO

Current

Sense

Oscillator

with PLL

Frequency

Shift

Slope

Compensation

PWM

Comparator

Minimum

COMP Clamp

Maximum

Clamp

Voltage

Reference

Overload
Recovery

VSENSE

SS/TR

COMP

RT/CLK

PH

BOOT

VIN

AGND

Thermal

Shutdown

EN

Enable

Comparator

Shutdown

Logic

Shutdown

Enable

Threshold

TPS54319RTE Block Diagram

Logic

Shutdown

PWRGD

POWERPAD

GND

Logic

Shutdown

107%

93%

S

Logic and PWM

Latch

i

1

i

hys

RT =400k ,
V =5V

W

I

-50 -25 0 25 50 75 100 125 150

T -JunctionTemperature-°C

J

450

455

460

465

470

475

480

485

490

495

500

f -SwitchingFrequency-kHz

s

0.02

0.03

0.04

0.05

0.06

0.07

0.08

RDSON - Static Drain-Source On-State Resistance - W

-50 -25 0 25 50 75 100 125 150

T - Junction Temperature - °C

J

High Side Rdson V = 3.3 V

IN

Low Side Rdson V = 3.3 V

IN

Low Side Rdson V = 5 V

IN

High Side Rdson V = 5 V

IN

TPS54319

SLVSA83 –JUNE 2010

FUNCTIONAL BLOCK DIAGRAM

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HIGH SIDE AND LOW SIDE Rdson vs TEMPERATURE FREQUENCY vs TEMPERATURE

6 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated

Figure 1. Figure 2.

TYPICAL CHARACTERISTICS CURVES

Product Folder Link(s): TPS54319

0.798

0.808

0.818

0.828

0.838

0.848

V =3.3V

I

0.858

-50 -25 0 25 50 75 100 125 150

T -JunctionTemperature-°C

J

V -VoltageReference-V

ref

V =3V

I

V =5V

I

-50 -25 0 25 50 75 100 125 150

T -JunctionTemperature-°C

J

6

6.2

6.4

6.6

6.8

7

7.2

7.4

7.6

7.8

8

HighSideSwitchCurrent- A

1000

1100

1200

1300

1400

1500

1600

1700

1800

1900

2000

80 100 120 140 160 180 200

RT-ResistancekW

f -SwitchingFrequency-KHz

s

300 400 500 600 700 800 900

1000

RT - Resistance - kW

200

300

400

500

600

700

800

900

1000

f - Switching Frequncy - KHz

s

0

25

50

75

100

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

Vsense-V

VsenseFalling

VsenseRising

NominalSwitchingFrequency-%

170

190

210

230

250

270

290

310

-50 -25 0 25 50 75 100 125 150

T -JunctionTemperature-°C

J

EA -Transconductance- A/Vm

V =3.3V

I

TPS54319

www.ti.com

SLVSA83 –JUNE 2010

TYPICAL CHARACTERISTICS CURVES (continued)

HIGH SIDE CURRENT LIMIT vs TEMPERATURE VOLTAGE REFERENCE vs TEMPERATURE

Figure 3. Figure 4.

SWITCHING FREQUENCY vs SWITCHING FREQUENCY vs

RT RESISTANCE LOW FREQUENCY RANGE RT RESISTANCE HIGH FREQUENCY RANGE

Figure 5. Figure 6.

SWITCHING FREQUENCY vs VSENSE TRANSCONDUCTANCE vs TEMPERATURE

Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 7

Figure 7. Figure 8.

Product Folder Link(s): TPS54319

55

60

65

70

75

80

85

90

95

100

105

V =3.3V

I

-50 -25 0 25 50 75 100 125 150

T -JunctionTemperature-°C

J

EA -Transconductance- A/Vm

1.15

1.16

1.17

1.18

1.19

1.2

1.21

1.22

1.23

1.24

1.25

1.26

1.27

1.28

1.29

1.3

V =3.3V,rising

I

-50 -25 0 25 50 75 100 125 150

T -JunctionTemperature-°C

J

V =3.3V,falling

I

EN-Threshold-V

-5.15

-5.05

-4.95

-4.85

-4.75

-4.65

-4.55

-4.45

-4.35

-4.25

V = 5 V,
Ven = Threshold +50 mV

I

-50 -25 0 25 50 75 100 125 150

T - Junction Temperature - °C

J

EN - Pin Current - Am

-1.65

-1.55

-1.45

-1.35

-1.25

-1.15

-1.05

-0.95

-0.85

V = 5 V,
Ven = Threshold -50 mV

I

EN - Pin Current - Am

-50 -25 0 25 50 75 100 125 150

T - Junction Temperature - °C

J

-3

-2.8

-2.6

-2.4

-2.2

-2

-1.8

-1.6

-1.4

-50 -30 -10 10 30 50 70 90 110 130 150

T - Junction Temperature - °C

J

V = 5 V

I

Iss/tr - Charge Current - Am

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

3

UVLOStartSwitching

UVLOStopSwitching

-50 -25 0 25 50 75 100 125 150

T -JunctionTemperature-°C

J

V -InputVoltage-V

I

TPS54319

SLVSA83 –JUNE 2010

TRANSCONDUCTANCE (SLOW START) vs

EN PIN CURRENT vs TEMPERATURE EN PIN CURRENT vs TEMPERATURE

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TYPICAL CHARACTERISTICS CURVES (continued)

JUNCTION TEMPERATURE EN PIN VOLTAGE vs TEMPERATURE

Figure 9. Figure 10.

Figure 11. Figure 12.

CHARGE CURRENT vs TEMPERATURE INPUT VOLTAGE vs TEMPERATURE

8 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated

Figure 13. Figure 14.

Product Folder Link(s): TPS54319

0

0.5

1

1.5

2

2.5

3

ShutdownSupplyCurrent- Am

V =3.3V

I

-50 -25 0 25 50 75 100 125 150

T -JunctionTemperature-°C

J

3 3.5 4 4.5 5 5.5 6

V -InputVoltage-V

I

T =25°C

J

0

0.5

1

1.5

2

2.5

3

ShutdownSupplyCurrent- Am

325

335

345

355

365

375

385

395

405

415

425

3 3.5 4 4.5 5 5.5 6

V -InputVoltage-V

I

Ivin-SupplyCurrent- Am

T =25°C

J

300

310

320

330

340

350

360

370

380

390

400

-50 -25 0 25 50 75 100 125 150

T -JunctionTemperature-°C

J

Ivin-SupplyCurrent- Am

V =3.3V

I

90

92

94

96

98

100

102

104

106

108

110

VsenseRising,V =5V

I

VsenseRising

VsenseFalling

-50 -25 0 25 50 75 100 125 150

T -JunctionTemperature-°C

J

PWRGDThreshold-%Vref

VsenseFalling

0

20

40

60

80

100

120

140

160

-50 -25 0 25 50 75 100 125 150

T -JunctionTemperature-°C

J

V =3.3V

I

RDSON-StaticDrain-SourceOn-StateResistance- W

TPS54319

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SLVSA83 –JUNE 2010

TYPICAL CHARACTERISTICS CURVES (continued)

SHUTDOWN SUPPLY CURRENT vs TEMPERATURE SHUTDOWN SUPPLY CURRENT vs INPUT VOLTAGE

Figure 15. Figure 16.

VIN SUPPLY CURRENT vs JUNCTION TEMPERATURE VIN SUPPLY CURRENT vs INPUT VOLTAGE

Figure 17. Figure 18.

PWRGD THRESHOLD vs TEMPERATURE PWRGD ON-RESISTANCE vs TEMPERATURE

Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 9

Figure 19. Figure 20.

Product Folder Link(s): TPS54319

0

10

20

30

40

50

60

70

V =5V,
SS=0.3V

I

80

-50 -25 0 25 50 75 100 125 150

T -JunctionTemperature-°C

J

SS/TR-VsenseOffset-mV

TPS54319

SLVSA83 –JUNE 2010

TYPICAL CHARACTERISTICS CURVES (continued)

SS/TR to VSENSE OFFSET vs TEMPERATURE

Figure 21.

OVERVIEW

The TPS54319 is a 6-V, 3-A, synchronous step-down (buck) converter with two integrated n-channel MOSFETs.
To improve performance during line and load transients the device implements a constant frequency, peak
current mode control which reduces output capacitance and simplifies external frequency compensation design.
The wide switching frequency of 300 kHz to 2000 kHz allows for efficiency and size optimization when selecting
the output filter components. The switching frequency is adjusted using a resistor to ground on the RT/CLK pin.
The device has an internal phase lock loop (PLL) on the RT/CLK pin that is used to synchronize the power
switch turn on to a falling edge of an external system clock.

The TPS54319 has a typical default start up voltage of 2.6 V. The EN pin has an internal pull-up current source
that can be used to adjust the input voltage under voltage lockout (UVLO) with two external resistors. In addition,
the pull up current provides a default condition when the EN pin is floating for the device to operate. The total
operating current for the TPS54319 is typically 360 mA when not switching and under no load. When the device
is disabled, the supply current is less than 5 mA.

The integrated 45 mΩ MOSFETs allow for high efficiency power supply designs with continuous output currents
up to 3 amperes.

The TPS54319 reduces the external component count by integrating the boot recharge diode. The bias voltage
for the integrated high side MOSFET is supplied by a capacitor between the BOOT and PH pins. The boot
capacitor voltage is monitored by an UVLO circuit and turns off the high side MOSFET when the voltage falls
below a preset threshold. This BOOT circuit allows the TPS54319 to operate approaching 100%. The output
voltage can be stepped down to as low as the 0.827 V reference.

The TPS54319 has a power good comparator (PWRGD) with 2% hysteresis.
The TPS54319 minimizes excessive output over-voltage transients by taking advantage of the over-voltage

power good comparator. When the regulated output voltage is greater than 107% of the nominal voltage, the
over-voltage comparator is activated, and the high side MOSFET is turned off and masked from turning on until
the output voltage is lower than 105%.

The SS/TR (slow start/tracking) pin is used to minimize inrush currents or provide power supply sequencing
during power up. A small value capacitor should be coupled to the pin for slow start. The SS/TR pin is
discharged before the output power up to ensure a repeatable restart after an over-temperature fault, UVLO fault
or disabled condition.

The use of a frequency fold-back circuit reduces the switching frequency during startup and over current fault
conditions to help limit the inductor current.

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O

0.827 V

R2 = R1

V 0.827 V

æ ö

´

ç ÷

-

è ø

TPS54319

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SLVSA83 –JUNE 2010

DETAILED DESCRIPTION

FIXED FREQUENCY PWM CONTROL

The TPS54319 uses an adjustable fixed frequency, peak current mode control. The output voltage is compared
through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives
the COMP pin. An internal oscillator initiates the turn on of the high side power switch. The error amplifier output
is compared to the high side power switch current. When the power switch current reaches the COMP voltage
level the high side power switch is turned off and the low side power switch is turned on. The COMP pin voltage
increases and decreases as the output current increases and decreases. The device implements a current limit
by clamping the COMP pin voltage to a maximum level and also implements a minimum clamp for improved
transient response performance.

SLOPE COMPENSATION AND OUTPUT CURRENT

The TPS54319 adds a compensating ramp to the switch current signal. This slope compensation prevents
sub-harmonic oscillations as duty cycle increases. The available peak inductor current remains constant over the
full duty cycle range.

BOOTSTRAP VOLTAGE (BOOT) AND LOW DROPOUT OPERATION

The TPS54319 has an integrated boot regulator and requires a small ceramic capacitor between the BOOT and
PH pin to provide the gate drive voltage for the high side MOSFET. The value of the ceramic capacitor should be

0.1 mF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or higher is
recommended because of the stable characteristics over temperature and voltage.

To improve drop out, the TPS54319 is designed to operate at 100% duty cycle as long as the BOOT to PH pin
voltage is greater than 2.2 V. The high side MOSFET is turned off using an UVLO circuit, allowing for the low
side MOSFET to conduct when the voltage from BOOT to PH drops below 2.2 V. Since the supply current
sourced from the BOOT pin is very low, the high side MOSFET can remain on for more switching cycles than are
required to refresh the capacitor, thus the effective duty cycle of the switching regulator is very high.

ERROR AMPLIFIER

The TPS54319 has a transconductance amplifier. The error amplifier compares the VSENSE voltage to the lower
of the SS/TR pin voltage or the internal 0.827 V voltage reference. The transconductance of the error amplifier is
245mA/V during normal operation. When the voltage of VSENSE pin is below 0.827 V and the device is
regulating using the SS/TR voltage, the gm is typically greater than 79 mA/V, but less than 245 mA/V. The
frequency compensation components are placed between the COMP pin and ground.

VOLTAGE REFERENCE

The voltage reference system produces a precise ±3.0% voltage reference over temperature by scaling the
output of a temperature-stable bandgap circuit. The bandgap and scaling circuits produce 0.827 V at the
non-inverting input of the error amplifier.

ADJUSTING THE OUTPUT VOLTAGE

The output voltage is set with a resistor divider from the output node to the VSENSE pin. It is recommended to
use divider resistors with 1% tolerance or better. Start with a 100 kΩ for the R1 resistor and use the Equation 1
to calculate R2. To improve efficiency at very light loads consider using larger value resistors. If the values are
too high the regulator is more susceptible to noise and voltage errors from the VSENSE input current are
noticeable.

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