TEXAS INSTRUMENTS TPS54240 Technical data

0

10

20

30

40

50

60

70

80

100

0 0.5 1.0 1.5 2.0

I - Output Current - A

O

Efficiency - %

2.5 3.0

90

VIN=12V
VOUT=3.3V
fsw=300kHz

PH

VIN

GND

BOOT

VSENSE

COMP

TPS54240

EN

RT /CLK

SS /TR

PWRGD

TPS54240

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SLVSAA6 –APRIL 2010

3.5V to 42V STEP DOWN SWIFT™ DC/DC CONVERTER WITH ECO-MODE™

Check for Samples: TPS54240

1

FEATURES

2

• 3.5V to 42V Input Voltage Range

• 200-mΩ High-Side MOSFET • Supported by SwitcherPro™ Software Tool

• High Efficiency at Light Loads with a Pulse
Skipping Eco-Mode™

• 138mA Operating Quiescent Current

• 1.3mA Shutdown Current

• 100kHz to 2.5MHz Switching Frequency

• Synchronizes to External Clock

• Adjustable Slow Start/Sequencing

• UV and OV Power Good Output

• Adjustable UVLO Voltage and Hysteresis

DESCRIPTION

The TPS54240 device is a 42V, 2.5A, step down regulator with an integrated high side MOSFET. Current mode
control provides simple external compensation and flexible component selection. A low ripple pulse skip mode
reduces the no load, regulated output supply current to 138mA. Using the enable pin, shutdown supply current is
reduced to 1.3mA, when the enable pin is low.

Under voltage lockout is internally set at 2.5V, but can be increased using the enable pin. The output voltage
startup ramp is controlled by the slow start pin that can also be configured for sequencing/tracking. An open
drain power good signal indicates the output is within 94% to 107% of its nominal voltage.

A wide switching frequency range allows efficiency and external component size to be optimized. Frequency fold
back and thermal shutdown protects the part during an overload condition.

The TPS54240 is available in 10 pin thermally enhanced MSOP Power Pad™ package.

SIMPLIFIED SCHEMATIC EFFICIENCY vs LOAD CURRENT

• 0.8-V Internal Voltage Reference

• MSOP10 Package With PowerPAD™

(http://focus.ti.com/docs/toolsw/folders/print/s

witcherpro.html)

• For SWIFT™ Documentation, See the TI
Website at http://www.ti.com/swift

APPLICATIONS

• 12-V and 24-V Industrial and Commercial Low
Power Systems

• GSM, GPRS Modules in Fleet Management,
E-Meters, and Security Systems

1

2Eco-Mode, PowerPAD, SwitcherPro, SWIFT are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright © 2010, Texas Instruments Incorporated

TPS54240

SLVSAA6 –APRIL 2010

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

Table 1. ORDERING INFORMATION

T

J

–40°C to 150°C 10 Pin MSOP TPS54240DGQ

(1) For the most current package and ordering information see the Package Option Addendum at the end

of this document, or see the TI website at www.ti.com.

(2) The DGQ package is also available taped and reeled. Add an R suffix to the device type (i.e.,

TPS54240DGQR).

ABSOLUTE MAXIMUM RATINGS

(1)

(1)

PACKAGE PART NUMBER

(2)

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Over operating temperature range (unless otherwise noted).

VALUE UNIT

VIN –0.3 to 47
EN –0.3 to 5
BOOT 55

Input voltage V

Output voltage PH –0.6 to 47 V

Voltage difference PAD to GND ±200 mV

Source current VSENSE 10 mA

Sink current

Electrostatic discharge (HBM) QSS 009-105 (JESD22-A114A) 2 kV
Electrostatic discharge (CDM) QSS 009-147 (JESD22-C101B.01) 500 V
Operating junction temperature –40 to 150 °C
Storage temperature –65 to 150 °C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

VSENSE –0.3 to 3
COMP –0.3 to 3
PWRGD –0.3 to 6
SS/TR –0.3 to 3
RT/CLK –0.3 to 3.6
BOOT-PH 8

PH, 10-ns Transient –2 to 47

EN 100 mA
BOOT 100 mA

PH Current Limit A
RT/CLK 100 mA
VIN Current Limit A
COMP 100 mA
PWRGD 10 mA
SS/TR 200 mA

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Product Folder Link(s): TPS54240

TPS54240

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PACKAGE DISSIPATION RATINGS

PACKAGE

MSOP 57 °C/W

(1) Test board conditions:

A. 3 inches × 3 inches, 2 layers, thickness: 0.062 inch
B. 2-ounce copper traces located on the top and bottom of the PCB
C. 6 (13 mil diameters) THERMAL VIAS LOCATED UNDER THE DEVICE PACKAGE

ELECTRICAL CHARACTERISTICS

TJ= –40°C to 150°C, VIN = 3.5 to 42V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SUPPLY VOLTAGE (VIN PIN)

Operating input voltage 3.5 42 V
Internal undervoltage lockout

threshold
Shutdown supply current EN = 0 V, 25°C, 3.5 V ≤ VIN ≤ 42 V 1.3 4
Operating : nonswitching supply

current

ENABLE AND UVLO (EN PIN)

Enable threshold voltage No voltage hysteresis, rising and falling, 25°C 1.15 1.25 1.36 V

Input current mA

Hysteresis current –2.9 mA

VOLTAGE REFERENCE

Voltage reference V

HIGH-SIDE MOSFET

On-resistance mΩ

ERROR AMPLIFIER

Input current 50 nA
Error amplifier transconductance (gM) –2 mA < I
Error amplifier transconductance (gM)

during slow start
Error amplifier dc gain V
Error amplifier bandwidth 2700 kHz
Error amplifier source/sink V
COMP to switch current

transconductance

CURRENT LIMIT

Current limit threshold VIN = 12 V, TJ= 25°C 3.5 6.1 A

THERMAL SHUTDOWN

Thermal shutdown 182 °C

No voltage hysteresis, rising and falling 2.5 V

VSENSE = 0.83 V, VIN = 12 V, 25°C 138 200

Enable threshold +50 mV –3.8
Enable threshold –50 mV –0.9

TJ= 25°C 0.792 0.8 0.808

VIN = 3.5 V, BOOT-PH = 3 V 300
VIN = 12 V, BOOT-PH = 6 V 200 410

< 2 mA, V

COMP

–2 mA < I
V

VSENSE
VSENSE

(COMP)

< 2 mA, V

COMP

= 0.4 V
= 0.8 V 10,000 V/V

= 1 V, 100 mV overdrive ±27 mA

SLVSAA6 –APRIL 2010

(1)

THERMAL IMPEDANCE

JUNCTION TO AMBIENT

0.784 0.8 0.816

= 1 V 310 mMhos

COMP

= 1 V,

COMP

70 mMhos

10.5 A/V

mA

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TPS54240

SLVSAA6 –APRIL 2010

ELECTRICAL CHARACTERISTICS (continued)

TJ= –40°C to 150°C, VIN = 3.5 to 42V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)

Switching Frequency Range using
RT mode

f

SW

SLOW START AND TRACKING (SS/TR)

POWER GOOD (PWRGD PIN)

V

VSENSE

Switching frequency RT= 200 kΩ 450 581 720 kHz
Switching Frequency Range using

CLK mode
Minimum CLK input pulse width 40 ns
RT/CLK high threshold 1.9 2.2 V
RT/CLK low threshold 0.5 0.7 V
RT/CLK falling edge to PH rising

edge delay
PLL lock in time Measured at 500 kHz 100 ms

Charge current V
SS/TR-to-VSENSE matching V
SS/TR-to-reference crossover 98% nominal 1.15 V
SS/TR discharge current (overload) VSENSE = 0 V, V(SS/TR) = 0.4 V 382 mA
SS/TR discharge voltage VSENSE = 0 V 54 mV

VSENSE threshold

Hysteresis VSENSE falling 2%
Output high leakage VSENSE = VREF, V(PWRGD) = 5.5 V, 25°C 10 nA
On resistance I(PWRGD) = 3 mA, VSENSE < 0.79 V 50 Ω
Minimum VIN for defined output V(PWRGD) < 0.5 V, II(PWRGD) = 100 mA 0.95 1.5 V

Measured at 500 kHz with RT resistor in series 60 ns

= 0.4 V 2 mA

SS/TR

= 0.4 V 45 mV

SS/TR

VSENSE falling 92%
VSENSE rising 94%
VSENSE rising 109%
VSENSE falling 107%

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100 2500 kHz

300 2200 kHz

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1

2

3

4

5

6

7

9

8

10

Thermal

Pad

(11)

BOOT

VIN

EN

PH

GND

COMP

VSENSE

PWRGD

SS/TR

RT/CLK

MSOP10

(TOP VIEW)

TPS54240

www.ti.com

SLVSAA6 –APRIL 2010

DEVICE INFORMATION

PIN CONFIGURATION

PIN FUNCTIONS

PIN

NAME NO.

BOOT 1 O

COMP 8 O

EN 3 I
GND 9 – Ground

PH 10 I The source of the internal high-side power MOSFET.
POWERPAD 11 – GND pin must be electrically connected to the exposed pad on the printed circuit board for proper operation.

PWRGD 6 O

RT/CLK 5 I a mode change occurs and the pin becomes a synchronization input. The internal amplifier is disabled and

SS/TR 4 I
VIN 2 I Input supply voltage, 3.5 V to 42 V.

VSENSE 7 I Inverting node of the transconductance ( gm) error amplifier.

I/O DESCRIPTION

A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the
minimum required by the output device, the output is forced to switch off until the capacitor is refreshed.

Error amplifier output, and input to the output switch current comparator. Connect frequency compensation
components to this pin.

Enable pin, internal pull-up current source. Pull below 1.2V to disable. Float to enable. Adjust the input
undervoltage lockout with two resistors.

An open drain output, asserts low if output voltage is low due to thermal shutdown, dropout, over-voltage or
EN shut down.

Resistor Timing and External Clock. An internal amplifier holds this pin at a fixed voltage when using an
external resistor to ground to set the switching frequency. If the pin is pulled above the PLL upper threshold,

the pin is a high impedance clock input to the internal PLL. If clocking edges stop, the internal amplifier is
re-enabled and the mode returns to a resistor set function.

Slow-start and Tracking. An external capacitor connected to this pin sets the output rise time. Since the
voltage on this pin overrides the internal reference, it can be used for tracking and sequencing.

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ERROR

AMPLIFIER

Boot

Charge

Boot

UVLO

UVLO

Current

Sense

Oscillator

withPLL

Frequency

Shift

Logic

And

PWMLatch

Slope

Compensation

PWM

Comparator

Minimum

Clamp

Pulse

Skip

Maximum

Clamp

Voltage

Reference

Overload
Recovery

VSENSE

SS/TR

COMP

RT/CLK

PH

BOOT

VIN

Thermal

Shutdown

EN

Enable

Comparator

Shutdown

Logic

Shutdown

Enable

Threshold

TPS54240 BlockDiagram

Logic

Shutdown

PWRGD

Shutdown

OV

GND

POWERPAD

7

4

8

5

9

11

10

1

2

3

6

UV

TPS54240

SLVSAA6 –APRIL 2010

FUNCTIONAL BLOCK DIAGRAM

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0.784

0.792

0.800

0.808

0.816

-50 -25 0 25 50 75 100 125 150

V -VoltageReference-V

ref

T -JunctionTemperature-°C

J

V =12V

I

0

125

250

375

500

-50 -25 0 25 50 75 100 125 150

T -JunctionTemperature-°C

J

RDSON-StaticDrain-SourceOn-StateResistance-mW

BOOT-PH=3V

BOOT-PH=6V

V =12V

I

550

570

580

590

600

610

-50 -25 0 25 50 75 100 125 150

f -SwitchingFrequency-kHz

s

560

T -JunctionTemperature-°C

J

V =12V,

RT =200kIW

5.0

5.5

6.0

7.0

-50 -25 0 25 50 75 100 125 150

SwitchCurrent- A

T -JunctionTemperature-°C

J

6.5

V =12V

I

0

500

1000

1500

2000

2500

0 25 50 75 100 125 150 175 200

RT/CLK-Resistance-kW

f -SwitchingFrequency-kHz

s

V =12V,
T =25°C

I

J

0

100

200

300

400

500

200 300 400 500 600 700 800 900 1000 1100

RT/CLK-Resistance-kW

f -SwitchingFrequency-kHz

s

1200

V =12V,
T =25°C

I

J

TPS54240

www.ti.com

SLVSAA6 –APRIL 2010

TYPICAL CHARACTERISTICS

ON RESISTANCE vs JUNCTION TEMPERATURE VOLTAGE REFERENCE vs JUNCTION TEMPERATURE

Figure 1. Figure 2.

SWITCH CURRENT LIMIT vs JUNCTION TEMPERATURE SWITCHING FREQUENCY vs JUNCTION TEMPERATURE

Figure 3. Figure 4.

SWITCHING FREQUENCY vs RT/CLK RESISTANCE HIGH SWITCHING FREQUENCY vs RT/CLK RESISTANCE LOW

FREQUENCY RANGE FREQUENCY RANGE

Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 7

Figure 5. Figure 6.

Product Folder Link(s): TPS54240

20

60

100

120

-50 -25 0 25 50 75 100 125 150

gm- A/Vm

T -JunctionTemperature-°C

J

V =12V

I

40

80

200

250

300

350

400

500

-50 -25 0 25 50 75 100 125 150

gm- A/Vm

T -JunctionTemperature-°C

J

V =12V

I

450

1.10

1.20

1.30

1.40

-50

-25 0 25 50

75

100

125

150

EN-Threshold-V

T -JunctionTemperature-°C

J

V =12V

I

-4.25

-4

-3.75

-3.5

-3.25

-50 -25 0 25 50 75 100 125 150

I - A

(EN)

m

T -JunctionTemperature-°C

J

V =12V,
V = Threshold+50mV

I

I(EN)

-1

-0.95

-0.9

-0.85

-0.8

-50 -25

0

25

50 75 100

125

150

I - A

(EN)

m

T -JunctionTemperature-°C

J

V =12V,
V = Threshold-50mV

I

I(EN)

-3

-2.5

-2

-1.5

-1

-50 -25 0 25 50 75 100 125 150

I - A

(SS/TR)

m

T -JunctionTemperature-°C

J

V =12V

I

TPS54240

SLVSAA6 –APRIL 2010

TYPICAL CHARACTERISTICS (continued)

EA TRANSCONDUCTANCE DURING SLOW START vs

JUNCTION TEMPERATURE EA TRANSCONDUCTANCE vs JUNCTION TEMPERATURE

Figure 7. Figure 8.

EN PIN VOLTAGE vs JUNCTION TEMPERATURE EN PIN CURRENT vs JUNCTION TEMPERATURE

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Figure 9. Figure 10.

EN PIN CURRENT vs JUNCTION TEMPERATURE SS/TR CHARGE CURRENT vs JUNCTION TEMPERATURE

8 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated

Figure 11. Figure 12.

Product Folder Link(s): TPS54240

200

275

350

425

575

-50 0 50 100 150

I - A

I(SS/TR)

m

T -JunctionTemperature-°C

J

V =12V

I

500

0

20

40

60

80

100

0 0.2 0.4 0.6 0.8

V -V

SENSE

V =12V,
T =25°C

I

J

%ofNominalf

sw

0

0.5

1

1.5

2

-50 -25 0 25 50 75 100 125 150

I - A

(VIN)

m

T -JunctionTemperature-°C

J

V =12V

I

0

0.5

1

1.5

2

0 10 20 30 40

V -InputVoltage-V

I

I - A

(VIN)

m

T =25°C

J

70

110

130

150

170

210

-50 0 50 100 150

I - A

(VIN)

m

T -JunctionTemperature-°C

J

V =12V,
V =0.83V

I

I(VSENSE)

90

190

110

130

150

170

0 20

40

I - A

(VIN)

m

V -InputVoltage-V

I

T =25 C,
V =0.83V

J

I(VSENSE)

o

TPS54240

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SLVSAA6 –APRIL 2010

TYPICAL CHARACTERISTICS (continued)

SS/TR DISCHARGE CURRENT vs JUNCTION TEMPERATURE SWITCHING FREQUENCY vs VSENSE

Figure 13. Figure 14.

SHUTDOWN SUPPLY CURRENT vs JUNCTION TEMPERATURE SHUTDOWN SUPPLY CURRENT vs INPUT VOLTAGE (Vin)

Figure 15. Figure 16.

VIN SUPPLY CURRENT vs JUNCTION TEMPERATURE VIN SUPPLY CURRENT vs INPUT VOLTAGE

Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 9

Figure 17. Figure 18.

Product Folder Link(s): TPS54240

85

90

95

100

105

110

115

-50 -25 0 25 50 75 100 125 150

PWRGDThreshold-%ofV

ref

VSENSEFalling

VSENSERising

VSENSEFalling

VSENSERising

V =12V

I

T -JunctionTemperature-°C

J

0

20

40

60

80

100

-50

-25

0 25

50

75

100

125

150

RDSON- W

T -JunctionTemperature-°C

J

V =12V

I

2

2.25

2.50

2.75

3

-50 -25 0 25 50 75 100 125 150

V -V

I(VIN)

T -JunctionTemperature-°C

J

1.5

1.8

2

2.3

2.5

-50 -25 0 25 50 75 100 125 150

V -V

I(BOOT-PH)

T -JunctionTemperature-°C

J

0

100

200

300

400

500

0 100 200 300 400 500 600 700 800

VSENSE-mV

Offset-mV

600

V =12V,

I

T =25 C

J

o

0

10

20

30

40

50

60

-50 -25 0 25 50 75 100 125 150

Offset-mV

T -JunctionTemperature-°C

J

V =0.4V

(SS/TR)

V =12V

I

TPS54240

SLVSAA6 –APRIL 2010

TYPICAL CHARACTERISTICS (continued)

PWRGD ON RESISTANCE vs JUNCTION TEMPERATURE PWRGD THRESHOLD vs JUNCTION TEMPERATURE

Figure 19. Figure 20.

BOOT-PH UVLO vs JUNCTION TEMPERATURE INPUT VOLTAGE (UVLO) vs JUNCTION TEMPERATURE

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Figure 21. Figure 22.

SS/TR TO VSENSE OFFSET vs VSENSE SS/TR TO VSENSE OFFSET vs TEMPERATURE

10 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated

Figure 23. Figure 24.

Product Folder Link(s): TPS54240

TPS54240

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SLVSAA6 –APRIL 2010

OVERVIEW

The TPS54240 device is a 42-V, 2.5-A, step-down (buck) regulator with an integrated high side n-channel
MOSFET. To improve performance during line and load transients the device implements a constant frequency,
current mode control which reduces output capacitance and simplifies external frequency compensation design.
The wide switching frequency of 100kHz to 2500kHz allows for efficiency and size optimization when selecting
the output filter components. The switching frequency is adjusted using a resistor to ground on the RT/CLK pin.
The device has an internal phase lock loop (PLL) on the RT/CLK pin that is used to synchronize the power
switch turn on to a falling edge of an external system clock.

The TPS54240 has a default start up voltage of approximately 2.5V. The EN pin has an internal pull-up current
source that can be used to adjust the input voltage under voltage lockout (UVLO) threshold with two external
resistors. In addition, the pull up current provides a default condition. When the EN pin is floating the device will
operate. The operating current is 138mA when not switching and under no load. When the device is disabled, the
supply current is 1.3mA.

The integrated 200mΩ high side MOSFET allows for high efficiency power supply designs capable of delivering

2.5 amperes of continuous current to a load. The TPS54240 reduces the external component count by
integrating the boot recharge diode. The bias voltage for the integrated high side MOSFET is supplied by a
capacitor on the BOOT to PH pin. The boot capacitor voltage is monitored by an UVLO circuit and will turn the
high side MOSFET off when the boot voltage falls below a preset threshold. The TPS54240 can operate at high
duty cycles because of the boot UVLO. The output voltage can be stepped down to as low as the 0.8V
reference.

The TPS54240 has a power good comparator (PWRGD) which asserts when the regulated output voltage is less
than 92% or greater than 109% of the nominal output voltage. The PWRGD pin is an open drain output which
deasserts when the VSENSE pin voltage is between 94% and 107% of the nominal output voltage allowing the
pin to transition high when a pull-up resistor is used.

The TPS54240 minimizes excessive output overvoltage (OV) transients by taking advantage of the OV power
good comparator. When the OV comparator is activated, the high side MOSFET is turned off and masked from
turning on until the output voltage is lower than 107%.

The SS/TR (slow start/tracking) pin is used to minimize inrush currents or provide power supply sequencing
during power up. A small value capacitor should be coupled to the pin to adjust the slow start time. A resistor
divider can be coupled to the pin for critical power supply sequencing requirements. The SS/TR pin is discharged
before the output powers up. This discharging ensures a repeatable restart after an over-temperature fault,
UVLO fault or a disabled condition.

The TPS54240, also, discharges the slow start capacitor during overload conditions with an overload recovery
circuit. The overload recovery circuit will slow start the output from the fault voltage to the nominal regulation
voltage once a fault condition is removed. A frequency foldback circuit reduces the switching frequency during
startup and overcurrent fault conditions to help control the inductor current.

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TPS54240

SLVSAA6 –APRIL 2010

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DETAILED DESCRIPTION

Fixed Frequency PWM Control

The TPS54240 uses an adjustable fixed frequency, peak current mode control. The output voltage is compared
through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives
the COMP pin. An internal oscillator initiates the turn on of the high side power switch. The error amplifier output
is compared to the high side power switch current. When the power switch current reaches the level set by the
COMP voltage, the power switch is turned off. The COMP pin voltage will increase and decrease as the output
current increases and decreases. The device implements a current limit by clamping the COMP pin voltage to a
maximum level. The Eco-Mode™ is implemented with a minimum clamp on the COMP pin.

Slope Compensation Output Current

The TPS54240 adds a compensating ramp to the switch current signal. This slope compensation prevents
sub-harmonic oscillations. The available peak inductor current remains constant over the full duty cycle range.

Pulse Skip Eco-Mode

The TPS54240 operates in a pulse skip Eco mode at light load currents to improve efficiency by reducing
switching and gate drive losses. The TPS54240 is designed so that if the output voltage is within regulation and
the peak switch current at the end of any switching cycle is below the pulse skipping current threshold, the
device enters Eco mode. This current threshold is the current level corresponding to a nominal COMP voltage or
500mV.

When in Eco-mode, the COMP pin voltage is clamped at 500mV and the high side MOSFET is inhibited. Further
decreases in load current or in output voltage can not drive the COMP pin below this clamp voltage level.

Since the device is not switching, the output voltage begins to decay. As the voltage control loop compensates
for the falling output voltage, the COMP pin voltage begins to rise. At this time, the high side MOSFET is enabled
and a switching pulse initiates on the next switching cycle. The peak current is set by the COMP pin voltage. The
output voltage re-charges the regulated value, then the peak switch current starts to decrease, and eventually
falls below the Eco mode threshold at which time the device again enters Eco mode.

For Eco mode operation, the TPS54240 senses peak current, not average or load current, so the load current
where the device enters Eco mode is dependent on the output inductor value. For example, the circuit in

Figure 49 enters Eco mode at about 5 mA of output current. When the load current is low and the output voltage

is within regulation, the device enters a sleep mode and draws only 138mA input quiescent current. The internal
PLL remains operating when in sleep mode. When operating at light load currents in the pulse skip mode, the
switching transitions occur synchronously with the external clock signal.

Low Dropout Operation and Bootstrap Voltage (BOOT)

The TPS54240 has an integrated boot regulator, and requires a small ceramic capacitor between the BOOT and
PH pins to provide the gate drive voltage for the high side MOSFET. The BOOT capacitor is refreshed when the
high side MOSFET is off and the low side diode conducts. The value of this ceramic capacitor should be 0.1mF.
A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10V or higher is recommended
because of the stable characteristics overtemperature and voltage.

To improve drop out, the TPS54240 is designed to operate at 100% duty cycle as long as the BOOT to PH pin
voltage is greater than 2.1V. When the voltage from BOOT to PH drops below 2.1V, the high side MOSFET is
turned off using an UVLO circuit which allows the low side diode to conduct and refresh the charge on the BOOT
capacitor. Since the supply current sourced from the BOOT capacitor is low, the high side MOSFET can remain
on for more switching cycles than are required to refresh the capacitor, thus the effective duty cycle of the
switching regulator is high.

The effective duty cycle during dropout of the regulator is mainly influenced by the voltage drops across the
power MOSFET, inductor resistance, low side diode and printed circuit board resistance. During operating
conditions in which the input voltage drops and the regulator is operating in continuous conduction mode, the
high side MOSFET can remain on for 100% of the duty cycle to maintain output regulation, until the BOOT to PH
voltage falls below 2.1V.

12 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated

Product Folder Link(s): TPS54240

4.6

4.8

5

5.2

5.4

5.6

0 0.05 0.10 0.15 0.20

I -OutputCurrent- A

O

V -InputVoltage-V

I

V =5V

O

Start

Stop

3

3.2

3.4

3.6

3.8

4

0 0.05 0.10 0.15 0.20

I -OutputCurrent- A

O

V -InputVoltage-V

I

V =3.3V

O

Start

Stop

TPS54240

www.ti.com

SLVSAA6 –APRIL 2010

DETAILED DESCRIPTION (continued)

Attention must be taken in maximum duty cycle applications which experience extended time periods with light
loads or no load. When the voltage across the BOOT capacitor falls below the 2.1V UVLO threshold, the high
side MOSFET is turned off, but there may not be enough inductor current to pull the PH pin down to recharge the
BOOT capacitor. The high side MOSFET of the regulator stops switching because the voltage across the BOOT
capacitor is less than 2.1V. The output capacitor then decays until the difference in the input voltage and output
voltage is greater than 2.1V, at which point the BOOT UVLO threshold is exceeded, and the device starts
switching again until the desired output voltage is reached. This operating condition persists until the input
voltage and/or the load current increases. It is recommended to adjust the VIN stop voltage greater than the
BOOT UVLO trigger condition at the minimum load of the application using the adjustable VIN UVLO feature with
resistors on the EN pin.

The start and stop voltages for typical 3.3V and 5V output applications are shown in Figure 25 and Figure 26.
The voltages are plotted versus load current. The start voltage is defined as the input voltage needed to regulate
the output within 1%. The stop voltage is defined as the input voltage at which the output drops by 5% or stops
switching.

During high duty cycle conditions, the inductor current ripple increases while the BOOT capacitor is being
recharged resulting in an increase in ripple voltage on the output. This is due to the recharge time of the boot
capacitor being longer than the typical high side off time when switching occurs every cycle.

Figure 25. 3.3V Start/Stop Voltage Figure 26. 5.0V Start/Stop Voltage

Error Amplifier

The TPS54240 has a transconductance amplifier for the error amplifier. The error amplifier compares the
VSENSE voltage to the lower of the SS/TR pin voltage or the internal 0.8V voltage reference. The
transconductance (gm) of the error amplifier is 310mA/V during normal operation. During the slow start operation,
the transconductance is a fraction of the normal operating gm. When the voltage of the VSENSE pin is below

0.8V and the device is regulating using the SS/TR voltage, the gm is 70mA/V.
The frequency compensation components (capacitor, series resistor and capacitor) are added to the COMP pin

to ground.

Voltage Reference

The voltage reference system produces a precise ±2% voltage reference over temperature by scaling the output
of a temperature stable bandgap circuit.

Adjusting the Output Voltage

The output voltage is set with a resistor divider from the output node to the VSENSE pin. It is recommended to
use 1% tolerance or better divider resistors. Start with a 10 kΩ for the R2 resistor and use the Equation 1 to
calculate R1. To improve efficiency at light loads consider using larger value resistors. If the values are too high
the regulator will be more susceptible to noise and voltage errors from the VSENSE input current will be
noticeable.

Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 13

Product Folder Link(s): TPS54240

Vout 0.8V

R1 = R2

0.8 V

-

æ ö

´

ç ÷
è ø

EN

VIN

+

-

TPS54240

R1

R2

Ihys

I1

0.9 Am

1.25V

2.9 Am

START STOP

HYS

V V

R1

I

-

=

ENA

START ENA

1

V

R2

V V

I

R1

=

­+

EN

Ihys

VIN

+

-

TPS54240

R1

R2

VOUT

R3

I1

0.9 Am

2.9 Am

1.25V

TPS54240

SLVSAA6 –APRIL 2010

www.ti.com

DETAILED DESCRIPTION (continued)

(1)

Enable and Adjusting Undervoltage Lockout

The TPS54240 is disabled when the VIN pin voltage falls below 2.5 V. If an application requires a higher
undervoltage lockout (UVLO), use the EN pin as shown in Figure 27 to adjust the input voltage UVLO by using
the two external resistors. Though it is not necessary to use the UVLO adjust registers, for operation it is highly
recommended to provide consistent power up behavior. The EN pin has an internal pull-up current source, I1, of

0.9mA that provides the default condition of the TPS54240 operating when the EN pin floats. Once the EN pin
voltage exceeds 1.25V, an additional 2.9mA of hysteresis, Ihys, is added. This additional current facilitates input
voltage hysteresis. Use Equation 2 to set the external hysteresis for the input voltage. Use Equation 3 to set the
input start voltage.

Figure 27. Adjustable Undervoltage Lockout (UVLO)

Another technique to add input voltage hysteresis is shown in Figure 28. This method may be used, if the
resistance values are high from the previous method and a wider voltage hysteresis is needed. The resistor R3
sources additional hysteresis current into the EN pin.

Figure 28. Adding Additional Hysteresis

Product Folder Link(s): TPS54240

14 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated

(2)

(3)

STA RT S TOP

OUT

HYS

V V

R1

V

I

R3

-

=

+

ENA

START ENA

ENA

1

V

R2

V V

V

I

R1 R3

=

­+ -

Tss(ms) Iss( A)

Css(nF) =

Vref (V) 0.8

m´

´

EN

SS/TR

V

SENSE

VOUT

TPS54240

www.ti.com

SLVSAA6 –APRIL 2010

DETAILED DESCRIPTION (continued)

(4)

(5)

Slow Start/Tracking Pin (SS/TR)

The TPS54240 effectively uses the lower voltage of the internal voltage reference or the SS/TR pin voltage as
the power-supply's reference voltage and regulates the output accordingly. A capacitor on the SS/TR pin to
ground implements a slow start time. The TPS54240 has an internal pull-up current source of 2mA that charges
the external slow start capacitor. The calculations for the slow start time (10% to 90%) are shown in Equation 6.
The voltage reference (V
remain lower than 0.47mF and greater than 0.47nF.

At power up, the TPS54240 will not start switching until the slow start pin is discharged to less than 40 mV to
ensure a proper power up, see Figure 29.

Also, during normal operation, the TPS54240 will stop switching and the SS/TR must be discharged to 40 mV,
when the VIN UVLO is exceeded, EN pin pulled below 1.25V, or a thermal shutdown event occurs.

The VSENSE voltage will follow the SS/TR pin voltage with a 45mV offset up to 85% of the internal voltage
reference. When the SS/TR voltage is greater than 85% on the internal reference voltage the offset increases as
the effective system reference transitions from the SS/TR voltage to the internal voltage reference (see

Figure 23). The SS/TR voltage will ramp linearly until clamped at 1.7V.

) is 0.8 V and the slow start current (ISS) is 2mA. The slow start capacitor should

REF

(6)

Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 15

Figure 29. Operation of SS/TR Pin when Starting

Product Folder Link(s): TPS54240