TEXAS INSTRUMENTS TPS54073 Technical data

6,4 mm X 9,7 mm

Typical Size

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PVIN PH

BOOT

PGND

VSENSE

Output

COMPAGND

VBIAS

Voltage
Input 1

TPS54073

* *

*

* Optional

TYPICAL APPLICATION

R = 1.5LW

V = 1.5 V

(core)

V

I/O

= 3.3 V

500 mV/div

t - Time - 5 ms/div

START-UP WAVEFORM

WITH 3 PRECHARGE DIODES

VIN

Voltage
Input 2

查询TPS54073PWPR供应商

2.2 – 4 -V, 14-A SYNCHRONOUS BUCK CONVERTER
WITH DISABLED SINKING DURING START-UP

FEATURES DESCRIPTION

• 8-m Ω MOSFET Switches for High Efficiency at

14.5-A Peak Output Current

• Separate Low-Voltage Power Bus

• Disabled Current Sinking During Start-Up

• Adjustable Output Voltage Down to 0.9 V

• Wide PWM Frequency: Fixed 350 kHz, 550 kHz

or Adjustable 280 kHz to 700 kHz

• Synchronizable to 700 kHz

• Load Protected by Peak Current Limit and

Thermal Shutdown

• Integrated Solution Reduces Board Area and

Total Cost

APPLICATIONS

• Low-Voltage, High-Density Distributed Power

Systems

• Point of Load Regulation for High-

Performance DSPs, FPGAs, ASICs, and
Microprocessors

• Broadband, Networking, and Optical

Communications Infrastructure

• Power PC Series Processors

TPS54073

SLVS547 – FEBRUARY 2005

As a member of the SWIFT™family of dc/dc regu­lators, the TPS54073 low-input voltage high-output
current synchronous buck PWM converter integrates
all required active components. Included on the
substrate with the listed features are a true, high
performance, voltage error amplifier that enables
maximum performance and flexibility in choosing the
output filter L and C components; an
undervoltage-lockout circuit to prevent start-up until
the input voltage reaches 3 V; an internally or
externally set slow-start circuit to limit in-rush
currents; and a power good output useful for
processor/logic reset, fault signaling, and supply se­quencing.

For reliable power up in output precharge appli­cations, the TPS54073 is designed to only source
current during start-up.

The TPS54073 is available in a thermally enhanced
28-pin TSSOP (PWP) PowerPAD™ package, which
eliminates bulky heatsinks. TI provides evaluation
modules and the SWIFT™ designer software tool to
aid in quickly achieving high-performance power
supply designs to meet aggressive equipment devel­opment cycles

SWIFT, PowerPAD are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright © 2005, Texas Instruments Incorporated

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TPS54073

SLVS547 – FEBRUARY 2005

These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION

T

A

-40 ° C to 85 ° C Adjustible down to 0.9 V Plastic HTSSOP (PWP)

(1) The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS54073PWPR). See the application

section of the data sheet for PowerPAD drawing and layout information.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

V

I

V

O

V

O

I

S

T

J

T

stg

(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings

Input voltage range VSENSE –0.3 to 4 V

Output voltage range V

Source current

Sink current COMP 6 mA

Voltage differential AGND to PGND ± 0.3 V
Operating junction temperature range –40 to 125 ° C
Storage temperature range –65 to 150 ° C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300 ° C

Electrostatic Discharge (ESD) ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

OUTPUT VOLTAGE PACKAGE PART NUMBER

(1)

(1)

TPS54073 UNIT

SS/ENA, SYNC –0.3 to 7
RT –0.3 to 6

PVIN, VIN –0.3 to 4.5
BOOT –0.3 to 10
VBIAS, COMP, PWRGD –0.3 to 7
PH –0.6 to 6
PH Internally limited
COMP, VBIAS 6 mA
PH 25 A

SS/ENA, PWRGD 10

Human body model (HBM) 1 kV
CDM 1000 V

TPS54073PWP

RECOMMENDED OPERATING CONDITIONS

MIN NOM MAX UNIT

V

Input voltage, VIN 3 4 V

I

Power Input voltage, PVIN 2.2 4 V

T

Operating junction temperature –40 125 ° C

J

DISSIPATION RATINGS

PACKAGE

28-Pin PWP with solder 14.87 ° C/W 6.72 W

(1) For more information on the PWP package, see TI technical brief, literature number SLMA002 .
(2) Test board conditions:

a. 3 inch x 3 inch, 4 layers, thickness = 0.062 inch
b. 2-ounce copper traces located on die top of the PCB.
c. 2-ounce copper mixed plane and traces on the bottom of the PCB.
d. 2-ounce copper ground planes on the two internal layers of the PCB.
e. 12 thermal vias (see the Figure 11 in the Application Section of this data sheet.

(3) Maximum power dissipation may be limited by over current protection.
2

(1) (2)

THERMAL IMPEDANCE TA= 25 ° C TA= 70 ° C TA= 85 ° C

JUNCTION-TO-AMBIENT POWER RATING POWER RATING POWER RATING

(3)

3.69 W 2.69 W

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DISSIPATION RATINGS (continued)

PACKAGE

28-Pin PWP without solder

(4)

THERMAL IMPEDANCE TA= 25 ° C TA= 70 ° C TA= 85 ° C

JUNCTION-TO-AMBIENT POWER RATING POWER RATING POWER RATING

27.9 ° C/W 3.58 W 1.97 W 1.43 W

ELECTRICAL CHARACTERISTICS

TJ= -40 ° C to 125 ° C, VIN = 3 V to 4 V, PVIN = 2.2 V to 4 V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SUPPLY VOLTAGE, VIN

V

Input voltage, VIN 3 4 V

I

Supply voltage range, PVIN Output = 1.8 V 2.2 4 V

fs= 350 kHz, RT open, PH pin open, SYNC = 0 V,
PVIN = 2.5 V

VIN = 3.3 V fs= 550 kHz, RT open, PH pin open, SYNC ≥ 2.5 V, 8.6 13 mA

I

Quiescent current

Q

PVIN = 2.5 V fs= 550 kHz, RT open, PH pin open, SYNC ≥ 2.5 V,

UNDERVOLTAGE LOCKOUT (VIN)

Start threshold voltage, UVLO 2.9 3 V
Stop threshold voltage, UVLO 2.7 2.8 V
Hysteresis voltage, UVLO 100 mV
Rising and falling edge deglitch, UVLO

BIAS VOLTAGE

Output voltage, VBIAS I
Output current, VBIAS

(2)

CUMULATIVE REFERENCE

V

Accuracy 0.882 0.891 0.900 V

ref

REGULATION

Line regulation
Load regulation

(1) (3)

(1) (3)

OSCILLATOR

Internally set—free running frequency kHz

Externally set—free running frequency range RT = 100 k Ω (1% resistor to AGND) 460 500 540 kHz

High-level threshold voltage, SYNC 2.5 V
Low-level threshold voltage, SYNC 0.8 V
Pulse duration, SYNC

(1)

Frequency range, SYNC 300 700 kHz
Ramp valley
Ramp amplitude (peak-to-peak)
Minimum controllable on time
Maximum duty cycle

(1)

(1)

(1)

(1)

(4) Estimated performance
(1) Specified by design
(2) Static resistive loads only
(3) Specified by the circuit used in Figure 12

(1)

PVIN = 2.5 V
SHUTDOWN, SS/ENA = 0 V, PVIN = 2.5 V 1 1.4 mA
fs= 350 kHz, RT open, PH pin open, SYNC = 0 V,

VIN = 3.3 V

VIN = 3.3 V
SHUTDOWN, SS/ENA = 0 V, VIN = 3.3 V < 140 µA

= 0 2.7 2.8 2.9 V

(VBIAS)

IL= 7 A, fs= 350 kHz, TJ= 85 ° C 0.05 %/V
IL= 0 A to 14 A, fs= 350 kHz, TJ= 85 ° C

PVIN = 2.5 V, VIN = 3.3 V

(1)

RT open
RT open

, SYNC ≤ 0.8 V 280 350 420

(1)

, SYNC ≥ 2.5 V 440 550 660

RT = 180 k Ω (1% resistor to AGND)

RT = 68 k Ω (1% resistor to AGND)

TPS54073

SLVS547 – FEBRUARY 2005

6.3 10 mA

3.2 6 mA

4.4 7 mA

2.5 µs

100 µA

0.013 %/A

(1)

(1)

252 280 308

663 700 762

50 ns

0.75 V
1 V

200 ns

90%

3

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TPS54073

SLVS547 – FEBRUARY 2005

ELECTRICAL CHARACTERISTICS (continued)

TJ= -40 ° C to 125 ° C, VIN = 3 V to 4 V, PVIN = 2.2 V to 4 V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ERROR AMPLIFIER

(4)

(4)

ref

(4)

(4)

PWM COMPARATOR

SLOW-START/ENABLE

POWER GOOD

CURRENT LIMIT

THERMAL SHUTDOWN

OUTPUT POWER MOSFETS

r

DS(on)

Error amplifier open-loop voltage gain 1 k Ω COMP to AGND
Error amplifier unity gain bandwidth Parallel 10 k Ω , 160 pF COMP to AGND
Error amplifier common mode input voltage

range

Powered by internal LDO

Input bias current, VSENSE VSENSE = V
Output voltage slew rate (symmetric), COMP 1 1.4 V/µs

PWM comparator propagation delay time, PWM
comparator input to PH pin (excluding 10-mV overdrive
deadtime)

Enable threshold voltage, SS/ENA 0.82 1.2 1.4 V
Enable hysteresis voltage, SS/ENA
Falling edge deglitch, SS/ENA

(4)

(4)

Internal slow-start time 2.6 3.35 4.1 ms
Charge current, SS/ENA SS/ENA = 0 V 2 5 8 µA
Discharge current, SS/ENA SS/ENA = 0.2 V, VIN = 2.7 V, PVIN = 2.5 V 1.3 2.3 4 mA

Power-good threshold voltage VSENSE falling 93 %V
Power-good hysteresis voltage
Power-good falling edge deglitch
Output saturation voltage, PWRGD I

(4)

(4)

= 2.5 mA 0.18 0.3 V

(sink)

Leakage current, PWRGD VIN = 3.3 V, PVIN = 2.5 V 1 µA

Current limit VIN = 3.3 V, PVIN = 2.5 V
Current limit leading edge blanking time
Current limit total response time

Thermal shutdown trip point
Thermal shutdown hysteresis

(4)

(4)

Power MOSFET switches m Ω

(4)

(4)

VIN = 3 V, PVIN = 2.5 V 8 21
VIN = 3.6 V, PVIN = 2.5 V 8 18

90 110 dB

(4)

3 5 MHz
0 VBIAS V

60 250 nA

70 85 ns

0.03 V

2.5 µs

3 %V

35 µs

, Output shorted 14.5 21 A

100 ns
200 ns

135 165 ° C

10 ° C

ref
ref

(4) Specified by design

4

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1
2
3
4
5
6
7
8
9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

AGND

VSENSE

COMP

PWRGD

BOOT

PH
PH
PH
PH
PH
PH
PH
PH
PH

RT
SYNC
SS/ENA
VBIAS
VIN
PVIN
PVIN
PVIN
PVIN
PGND
PGND
PGND
PGND
PGND

THERMAL

PAD

TPS54073

SLVS547 – FEBRUARY 2005

DEVICE INFORMATION

PWP PACKAGE

(TOP VIEW)

TERMINAL FUNCTIONS

PIN NAME PIN NUMBER DESCRIPTION

AGND 1 RT resistor. If using the PowerPAD, connect it to AGND. See the Application Information section for

BOOT 5
COMP 3 Error amplifier output. Connect frequency compensation network from COMP to VSENSE

PGND copper areas to the input and output supply returns, and negative terminals of the input and output

PH 6-14 Phase output. Junction of the internal high-side and low-side power MOSFETs, and output inductor.
PVIN 20, 21, 22, 23

PWRGD 4
RT 28 Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency, fs.
SS/ENA 26

SYNC 27 or pin select between two internally set switching frequencies. When used to synchronize to an external

VBIAS 25

VIN 24
VSENSE 2 Error amplifier inverting input. Connect to output voltage compensation network/output divider.

15, 16, 17, 18,

19

Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, and
details.

Bootstrap output. 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating
drive for the high-side FET driver.

Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large
capacitors. A single point connection to AGND is recommended.

Input supply for the power MOSFET switches and internal bias regulator. Bypass the PVIN pins to the
PGND pins close to device package with a high-quality, low-ESR 10-µF ceramic capacitor.

Power-good open-drain output. High when VSENSE > 90% V
output is low when SS/ENA is low or the internal shutdown signal is active.

Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device
operation and capacitor input to externally set the start-up time.

Synchronization input. Dual function pin which provides logic input to synchronize to an external oscillator
signal, a resistor must be connected to the RT pin.

Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND
pin with a high-quality, low-ESR 0.1-µF to 1.0-µF ceramic capacitor.

Input supply for the internal control circuits. Bypass the VIN pin to the PGND pins close to device package
with a high-quality, low-ESR 1-µF ceramic capacitor.

, otherwise PWRGD is low. Note that

ref

5

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Falling

Edge

Deglitch

Enable

Comparator

1.2 V

VIN

2.95 V

Hysteresis: 0.03 V

2.5 µs

Falling

and

Rising

Edge

Deglitch

2.5 µs

VIN UVLO

Comparator

Hysteresis: 0.11 V

Internal/External

Slow-start

(Internal Slow-start Time = 3.35 ms

Reference

VREF = 0.891 V

−

+

Error

Amplifier

Thermal

Shutdown

150°C

SHUTDOWN

SS_DIS

PWM

Comparator

OSC

Leading

Edge

Blanking

100 ns

R Q
S

Adaptive Dead-Time

and

Control Logic

SHUTDOWN

8 mΩ

VIN

REG

VBIAS

PVIN

BOOT

VIN

PH

C

O

PGND

PWRGD

Falling

Edge

Deglitch

35 µs

VSENSE

SHUTDOWN

0.90 V

ref

Hysteresis: 0.03 Vref

Power-Good

Comparator

AGND

VBIAS

ILIM

Comparator

2.2 − 4.0 V

V

O

RT

COMPVSENSE

SS/ENA

TPS54073

8 mΩ

L

OUT

VIN

3.0 − 4.0 V

SYNC

Start−Up

Driver

Suppression

TPS54073

SLVS547 – FEBRUARY 2005

FUNCTIONAL BLOCK DIAGRAM

6

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TYPICAL CHARACTERISTICS

250

350

450

550

650

750

−40 0 25 85 125

T

J

− Junction Temperature − °C

f − Internally Set Oscillator Frequency − kHz

SYNC ≥ 2.5 V

SYNC ≤ 0.8 V

0

2

4

6

8

10

12

-40 -20 0 20 40 60 80 100

T - Junction Temperature - C

J

o

Drain-Source On-State Resistance - mW

VIN = 3.6 V,

PVIN = 2.5 V,

IO= 9 A

125

0

2

4

6

8

10

12

-40 -20

0 20 40 60 80

100 125

T - Junction Temperature - C

J

o

Drain-Source On-State Resistance - mW

VIN = 3.3 V,

PVIN = 2.5 V,

IO= 9 A

200

300

400

500

600

700

800

−40 0 25 85 125

T

J

− Junction Temperature − °C

f − Externally Set Oscillator Frequency − kHz

RT = 68 kΩ

RT = 100 kΩ

RT = 180 kΩ

0.885

0.887

0.889

0.891

0.893

0.895

−40 0 25 85 125

T

J

− Junction Temperature − °C

− Voltage Reference − V

V

ref

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

0 2 4 6 8 10 12 14 16

- Power Dissipation - W

P

D

I - Output Current - A

O

TA= 25oC

−20

0

20

40

60

80

100

120

140

1 100 1 k 1 M

−200

−180

−160

−140

−120

−100

−80

−60

−40

−20

0

10 10 k 100 k 10 M

f − Frequency − Hz

Gain − dB

Phase − Degrees

Phase

Gain

RL = 10 kΩ,
CL = 160 pF,
TA = 25°C

0.885

0.887

0.889

0.891

0.893

0.895

3 3.1 3.2 3.3 3.4 3.5 3.6

V

I

− Input Voltage − V

− Output Voltage Regulation − V
V

O

PVIN = 2.5 V

2.75

2.90

3.05

3.20

3.35

3.50

3.65

−40 0 25 85 125

T

J

− Junction Temperature − °C

Internal Slow-Start Time − ms

3.80
VIN = 3.3 V,
PVIN = 2.5 V

DRAIN-SOURCE ON-STATE DRAIN-SOURCE ON-STATE INTERNALLY SET OSCILLATOR

RESISTANCE RESISTANCE FREQUENCY

vs vs vs

JUNCTION TEMPERATURE JUNCTION TEMPERATURE JUNCTION TEMPERATURE

Figure 1. Figure 2. Figure 3.

TPS54073

SLVS547 – FEBRUARY 2005

EXTERNALLY SET OSCILLATOR

FREQUENCY VOLTAGE REFERENCE DEVICE POWER DISSIPATION

vs vs vs

JUNCTION TEMPERATURE JUNCTION TEMPERATURE OUTPUT CURRENT

Figure 4. Figure 5. Figure 6.

REFERENCE VOLTAGE INTERNAL SLOWS-START TIME

vs ERROR AMPLIFIER vs

INPUT VOLTAGE OPEN-LOOP RESPONSE JUNCTION TEMPERATURE

Figure 7. Figure 8. Figure 9.

7

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AGND

BOOT

VSENSE

COMP

PWRGD

PH

PH

PH

PH

PH

PH

PH

PH

PH

RT

SYNC

SS/ENA

VBIAS

VIN

PVIN

PVIN

PVIN

PVIN

PGND

PGND

PGND

PGND

PGND

VOUT

PH

PVIN

TOPSIDE GROUND AREA

VIA to Ground Plane

ANALOG GROUND TRACE

EXPOSED
POWERPAD
AREA

COMPENSATION
NETWORK

OUTPUT INDUCTOR

OUTPUT
FILTER
CAPACITOR

BOOT
CAPACITOR

INPUT
BYPASS
CAPACITOR

INPUT
BULK
FILTER

FREQUENCY SET RESISTOR

SLOW START
CAPACITOR

BIAS CAPACITOR

INPUT
BYPASS
CAPACITOR

VIN

OPTIONAL PRE-CHARGE DIODES

CONNECT TO PRE-CHARGE
VOLTAGE SOURCE

TPS54073

SLVS547 – FEBRUARY 2005

PCB LAYOUT

APPLICATION INFORMATION

The PVIN pins are connected together on the printed- ground side of the input and output filter capacitors.
circuit board (PCB) and bypassed with a low ESR The AGND and PGND pins are tied to the PCB
ceramic bypass capacitor. Care should be taken to ground by connecting them to the ground area under
minimize the loop area formed by the bypass capaci- the device as shown in Figure 10 . Use a separate
tor connections, the PVIN pins, and the TPS54073 wide trace for the analog ground signal path. This
ground pins. The minimum recommended bypass analog ground is used for the voltage set point
capacitance is a 10-µF ceramic capacitor with a X5R divider, timing resistor RT, slow-start capacitor, and
or X7R dielectric. The optimum placement is as close bias capacitor grounds. The PH pins are tied together
as possible to the PVIN pins, the AGND, and PGND and routed to the output inductor. Because the PH
pins. See Figure 10 for an example of a board layout. connection is the switching node, an inductor is
If the VIN is connected to a separate source supply, it located close to the PH pins, and the area of the PCB
is bypassed with its own capacitor. There is an area conductor is minimized to prevent excessive capaci­of ground on the top layer of the PCB, directly under tive coupling. Connect the boot capacitor between the
the IC, with an exposed area for connection to the phase node and the BOOT pin as shown in Fig-

Figure 10. TPS54073 Layout

PowerPAD. Use vias to connect this ground area to ure 10 . Keep the boot capacitor close to the IC, and
any internal ground planes. Use additional vias at the minimize the conductor trace lengths. Connect the

8