Texas Instruments TPS5211PWP, TPS5211PWPR Datasheet

TPS5211

HIGH FREQUENCY PROGRAMMABLE HYSTERETIC

REGULATOR CONTROLLER

SLVS243 – SEPTEMBER 1999

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

700 KHz Operation

D

1.25 MHz Operation With External Driver

D

1.5% Reference Over Full Operating
T emperature Range

D

Synchronous Rectifier Driver for Greater
Than 90% Efficiency

D

Programmable Reference V oltage Range of

1.3 V to 3.5 V

D

User–Selectable Hysteretic T ype Control

D

Droop Compensation for Improved Load
Transient Regulation

D

Adjustable Overcurrent Protection

D

Programmable Softstart

D

Overvoltage Protection

D

Active Deadtime Control

D

Power Good Output

D

Internal Bootstrap Schottky Diode

D

Low Supply Current . . . 3-mA T yp

D

Reduced System Component Count and
Size

description

The TPS521 1 is a hysteretic regulator controller which provides an accurate, programmable supply voltage to
microprocessors. An internal 5-bit DAC is used to program the reference voltage to within a range of 1.3 V to

3.5 V. The output voltage can be set to equal the reference voltage or some multiple of the reference voltage.
A hysteretic controller with user-selectable hysteresis and programmable droop compensation is used to
dramatically reduce overshoot and undershoot caused by load transients. Propagation delay from the
comparator inputs to the output drivers is less than 250 ns. Overcurrent shutdown and crossover protection for
the output drivers combine to eliminate destructive faults in the output FETs. The softstart current source is
proportional to the reference voltage, thereby eliminating variation of the softstart timing when changes are
made to the output voltage. PWRGD monitors the output voltage and pulls the open-collector output low when
the output drops 7% below the nominal output voltage. An overvoltage circuit disables the output drivers if the
output voltage rises 15% above the nominal value. The inhibit pin can be used to control power sequencing.
Inhibit and undervoltage lockout assures the 12-V supply voltage and system supply voltage (5 V or 3.3 V) is
within proper operating limits before the controller starts. Single-supply (12 V) operation is easily accomplished
using a low-current divider for the required 5-V signals. The output driver circuits include 2-A drivers with internal
8-V gate-voltage regulators. The high-side driver can be configured either as a ground-referenced driver or as
a floating bootstrap driver. The TPS521 1 is available in a 28-pin TSSOP PowerP AD package. It operates over
a junction temperature range of 0°C to 125°C.

AVAILABLE OPTIONS

PACKAGE

T

J

TSSOP

(PWP)

0°C to 125°C TPS5211PWPR

Copyright  1999, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1
2
3
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9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

IOUT

DROOP

OCP
VHYST
VREFB

VSENSE
ANAGND
SLOWST

BIAS

LODRV

LOHIB

DRVGND

LOWDR

DRV

PWRGD
VID0
VID1
VID2
VID3
VID4
INHIBIT
IOUTLO
LOSENSE
HISENSE
BOOTLO
HIGHDR
BOOT
V

CC

PWP PACKAGE

(TOP VIEW)

TPS5211

HIGH FREQUENCY PROGRAMMABLE HYSTERETIC

REGULATOR CONTROLLER

SLVS243 – SEPTEMBER 1999

2

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

•

11111

Decode

VID0
VID1
VID2
VID3
VID4

SQ

R

Deglitch

Deglitch

100 mV

+

V

OVP

1.15 V

ref

V

PGD

0.93 V

ref

Rising

Edge

Delay

–

+

+

–

PREREG

DRV REG

–

+

–

+

Hysteresis

Setting

–+

VID

MUX

and

Decoder

2x

SLOWST

OCP

INHIBIT

Bandgap Shutdown

I

VREFB

5

Shutdown

VSENSE

HIGHIN

HIGHDR

V

CC

Analog
Bias

Analog Bias

Slowstart
Comp

Hysteresis
Comp

CM Filters

VREF

–

+

Σ

28 20 21 1915 7

V

CC

ANAGND PWRGD LOSENSE IOUTLO HISENSE

2 V

10 V

V

CC

UVLO

NOCPU

Fault

Shutdown

IOUT

BIAS
DRV

BOOT
HIGHDR

BOOTLO

LOWDR
DRVGND

1

9
14

16
17

18

13
12

6

11 1042523

VID0 VID1 VID2 VID3 VID4

24252627

VREFB DROOP VHYST VSENSE LOHIB LODRV

8

3

22

200 kΩ

200 kΩ

I

VREFB

functional block diagram

TPS5211

HIGH FREQUENCY PROGRAMMABLE HYSTERETIC

REGULATOR CONTROLLER

SLVS243 – SEPTEMBER 1999

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

NAME NO.

I/O

DESCRIPTION

ANAGND 7 Analog ground
BIAS 9 O Analog BIAS pin. A 1-µF ceramic capacitor should be connected from BIAS to ANAGND.
BOOT 16 I Bootstrap. Connect a 1-µF low-ESR capacitor from BOOT to BOOTLO.
BOOTLO 18 O Bootstrap low. Connect BOOTLO to the junction of the high-side and low-side FETs for floating drive

configuration. Connect BOOTLO to PGND for ground reference drive configuration.

DROOP 2 I Droop voltage. Voltage input used to set the amount of output-voltage set-point droop as a function of load

current. The amount of droop compensation is set with a resistor divider between IOUT and ANAGND.
DRV 14 O Drive regulator for the FET drivers. A 1-µF ceramic capacitor should be connected from DRV to DR VGND.
DRVGND 12 Drive ground. Ground for FET drivers. Connect to FET PWRGND.
HIGHDR 17 O High drive. Output drive to high-side power switching FETs
HISENSE 19 I High current sense. For current sensing across high-side FETs, connect to the drain of the high-side FETs; for

optional resistor sensing scheme, connect to power supply side of current-sense resistor placed in series with

high-side FET drain.
INHIBIT 22 I Disables the drive signals to the MOSFET drivers. Can also serve as UVLO for system logic supply (either 3.3 V

or 5 V).
IOUT 1 O Current out. Output voltage on this pin is proportional to the load current as measured across the Rds(on) of the

high-side FETs. The voltage on this pin equals 2×R

ds(on)×IOUT. In applications requiring very accurate

current sensing, a sense resistor should be connected between the input supply and the drain of the high-side

FET s.
IOUTLO 21 O Current sense low output. This is the voltage on the LOSENSE pin when the high-side FETs are on. A ceramic

capacitor should be connected from IOUTLO to HISENSE to hold the sensed voltage while the high-side FET s

are off. Capacitance range should be between 0.033 µF and 0.1 µF.
LODRV 10 I Low drive enable. Normally tied to 5 V. To activate the low-side FETs as a crowbar , pull LODRV low.
LOHIB 11 I Low side inhibit. Connect to the junction of the high and low side FETs to control the anti-cross-conduction and

eliminate shoot-through current. Disabled when configured in crowbar mode.
LOSENSE 20 I Low current sense. For current sensing across high-side FETs, connect to the source of the high-side FET s; for

optional resistor sensing scheme, connect to high-side FET drain side of current-sense resistor placed in series

with high-side FET drain.
LOWDR 13 O Low drive. Output drive to synchronous rectifier FETs
OCP 3 I Over current protection. Current limit trip point is set with a resistor divider between IOUT and ANAGND.
PWRGD 28 O Power good. Power good signal goes high when output voltage is within 7% of voltage set by VID pins.

Open-drain output.
SLOWST 8 O Slowstart (soft start). A capacitor from SLOWST to ANAGND sets the slowstart time.

Slowstart current = I

VREFB

/5

V

CC

15 12-V supply. A 1-µF ceramic capacitor should be connected from VCC to DRVGND.

VHYST 4 I HYSTERESIS set pin. The hysteresis is set with a resistor divider from V

REFB

to ANAGND.

The hysteresis window = 2 × (V

REFB

– V

HYST

)
VID0 27 I Voltage identification input 0
VID1 26 I Voltage identification input 1
VID2 25 I Voltage identification input 2
VID3 24 I Voltage identification input 3
VID4 23 I Voltage Identification input 4. Digital inputs that set the output voltage of the converter. The code pattern for

setting the output voltage is located in T able 1. Internally pulled up to 5 V with a resistor divider biased from V

CC

.

VREFB 5 O Buffered reference voltage from VID network
VSENSE 6 I Voltage sense input. To be connected to converter output voltage bus to sense and control output voltage. It is

recommended an RC low pass filter be connected at this pin to filter noise.

TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER

SLVS243 – SEPTEMBER 1999

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

detailed description

V

REF

The reference/voltage identification (VID) section consists of a temperature-compensated bandgap reference
and a 5-bit voltage selection network. The 5 VID terminals are inputs to the VID selection network and are
TTL-compatible inputs internally pulled up to 5 V by a resistor divider connected to VCC. The VID codes conform
to the Intel

VRM 8.3 DC-DC Converter Specification

for voltage settings between 1.8 V and 3.5 V , and they are

decremented by 50 mV , down to 1.3 V, for the lower VID settings. V oltages higher than V

REF

can be implemented

using an external divider. Refer to T able 1 for the VID code settings. The output voltage of the VID network, V

REF

,
is within ±1.5% of the nominal setting over the VID range of 1.3 V to 2.5 V , including a junction temperature range
of 5°C to +125°C, and a VCC supply voltage range of 1 1.4 V to 12.6 V . The output of the reference/VID network
is indirectly brought out through a buffer to the V

REFB

pin. The voltage on this pin will be within 5mV of V

REF

.
It is not recommended to drive loads with V

REFB

, other than setting the hysteresis of the hysteretic comparator,

because the current drawn from V

REFB

sets the charging current for the slowstart capacitor. Refer to the

slowstart section for additional information.

hysteretic comparator

The hysteretic comparator regulates the output voltage of the synchronous-buck converter. The hysteresis is
set by 2 external resistors and is centered on V

REF

. The 2 external resistors form a resistor divider from V

REFB

to ANAGND, with the output voltage connecting to the VHYST pin. The hysteresis of the comparator will be
equal to twice the voltage

difference

between the VREFB and VHYST pins. The propagation delay from the

comparator inputs to the driver outputs is 250 ns (maximum). The maximum hysteresis setting is 60 mV.

low-side driver

The low-side driver is designed to drive low-Rds(on) n-channel MOSFETs. The current rating of the driver is
2 A, source and sink. The bias to the low-side driver is internally connected to the DRV regulator.

high-side driver

The high-side driver is designed to drive low-Rds(on) n-channel MOSFETs. The current rating of the driver is
2 A, source and sink. The high-side driver can be configured either as a ground-referenced driver or as a floating
bootstrap driver. When configured as a floating driver , the bias voltage to the driver is developed from the DR V
regulator. The internal bootstrap diode, connected between the DR V and BOOT pins, is a Schottky for improved
drive efficiency. The maximum voltage that can be applied between BOOT and DRVGND is 30 V. The driver
can be referenced to ground by connecting BOOTLO to DRVGND, and connecting BOOT to either DRV or VCC.
The rms current through the drivers output should not exceed 110 mA. Refer to the application information
section to determine how to calculate an operating frequency to meet this requirement.

deadtime control

Deadtime control prevents shoot-through current from flowing through the main power FETs during switching
transitions by actively controlling the turnon times of the MOSFET drivers. The high-side driver is not allowed
to turn on until the gate-drive voltage to the low-side FET s is below 2 V ; the low-side driver is not allowed to turn
on until the voltage at the junction of the high-side and low-side FETs (Vphase) is below 2 V.

TPS5211

HIGH FREQUENCY PROGRAMMABLE HYSTERETIC

REGULATOR CONTROLLER

SLVS243 – SEPTEMBER 1999

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

detailed description (continued)

current sensing

Current sensing is achieved by sampling and holding the voltage across the high-side power FETs while the
high-side FET s are on. The sampling network consists of an internal 60-Ω switch and an external ceramic hold
capacitor. Recommended value of the hold capacitor is between 0.033 µF and 0.1 µF. Internal logic controls
the turnon and turnoff of the sample/hold switch such that the switch does not turn on until the Vphase voltage
transitions high, and the switch turns off when the input to the high-side driver goes low . The sampling will occur
only when the high-side FETs are conducting current. The voltage on the IOUT pin equals 2 times the sensed
high-side voltage. In applications where a higher accuracy in current sensing is required, a sense resistor can
be placed in series with the high-side FETs, and the voltage across the sense resistor can be sampled by the
current sensing circuit.

droop compensation

The droop compensation network reduces the load transient overshoot/undershoot on V

O

, relative to V

REF

. V

O

is programmed to a voltage greater than V

REF

by an external resistor divider from VO to VSENSE to reduce the
undershoot on VO during a low-to-high load transient. The overshoot during a high-to-low load transient is
reduced by subtracting the voltage on DROOP from V

REF

. The voltage on IOUT is divided with an external

resistor divider, and connected to DROOP.

inhibit

INHIBIT is a TTL-compatible digital input used to enable the controller. When INHIBIT is low , the output drivers
are low and the slowstart capacitor is discharged. When INHIBIT goes high, the short across the slowstart
capacitor is released and normal converter operation begins. When the system-logic supply is connected to
INHIBIT, it also controls power sequencing by locking out controller operation until the system-logic supply
exceeds the input threshold voltage of the inhibit circuit. The 12-V supply and the system logic supply (either
5 V or 3.3 V) must be above UVLO thresholds before the controller is allowed to start up. The start threshold
is 2.1 V and the hysteresis is 100 mV for the INHIBIT comparator.

VCC undervoltage lockout (UVLO)

The undervoltage lockout circuit disables the controller while the VCC supply is below the 10-V start threshold
during power up. When the controller is disabled, the output drivers will be low and the slowstart capacitor is
discharged. When VCC exceeds the start threshold, the short across the slowstart capacitor is released and
normal converter operation begins. There is a 2-V hysteresis in the undervoltage lockout circuit for noise
immunity.

slowstart

The slowstart circuit controls the rate at which VO powers up. A capacitor is connected between SLOWST and
ANAGND and is charged by an internal current source. The current source is proportional to the reference
voltage, so that the charging rate of C

SLOWST

is proportional to the reference voltage. By making the charging

current proportional to V

REF

, the power-up time for VO will be independent of V

REF

. Thus, C

SLOWST

can remain

the same value for all VID settings. The slowstart charging current is determined by the following equation:

I

slowstart

= I(VREFB) / 5 (amps)
Where I(VREFB) is the current flowing out of VREFB.
It is recommended that no additional loads be connected to VREFB, other than the resistor divider for setting

the hysteresis voltage. The maximum current that can be sourced by the VREFB circuit is 500 µA. The equation
for setting the slowstart time is:

t

SLOWST

= 5 × C

SLOWST

× R

VREFB

(seconds)

Where R

VREFB

is the total external resistance from V

REFB

to ANAGND.

TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER

SLVS243 – SEPTEMBER 1999

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

detailed description (continued)

power good

The power-good circuit monitors for an undervoltage condition on VO. If VO is 7% below V

REF

, then the PWRGD

pin is pulled low. PWRGD is an open-drain output.

overvoltage protection

The overvoltage protection (OVP) circuit monitors V

O

for an overvoltage condition. If VO is 15% above V

REF

,

then a fault latch is set and both output drivers are turned off. The latch will remain set until V

CC

goes below the
undervoltage lockout value. A 3-µs deglitch timer is included for noise immunity. Refer to the LODRV section
for information on how to protect the microprocessor against overvoltages due to a shorted fault across the
high-side power FET.

overcurrent protection

The overcurrent protection (OCP) circuit monitors the current through the high-side FET. The overcurrent
threshold is adjustable with an external resistor divider between IOUT and ANAGND, with the divider voltage
connected to the OCP pin. If the voltage on OCP exceeds 100 mV , then a fault latch is set and the output drivers
are turned off. The latch will remain set until VCC goes below the undervoltage lockout value. A 3-µs deglitch
timer is included for noise immunity . The OCP circuit is also designed to protect the high-side power FET against
a short-to-ground fault on the terminal common to both power FETs.

drive regulator

The drive regulator provides drive voltage to the output drivers. The minimum drive voltage is 7 V . The minimum
short circuit current is 100 mA. Connect a 1-µF ceramic capacitor from DRV to DRVGND.

LODRV

The LODRV circuit is designed to protect the microprocessor against overvoltages that can occur if the high-side
power FETs become shorted. External components to sense an overvoltage condition are required to use this
feature. When an overvoltage fault occurs, the low-side FET s are used as a crowbar . LODR V is pulled low and
the low-side FET will be turned on, overriding all control signals inside the TPS5211 controller. The crowbar
action will short the input supply to ground through the faulted high-side FETs and the low-side FETs. A fuse
in series with Vin should be added to disconnect the short-circuit.

Table 1. Voltage Identification Codes

VID TERMINALS

(0 = GND, 1 = floating or pull-up to 5 V)

V

REF

VID4 VID3 VID2 VID1 VID0 (Vdc)

0 1 1 1 1 1.30
0 1 1 1 0 1.35
0 1 1 0 1 1.40
0 1 1 0 0 1.45
0 1 0 1 1 1.50
0 1 0 1 0 1.55
0 1 0 0 1 1.60
0 1 0 0 0 1.65
0 0 1 1 1 1.70
0 0 1 1 0 1.75
0 0 1 0 1 1.80
0 0 1 0 0 1.85
0 0 0 1 1 1.90

TPS5211

HIGH FREQUENCY PROGRAMMABLE HYSTERETIC

REGULATOR CONTROLLER

SLVS243 – SEPTEMBER 1999

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Table 1. Voltage Identification Codes (Continued)

VID TERMINALS

(0 = GND, 1 = floating or pull-up to 5 V)

V

REF

VID4 VID3 VID2 VID1 VID0 (Vdc)

0 0 0 1 0 1.95
0 0 0 0 1 2.00
0 0 0 0 0 2.05
1 1 1 1 1 No CPU
1 1 1 1 0 2.10
1 1 1 0 1 2.20
1 1 1 0 0 2.30
1 1 0 1 1 2.40
1 1 0 1 0 2.50
1 1 0 0 1 2.60
1 1 0 0 0 2.70
1 0 1 1 1 2.80
1 0 1 1 0 2.90
1 0 1 0 1 3.00
1 0 1 0 0 3.10
1 0 0 1 1 3.20
1 0 0 1 0 3.30
1 0 0 0 1 3.40
1 0 0 0 0 3.50

absolute maximum ratings over operating virtual junction temperature (unless otherwise noted)

†

Supply voltage range, V

CC

(see Note1) –0.3 V to 14 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range: BOOT to DRVGND (High-side Driver ON) –0.3 V to 30 V. . . . . . . . . . . . . . . . . . . . . . . . .

BOOT to HIGHDRV –0.3 V to 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

BOOT to BOOTLO –0.3 V to 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

INHIBIT, VIDx, LODRV –0.3 V to 7.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PWRGD, OCP, DROOP –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

LOHIB, LOSENSE, IOUTLO, HISENSE –0.3 V to 14 V. . . . . . . . . . . . . . . . . . . . . . . . . .

VSENSE –0.3 V to 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage difference between ANAGND and DRVGND ±0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output current, V

REFB

0.5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Short circuit duration, DRV Continuous. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating virtual junction temperature range, TJ 0°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: Unless otherwise specified, all voltages are with respect to ANAGND.

DISSIPATION RATING TABLE

PACKAGE

TA ≤ 25°C

POWER RATING

DERATING FACTOR

ABOVE TA = 25°C

TA = 70°C

POWER RATING

TA = 85°C

POWER RATING

PWP 1 150 mW 11.5 mW/°C 630 mW 460 mW

TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER

SLVS243 – SEPTEMBER 1999

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

recommended operating conditions

MIN MAX UNIT

Supply voltage, V

CC

11.4 13 V

Input voltage, BOOT to DRVGND 0 28 V

Input voltage, BOOT to BOOTLO 0 13 V
Input voltage, INHIBIT, VIDx, LODRV , PWRGD, OCP, DROOP 0 6 V
Input voltage, LOHIB, LOSENSE, IOUTLO, HISENSE 0 13 V
Input voltage, VSENSE 0 4.5 V
Voltage dif ference between ANAGND and DRVGND 0 ±0.2 V
Output current, V

REFB

†

0 0.4 mA

†

Not recommended to load V

REFB

other than to set hystersis since I

VREFB

sets slowstart time.

electrical characteristics over recommended operating virtual junction temperature range,
V

CC

= 12 V, I

DRV

= 0 A (unless otherwise noted)

reference/voltage identification

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

REF

Cumulative reference accuracy
(see Note 2)

VCC = 11.4 to 12.6 V, 1.3 V ≤ V

REF

≤ 3.5 V –0.015 0.015 V/V

VIDx High-level input voltage 2.25 V
VIDx Low-level input voltage 1 V

Output voltage I

VREFB

= 50 µA V

REF

–5mV V

REFVREF

+5mV V

V

REFB

Output regulation 10 µA ≤ IO ≤ 500 µA 2 mV
Input resistance VIDx = 0 V 36 73 95 kΩ

VID

x

Input pull-up voltage divider 4.8 4.9 5 V

NOTES: 2. Cumulative reference accuracy is the combined accuracy of the reference voltage and the input offset voltage of the hysteretic

comparator. Cumulative accuracy equals the average of the high-level and low-level thresholds of the hysteretic comparator.

3. This parameter is ensured by design and is not production tested.

power good

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Undervoltage trip threshold 90 93 95 %V

REF

V

OL

Low-level output voltage IO = 5 mA 0.5 0.75 V

I

OH

High-level input current V

PWRGD

= 6 V 1 µA

V

hys

Hysteresis voltage 1.3 2.9 4.5 %V

REF

slowstart

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Charge current

V

SLOWST

= 0.5 V,

I

VREFB

= 65 µA

V

VREFB

= 1.3 V,

10.4 13 15.6 µA

Discharge current V

SLOWST

= 1 V 3 mA
Comparator input offset voltage 10 mV
Comparator input bias current See Note 3 10 100 nA
Comparator hysteresis –7.5 7.5 mV

NOTE 3: This parameter is ensured by design and is not production tested.

TPS5211

HIGH FREQUENCY PROGRAMMABLE HYSTERETIC

REGULATOR CONTROLLER

SLVS243 – SEPTEMBER 1999

9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating virtual junction temperature range,
V

CC

= 12 V, I

DRV

= 0 A (unless otherwise noted) (continued)

hysteretic comparator

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Input offset voltage V

DROOP

= 0 V (see Note 3) –2.5 2.5 mV
Input bias current See Note 3 500 nA
Hysteresis accuracy V

REFB

– V

HYST

= 15 mV

(Hysteresis window = 30 mV)

–3.5 3.5 mV

Maximum hysteresis setting V

REFB

– V

HYST

= 30 mV 60 mV

NOTE 3: This parameter is ensured by design and is not production tested.

high-side VDS sensing

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Gain 2 V/V
Initial accuracy

V

HISENSE

= 12 V, V

LOSENSE

= 11.9 V,

Differential input to Vds sensing amp = 100 mV

194 206 mV

IOUTLO Sink current 5 V ≤ V

IOUTLO

≤ 13 V 250 nA

IOUT Source current

V

IOUT

= 0.5 V, V

HISENSE

= 12 V,

V

IOUTLO

= 11.5 V

500 µA

IOUT Sink current

V

IOUT

= 0.05 V, V

HISENSE

= 12 V,

V

IOUTLO

= 12 V

50 µA

V

HISENSE

= 11 V, R

IOUT

= 10 kΩ 0 2 V

Output voltage swing

V

HISENSE

= 4.5 V, R

IOUT

= 10 kΩ

0 1.5 V

V

HISENSE

= 3 V, R

IOUT

= 10 kΩ 0 0.75 V

High-level input voltage

2.85 V

LOSENSE

Low-level input voltage

V

HISENSE

= 4.5 V

(see Note 3)

2.4 V

11.4 V ≤ V

HISENSE

≤ 12.6 V,
LOSENSE connected to HISENSE,
V

HISENSE

– V

IOUTLO

= 0.15 V

50 60 80

Sample/hold resistance

4.5 V ≤ V

HISENSE

≤ 5.5 V,
LOSENSE connected to HISENSE,
V

HISENSE

– V

IOUTLO

= 0.15 V

62 85 123

Ω

3 V ≤ V

HISENSE

≤ 3.6 V,
LOSENSE connected to HISENSE,
V

HISENSE

– V

IOUTLO

= 0.15 V

67 95 144

CMRR

V

HISENSE

= 12.6 V to 3 V,

V

HISENSE

– V

OUTLO

= 100 mV

69 75 dB

NOTE 3. This parameter is ensured by design and is not production tested.

inhibit

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Start threshold 1.9 2.1 2.35 V
Hysteresis 0.08 0.1 0.12 V
Stop threshold 1.85 V

TPS5211
HIGH FREQUENCY PROGRAMMABLE HYSTERETIC
REGULATOR CONTROLLER

SLVS243 – SEPTEMBER 1999

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating virtual junction temperature range,
V

CC

= 12 V, I

DRV

= 0 A (unless otherwise noted) (continued)

overvoltage protection

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Overvoltage trip threshold 112 115 120 %V

REF

Hysteresis See Note 3 10 mV

NOTE 3: This parameter is ensured by design and is not production tested.

overcurrent protection

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

OCP trip threshold 90 100 110 mV
Input bias current 100 nA

deadtime

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

High-level input voltage 2.4

LOHIB

Low-level input voltage 1.4

V

High-level input voltage See Note 3 3

LOWDR

Low-level input voltage See Note 3 1.7

V

NOTE 3: This parameter is ensured by design and is not production tested.

LODRV

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

High-level input voltage 1.85

LODRV

Low-level input voltage 0.95

V

droop compensation

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Initial accuracy V

DROOP

= 50 mV 46 54 mV

drive regulator

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Output voltage 11.4 V ≤ VCC ≤ 12.6 V, I

DRV

= 120 mA 7 9 V

Output regulation 1 mA ≤ I

DRV

≤ 50 mA 100 mV

Short-circuit current 120 mA

bias regulator

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Output voltage 11.4 V ≤ VCC ≤ 12.6 V, See Note 4 6 V

NOTE 4: The bias regulator is designed to provide a quiet bias supply for the TPS5211 controller. External loads should not be driven by the bias

regulator.

input undervoltage lockout

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Start threshold 9.25 10 10.75 V
Hysteresis 1.9 2 2.2 V
Stop threshold 7.5 V