Texas Instruments TPS51640A, TPS59640, TPS59641 Schematic [ru]

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TPS51640

VCC_CPU

VCC_GFX

Processor

3-phase CPU

Controller

IMVP-7

SVID Interface

1-phase GPU

Controller

TPS51601 FET Driver

CPU Power Stage

TPS51601 FET Driver

Internal

FET Driver

Internal

FET Driver

GPU Power Stage

UDG-11062

TPS51640A, TPS59640, TPS59641

www.ti.com

SLUSAQ2 –JANUARY 2012

Dual-Channel (3-Phase CPU/1-Phase GPU) SVID, D-CAP+™ Step-Down Controller for

IMVP-7 V

FEATURES

• Intel IMVP-7 Serial VID (SVID) Compliant

with Two Integrated Drivers

CORE

• Supports CPU and GPU Outputs

• CPU Channel 1, 2, or 3 Phase

• Single-Phase GPU Channel

• Full IMVP-7 Mobile Feature Set Including

Digital Current Monitor

• 8-Bit DAC with 0.250-V to 1.52-V Output Range

• Optimized Efficiency at Light and Heavy Loads

• V

Overshoot Reduction (OSR)

CORE

Undershoot Reduction (USR)

CORE

• Accurate, Adjustable Voltage Positioning

• 8 Independent Frequency Selections per

Channel (CPU/GPU)

• Patent Pending AutoBalance™ Phase Balancing

• Selectable 8-Level Current Limit

• 3-V to 28-V Conversion Voltage Range

• Two Integrated Fast FET Drivers w/Integrated

Boost FET

• Internal Driver Bypass Mode for Use with DrMOS Devices

• Small 6 × 6 , 48-Pin, QFN, PowerPAD™ Package

DESCRIPTION

The TPS51640A, TPS59640 and TPS59641 are dual-channel, fully SVID compliant IMVP-7 step-down controllers with two integrated gate drivers. Advanced control features such as D-CAP™+ architecture with overlapping pulse support (undershoot reduction, USR) and overshoot reduction (OSR) provide fast transient response, lowest output capacitance and high efficiency. All of these controllers also support single-phase operation for light loads. The full compliment of IMVP-7 I/O is integrated into the controllers including dual PGOOD signals, ALERT and VR_HOT. Adjustable control of V and voltage positioning round out the IMVP-7 features. In addition, the controllers' CPU channel includes two high-current FET gate drivers to drive high-side and low-side N-channel FETs with exceptionally high speed and low switching loss. The TPS51601 or TPS51601A driver is used for the third phase of the CPU and the GPU channel.

The BOOT voltage (V

) on the TPS51640A and

BOOT

TPS59640 is 0 V. The TPS59641 is specifically designed for a V

level of 1.1 V.

BOOT

These controllers are packaged in a space saving, thermally enhanced 48-pin QFN. The TPS51640A is rated to operate from –10°C to 105°C. The TPS59640 and TPS59641 are rated to operate from –40°C to 105°C.

CORE

slew rate

APPLICATIONS

• IMVP-7 V Battery, NVDC or 3 V/5 V/12 V rails

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2D-CAP+, PowerPAD, D-CAP are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Applications for Adapter,

CORE

SIMPLIFIED APPLICATION

TPS51640A, TPS59640, TPS59641

SLUSAQ2 –JANUARY 2012

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

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(1)(2)

Green (RoHS and

no Sb/Br)

250

2500

PACKAGE PINS ECO PLAN

BOOT

–10°C to 105°C 0

Plastic Quad Flat

Pack (QFN)

–40°C to 105°C

1.1

ORDERING INFORMATION

(V) NUMBER MEDIA QUANTITY

0 48 Tape-and-reel

ORDERABLE TRANSPORT MINIMUM

TPS51640ARSLT 250 TPS51640ARSLR 2500

TPS59640RSLT 250 TPS59640RSLR 2500

TPS59641RSLT

TPS59641RSLTR

(3)

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com. (2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. (3) Product preview. Not currently available.

ABSOLUTE MAXIMUM RATINGS

(1)(2)

over operating free-air temperature range (unless otherwise noted)

MIN TYP MAX UNIT

VBAT –0.3 32 CSW1, CSW2 –6.0 32 V CDH1 to CSW1; CDH2 to CSW2; CBST1 to CSW1; CBST2 to CSW2 –0.3 6.0

Input voltage

CTHERM, CCOMP, CF-IMAX, GF-IMAX, GCOMP, GTHERM, V5DRV, V5

COCP-I, CCSP1, CCSP2, CCSP3, CCSN1, CCSN2, CCSN3, CVFB, CGFB, V3R3, VR_ON, VCLK, VDIO, SLEWA, GGFB, GVFB, GCSN, –0.3 3.6 GCSP, GOCP-I,

PGND –0.3 0.3 VREF –0.3 1.8

Output voltage CPGOOD, ALERT, VR_HOT, GPGOOD, CIMON, GIMON –0.3 3.6 V

CPWM3, CSKIP, GPWM, GSKIP, CDL1, CDL2 –0.3 6.0

Electrotatic discharge

Operating junction temperature, T Storage temperature, T

stg

(HBM) QSS 009-105 (JESD22-A114A) 1.5 kV (CDM) QSS 009-147 (JESD22-C101B.01) 500 V

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to the network ground terminal unless otherwise noted.

–0.3 6.0

-40 125 °C

-55 150 °C

TPS51640A, TPS59640, TPS59641

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THERMAL INFORMATION

THERMAL METRIC

JCtop

JCbot

JT JB

Junction-to-ambient thermal resistance 31.7 Junction-to-case (top) thermal resistance 19.8 Junction-to-board thermal resistance 7.1 Junction-to-top characterization parameter 0.3 Junction-to-board characterization parameter 7.1 Junction-to-case (bottom) thermal resistance 2.1

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(1)

RECOMMENDED OPERATING CONDITIONS

MIN TYP MAX UNIT

VBAT –0.1 28 CSW1, CSW2 –3.0 30 CDH1 to CSW1; CDH2 to CSW2; CBST1 to CSW1; CBST2 to

CSW2 V5DRV, V5 4.5 5.5 V3R3 3.1 3.5

Input voltage CCOMP, GCOMP –0.1 2.5 V

CTHERM, GTHERM 0.1 3.6 CF-IMAX, GF-IMAX, COCP-I, GOCP-I 0.1 1.7 CCSP1, CCSP2, CCSP3, CCSN1, CCSN2, CCSN3, CVFB, CGFB,

GGFB, GVFB, GCSN, GCSP, VR_ON, VCLK, VDIO, SLEWA, –0.1 3.5 PGND –0.1 0.1 VREF –0.1 1.72

Output voltage V

CIMON, GIMON –0.1 V CPGOOD, ALERT, VR_HOT, GPGOOD, –0.1 V CPWM3, CSKIP, GPWM, GSKIP, CDL1, CDL2, –0.1 V

Operating free air temperature, T

TPS59640,TPS59641 –40 105

TPS51460A –10 105

–0.1 5.5

–0.1 1.7

SLUSAQ2 –JANUARY 2012

TPS51640A

TPS59640 TPS59641

RSL

48 PINS

UNITS

°C/W

VREF

V3R3

°C

TPS51640A, TPS59640, TPS59641

SLUSAQ2 –JANUARY 2012

ELECTRICAL CHARACTERISTICS

over recommended free-air temperature range, VV5= V (Unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SUPPLY: CURRENTS, UVLO AND POWER-ON RESET

V5-4

V5-3

V5-2

V5-PS3

V5STBY

UVLOH

UVLOL

V3R3

V3R3SBY

3UVLOH

3UVLOL

V5 supply current CPU: 3-phase active GPU: 1-phase active

V5 supply current CPU: 2-phase active GPU: 1-phase active

V5 supply current CPU: 1-phase IV5+ I active GPU: 1-phase active

V5 supply current CPU: 3-phase active GPU: 1-phase active

V5DRV standby current VR_ON = ‘LO’, IV5+ I V5 UVLO 'OK' Threshold Ramp up, VR_ON=’HI’, 4.25 4.4 4.5 V V5 UVLO fault threshold Ramp down, VR_ON = ’HI’, 3.95 4.2 4.3 V V3R3 supply current SVID bus idle, VR_ON = ‘HI’ 0.5 1.0 mA V3R3 standby current VR_ON = ‘LO’ 10 µA V3R3 UVLO 'OK' threshold Ramp up, VR_ON=’HI’, 2.5 2.9 3.0 V V3R3 UVLO fault threshold Ramp down, VR_ON = ’HI’, 2.4 2.7 2.8 V

IV5+ I VR_ON = ‘HI’

IV5+ I VR_ON = ‘HI’, V

VR_ON = ‘HI’, V IV5+ I

VR_ON = ‘HI’, SetPS = PS3 5.1 mA (Note: 3-phase CPU goes to 1-phase in PS3)

REFERENCES: DAC, VREF, VBOOT AND DRVL DISCHARGE FOR BOTH CPU AND GPU

BOOT

VIDSTP

Boot voltage

VID step size 5 mV

0.25 ≤ V I

DAC1

xVFB tolerance no load active

xPU_CORE

0.25 ≤ V I

xPU_CORE

–40°C ≤ TA≤ 105°C

1.000V ≤ V I

DAC4

VREF

VREFSRC

VREFSNK

DLDQ

xVFB tolerance above 1 V VID

VREF Output 4.5 V ≤ VV5≤ 5.5 V, I VREF output source 0 µA ≤ I VREF output sink –500 µA ≤ I DRVL discharge threshold Soft-stop transistor turns on at this point. 200 300 mV

xPU_CORE

1.000V ≤ V I

xPU_CORE

–40°C ≤ TA≤ 105°C

VOLTAGE SENSE: xVFB AND xGFB FOR BOTH CPU AND GPU

xVFB

xGFB

GAINGND

xVFB input bias current V xGFB input bias current V

xVFB xVFB

xGFB/GND gain 1 V/V

CURRENT MONITOR

CiMONLK

CIMONLO

CIMONMID

CIMONHI

Zero level current output Σ∆CS = 0 mV, AIMON = 12 × (1+1.27) 35 mV Low level current output Σ∆CS = 15.6 mV, AIMON = 12 × (1+1.27) 425 mV Mid level current output Σ∆CS = 31.1 mV, AIMON = 12 × (1+1.27) 850 mV High level current output Σ∆CS = 62.3 mV, AIMON = 12 × (1+1.27) 1700 mV

ZERO-CROSSING

Inductor zero crossing threshold voltage

, V

V5DRV

, V

V5DRV

, V

V5DRV

, V

V5DRV

xVFB

= 0 A, 0°C ≤ TA≤ 85°C

xVFB

= 0 A, –6 8.3

xVFB

= 0 A, 0°C ≤ TA≤ 85°C

xVFB

= 0 A, –0.65% 1.0%

VREF

=2 V, V =2 V, V

V5DRV

VDAC

CCSP3

VDAC

CCSP3

VDAC

= 5.0 V; V

< V

xVFB

< V

xVFB

=3.3 V

< V

xVFB

= V

CCSP2

< V

xVFB

V5DRV

< (V

V3R3

VDAC

= 3.3 V

VDAC

= 3.3 V; V

+ 100 mV),

TPS59640

TPS51640A

TPS59641 1.1

≤ 0.995V,

TPS51640A –5 5

TPS59640 TPS59641

≤ 1.520 V,

TPS51640A –0.5% 0.5%

TPS59640 TPS59641

= 0 A 1.70 V

VREF

≤ 500 µA –4 –0.1 mV

≤ 0 µA 0.1 4 mV

=0 V 20 40 µA

xGFB

=0 V -40 -20 µA

xGFB

= V

PGND

= V

, V

GND

xVFB

6.0 9.0 mA

5.5 mA

4.9 mA

10 20 µA

0 V

0 mV

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= V

CORE

TPS51640A, TPS59640, TPS59641

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ELECTRICAL CHARACTERISTICS (continued)

over recommended free-air temperature range, VV5= V (Unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

CURRENT SENSE: OVERCURRENT, ZERO CROSSING, VOLTAGE POSITIONING AND PHASE BALANCING

= 20 kΩ

xOCP-I

= 24 kΩ

xOCP-I

= 30 kΩ

xOCP-I

= 39 kΩ

xOCP-I

OCPP

IMAX

xVFBDQ

M-DROOP

BAL_TOL

CSINT

OCP voltage (valley current limit)

= 56 kΩ

xOCP-I

= 75 kΩ

xOCP-I

= 100 kΩ

xOCP-I

= 150 kΩ

xOCP-I

IMAX values both channels

IMAX_MIN

IMAX

IMAX_MAX

= 133 mV, value of xIMAX,

= V

REF

= 653mV, value of xIMAX 98 A CS pin input bias current CSPx and CSNx –1.0 0.2 1.0 µA xVFB input bias current,

discharge

Droop amplifier transconductance

Internal current share tolerance –3% +3%

End of soft-stop, xVFB = 100mV 90 125 180 µA

xVFB = 1 V µS

– V

CSP1 CSP3

– V

CSN1

CSN3

Internal current sense gain Gain from CSPx – CSNx to PWM comparator 11.65 12.00 12.30 V/V

V5DRV

× I

MAX

) = (V ) = V

= 5.0 V; V

/ 255

– V

CSP2

OCPP_MIN

CSN2

V3R3

= 3.3 V; V

xGFB

= V

PGND

= V

TPS51640A 5.1 7.0 9.7

TPS59640 TPS59641

4.6 7.0 9.7

TPS51640A 8.1 10.0 12.6

TPS59640 TPS59641

7.6 10.0 13.1

TPS51640A 12.1 14.0 16.7

TPS59640 TPS59641

11.6 14.0 17.2

TPS51640A 17.1 19.0 21.7

TPS59640 TPS59641

16.6 19.0 22.2

TPS51640A 23.1 25.0 27.9

TPS59640 TPS59641

22.6 25.0 28.4

TPS51640A 29.7 32.0 35.0

TPS59640 TPS59641

29.2 32.0 35.5

TPS51640A 37.9 40.0 43.3

TPS59640 TPS59641

37.4 40.0 43.8

TPS51640A 46.8 49.0 52.6

TPS59640 TPS59641

46.2 49.0 53.1

TPS51640A 486 497 518

TPS59640 TPS59641

480 497 518

) =

SLUSAQ2 –JANUARY 2012

, V

xVFB

= V

CORE

GND

20 A

TPS51640A, TPS59640, TPS59641

SLUSAQ2 –JANUARY 2012

ELECTRICAL CHARACTERISTICS (continued)

over recommended free-air temperature range, VV5= V (Unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

TIMERS: SLEW RATE, ISLEW, ADDR, ON-TIME AND I/O TIMING

STARTUP1

STRTSTP

SET

PGDDGLTO

PGDDGLTU

TON_CPU

Start-up time time from VR_ON until the controller responds to 5 ms

xVFB slew soft-start / soft-stop 1.25 1.50 1.75 mV/µs

Slew rate setting V

xPGOOD deglitch time 5 100 µs

xPGOOD deglitch time 150 500 µs

CPU on-time RCF=39 kΩ, V

BOOT

SVID commands SLEWRATE = 12mV/µs, VR_ON goes ‘HI’,

VR_ON goes ‘LO = ‘Soft-stop’ VSLEWA ≤ 0.30V (Also disables SVID CLK timer) 10.0 12.0 14.5 V

SLEWA

0.75 V ≤ V

SLEWA

Time from xVFB out of +220 mV VDAC boundary to xPGOOD low.

Time from xVFB out of –315 mV VDAC boundary to xPGOOD low.

RCF=20 kΩ, V (250 kHz)

RCF=24 kΩ, V (300 kHz)

RCF=30 kΩ, V (350 kHz)

(400 kHz)

RCF=56 kΩ, V (450 kHz)

RCF=75 kΩ, V (500 kHz)

RCF=100 kΩ, V RCF=150 kΩ, V

V5DRV

> 0 V, SLEWRATE = 12 mV/µs, no faults,

= 0.4 V 3.5 4.0 5.0 = 0.6 V 7.5 8.5 9.5

≤ 0.85 V 10.0 12.0 14.5

SLEWA

= 1.0 V 16 mV/µs = 1.2 V 20 = 1.4 V 23 = 1.6 V 26 ≥ 2.50 V 26

=12 V, V

BAT

=12 V, V

BAT

=12 V, V

BAT

=12 V, V

BAT

=12 V, V

BAT

=12 V, V

BAT

BAT BAT

= 5.0 V; V

=12 V, V =12 V, V

= 3.3 V; V

V3R3

DAC

=1.1 V

TPS51640A 270 327 375

TPS59640 TPS59641

DAC

=1.1 V

TPS51640A 225 272 320

TPS59640 TPS59641

DAC

=1.1 V

TPS51640A 185 235 280

TPS59640 TPS59641

=1.1 V ns

DAC

TPS51640A 160 207 252

TPS59640 TPS59641

DAC

=1.1 V

TPS51640A 140 185 231

TPS59640 TPS59641

DAC

=1.1 V

TPS51640A 120 167 212

TPS59640 TPS59641

=1.1 V (550 kHz) 109 152 198

DAC

=1.1 V (600 kHz) 105 140 177

DAC

xGFB

= V

PGND

= V

GND

265 327 380

220 272 325

180 235 285

155 207 262

134 185 241

115 167 217

, V

xVFB

= V

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CORE

TPS51640A, TPS59640, TPS59641

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ELECTRICAL CHARACTERISTICS (continued)

over recommended free-air temperature range, VV5= V (Unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

TIMERS: SLEW RATE, ISLEW, ADDR, ON-TIME AND I/O TIMING (Continued)

RGF=20 kΩ, V (275 kHz)

RGF=24 kΩ, V (330 kHz)

RGF=30 kΩ, V (385 kHz)

TON_GPU

MIN

VCCVID

VRONPGD

PGDVCC

VRTDGLT

SFTSTP

PROTECTION: OVP, UVP PGOOD, VR_HOT, ‘FAULTS OFF’ AND INTERNAL THERMAL SHUTDOWN

OVPH

PGDH

PGDL

THERM

THRM

INT

HYS

GPU on-time

RGF=39 kΩ,V (440 kHz)

RGF=56 kΩ, V (495 kHz)

RGF=75 kΩ, V RGF=100 kΩ, V RGF=150 kΩ, V

Controller minimum off time Fixed value 150 200 ns

ACK of SetVID-x command to start of voltage

VID change to xVFB change

(1)

ramp VR_ON low to xPGOOD low 20 50 100 ns xPGOOD low to xVFB change

(1)

VR_HOT# deglitch time 0.2 0.7 ms Soft-stop transistor resistance Connect to CVFB, GVFB 550 770 1100 Ω

Fixed OVP voltage threshold voltage

xPGOOD high threshold 190 220 245 mV

xPGOOD low threshold –348 –315 –280 mV

VCSN1 or VGCSN > V

Measured at the xVFB pin wrt/VID code,

device latches OFF

Measured at the xVFB pin wrt/VID code,

device latches OFF

bit0 of xTHERM register = high 757 783 808

bit1 of xTHERM register also is high 651 680 707

bit2 of xTHERM register also is high 611 638 663

bit3 of xTHERM register also is high 570 598 623 IMVP-7 thermal bit voltage

definition

bit4 of xTHERM register also is high 531 559 583

bit5 of xTHERM register also is high 496 523 548

bit6 of xTHERM register also is high,

ALERT goes low

bit7 of XTHERM register also is high,

VR_HOT goes low

CDLx goes low, CDHx goes low 373 410 425 THERM current Leakage current –5 5 µA Internal controller thermal

Shutdown Controller thermal SD

hysteresis

(1)

Latch off controller 155 °C

Cooling required before converter can be reset 20 °C

V5DRV

BAT

BAT BAT

= 5.0 V; V

=12 V, V

=12 V, V =12 V, V

OVPH

DAC

V3R3

=1.1 V

= 3.3 V; V

TPS51640A 315 347 388

TPS59640

xGFB

= V

TPS59641

DAC

=1.1V

TPS51640A 251 287 330

TPS59640 TPS59641

DAC

=1.1 V

TPS51640A 215 245 287

TPS59640 TPS59641

DAC

=1.1 V

TPS51640A 180 216 252

TPS59640 TPS59641

DAC

=1.1 V

TPS51640A 160 190 223

TPS59640 TPS59641

=1.1 V (550 kHz) 145 171 210

DAC

=1.1 V (605 kHz) 120 156 205

DAC

=1.1 V (660 kHz) 100 150 201

DAC

for 1 µs, DRVL → ON 1.68 1.72 1.77 V

SLUSAQ2 –JANUARY 2012

= V

, V

PGND

GND

xVFB

= V

CORE

310 347 393

246 287 335

210 245 292 ns

175 216 257

155 190 228

2 µs

100 ns

461 488 513

428 455 481

(1) Specified by design. Not production tested.

TPS51640A, TPS59640, TPS59641

SLUSAQ2 –JANUARY 2012

ELECTRICAL CHARACTERISTICS (continued)

over recommended free-air temperature range, VV5= V (Unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

LOGIC (VCLK, VDIO, ALERT, VR_HOT, VR_ON) INTERFACE PINS: I/O VOLTAGE AND CURRENT

RSVIDL

RPGDL

VRTTLK

HYST

VR_ONL

VR_ONH

Open drain pull down resistance 4 8 13 Ω Open drain pull down resistance xPGOOD pull-down resistance at 0.31 V 36 50 Open drain leakage current -2 0.2 2 µA Input logic low 0.45 V

Input logic high 0.65 V Hysteresis voltage

(1)

VR_ON logic low 0.3 V VR_ON logic high 0.8 V I/O 3.3 V leakage Leakage current , V

OVERSHOOT AND UNDERSHOOT REDUCTION (OSR/USR) THRESHOLD SETTING

OSR

USR

OSR_OFF

OSRHYS

OSR voltage set mV

USR voltage set mV

OSR OFF setting V OSR/USR voltage hysteresis

(2) Specified by design. Not production tested.

VDIO, ALERT, VR_HOT, pull-down resistance at

0.31 V

VR_HOT, xPGOOD, Hi-Z leakage,

apply 3.3-V in off state

VCLK, VDIO

= 20 kΩ 106

xSKIP

= 24 kΩ 156

xSKIP

= 30 kΩ 207

xSKIP

= 39 kΩ 257

xSKIP

= 56 kΩ 308

xSKIP

= 75 kΩ 409

xSKIP

= 100 kΩ 510

xSKIP

= 150 kΩ 610

xSKIP

= 20 kΩ 40

xSKIP

= 24 kΩ 60

xSKIP

= 30 kΩ 75

xSKIP

= 39 kΩ 115

xSKIP

= 56 kΩ 153

xSKIP

= 75 kΩ 190

xSKIP

= 100 kΩ 230

xSKIP

≥ 150 kΩ = OFF –

xSKIP

at start up 100 300 mV

xSKIP

(2)

All settings 20%

V5DRV

= 5.0 V; V

= 1.1 V 10 25.0 µA

VR_ON

V3R3

= 3.3 V; V

xGFB

= V

PGND

= V

, V

GND

xVFB

0.05 V

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= V

CORE

TPS51640A, TPS59640, TPS59641

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ELECTRICAL CHARACTERISTICS (continued)

over recommended free-air temperature range, VV5= V (Unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DRIVERS: HIGH-SIDE, LOW-SIDE, CROSS CONDUCTION PREVENTION AND BOOST RECTIFIER

– V

DRVH

DRVH ON resistance Ω

DRVH

DRVL

NONOVLP

DS(on)

BSTLK

DRVH sink/source current

(3)

DRVH transition time CDHx 10% to 90% or 90% to 10%, C

DRVL ON resistance Ω

DRVL sink/source current

(3)

DRVL transition time ns

Driver non overlap time ns

BST on-resistance (V BST switch leakage current V

CDHx

‘HI’ State, (V

‘LO’ State, (V

CDLx

CSWx

CDLx falls to 1 V to CDHx rises to 1 V 13 25

VBST

PWM and SKIP OUTPUT: I/O Voltage and Current

PWML

PWMH

SKIPL

SKIPH

PW(leak)

xPWMy output low level 0.7 V xPWMy output high level 4.2 V SKIP output low level 0.7 V xSKIP output high level 4.2 V xPWM leakage Tri-state, V = 5 V 0.1 µA

(3) Specified by design. Not production tested.

CBSTx VBST

CBSTx DRVH

V5DRV

CSWx

– V

VDRVH

– V

CSWx

– VLL) = 0.25 V = 2.5 V, (V = 2.5 V, (V

= 2.5 V, Source 2.7 A = 2.5 V, Sink 6 A 90% to 10%, C 10% to 90%, C

falls to 1 V to V

– V

VBST

= 34 V, V

V5DRV

= 5.0 V; V

V3R3

= 3.3 V; V

xGFB

) = 5 V, ‘HI’ state,

) = 0.25 V

) = 5 V, ‘LO’ state,

– V

) = 5 V, Source 2.2 A

CSWx

– V

) = 5 V, Sink 2.2 A

CSWx

= 3 nF

CDHx

) = 0.25 V 0.9 2 )= 0.2 V 0.4 1

PGND

= 3 nF 15 40 = 3 nF 15 40

rises to 1 V 13 25

V5DRV

VDRVL

CBSTx CBSTx

– V

VDRVL

CDLx CDLx

CDLx

), IF= 5 mA 5 10 20 Ω

=28 V 0.1 1 µA

CSWx

= V

PGND

SLUSAQ2 –JANUARY 2012

= V

, V

xVFB

= V

GND

1.2 2.5

0.8 2.5

15 40 ns 15 40 ns

CORE

CTHERM

COCP-I

CIMON

CCSP1

CCSN1

CCSN2

CCSP2

CCSP3

CCSN3

CVFB

CCOMP

CGFB

CF-IMAX

VREF

V3R3

VR_ON

CPGOOD

VCLK

ALERT

VDIO

VR_HOT

SLEWA

GPGOOD

GF-IMAX

CPWM3

CSKIP

GPWM

GSKIP

GTHERM

GOCP-I

GIMON

GCSP

GCSN

GCOMP

GVFB

GGFB

CDH1

CBST1

CSW1

CDL1

V5DRV

PGND

CDL2

CSW2

CBST2

CDH2

VBAT

TPS51640A

TPS59640 TPS59641

TPS51640A, TPS59640, TPS59641

SLUSAQ2 –JANUARY 2012

www.ti.com

DEVICE INFORMATION

RSL PACKAGE

48 PINS

(TOP VIEW)

PIN FUNCTIONS

NAME NO.

ALERT 19 O SVID interrupt line, open drain. Route between VCLK and VDIO to prevent cross-talk. CBST1 46 I Top N-channel FET bootstrap voltage input for CPU phase 1. CBST2 39 I Top N-channel bootstrap voltage input for CPU phase 2. CCSN1 5 CCSN2 6 I CCSN3 9 CCOMP 10 O Output of GM error amplifier for the CPU converter. A resistor to VREF sets the droop gain. CCSP1 4 CCSP2 7 I or inductor DCR sense network. Tie CCSP3, 2 or 1 (in that order) to V3R3 to disable the phase. Tie CCSP1 to CCSP3 8 CDH1 47 O Top N-channel FET gate drive output for CPU phase 1. CDH2 38 O Top N-channel FET gate drive output for CPU phase 2. CDL1 44 O Synchronous N-channel FET gate drive output for CPU phase 1. CDL2 41 O Synchronous N-channel FET gate drive output for CPU phase 2.

I/O DESCRIPTION

Negative current sense inputs for the CPU converter. Connect to the most negative node of current sense resistor or inductor DCR sense network. CCSN1 has a secondary OVP comparator.

Positive current sense inputs for the CPU converter. Connect to the most positive node of current sense resistor V3R3 to run the GPU converter only.

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TPS51640A, TPS59640, TPS59641

SLUSAQ2 –JANUARY 2012

NAME NO.

I/O DESCRIPTION

Voltage divider to VREF. A resistor to GND sets the operating frequency of the CPU converter. The voltage level

CF-IMAX 13 I sets the maximum operating current of the CPU converter. The IMAX value is an 8-bit A/D where V

/ 255. Both are latched at start-up.

MAX

CGFB 12 I

CIMON 3 O

COCP-I 2 I

Voltage sense return tied for the CPU converter. Tie to GND with a 10-Ω resistor to close feedback when the microprocessor is not in the socket.

Analog current monitor output for the CPU converter. V 220-nF capacitor to GND for stability.

Resistor to GND (R voltage divider to CIMON. Resistor ratio sets the IMON gain (see CIMON pin description).

) selects 1 of 8 OCP levels (per phase, latched at start-up) of the CPU converter. Also,

COCP

= ΣVCS× ACS × (1 + R

CIMON

CIMON/RCOCP

= V

IMAX

REF

). Connect a

CPGOOD 17 O IMVP-7_PWRGD output for the CPU converter. Open-drain. CSW1 45 I/O Top N-channel FET gate drive return for CPU phase 1. CSW2 40 I/O Top N-channel FET gate drive return for CPU phase 2. CPWM3 36 O PWM control for the external driver, 5V logic level.

CSKIP 35 O

CTHERM 1 I/O

CVFB 11 I

Skip mode control of the external driver for the CPU converter. A logic HI = FCCM, LO = SKIP. R to GND selects 1 of 8 OSR/USR levels. 0.1 V < V

< 0.3 V at start-up turns OSR off.

CSKIP

Thermal sensor connection for the CPU converter. A resistor connected to VREF forms a divider with an NTC thermistor connected to GND.

Voltage sense line tied directly to V feedback when µP is not in the socket. The soft-stop transistor is on this pin

of the CPU converter. Tie to V

CORE

with a 10-Ω resistor to close

CORE

Negative current sense input for the GPU converter. Connect to the most negative node of current sense resistor

GCSN 28 I or inductor DCR sense network. GCSN has a secondary OVP comparator and includes the soft-stop pull-down

transistor.

GCSP 29 I

Positive current sense input for the GPU converter. Connect to the most positive node of current sense resistor or inductor DCR sense network. Tie to V3R3 to disable the GPU converter.

GCOMP 27 O Output of gMerror amplifier for the GPU converter. A resistor to VREF sets the droop gain. GGFB 25 I

Voltage sense return tied for the GPU converter. Tie to GND with a 10-Ω resistor to close feedback when the microprocessor is not in the socket.

24 I Voltage divider to VREF. R to GND sets the operating frequency of the GPU converter. The voltage level sets

GF-IMAX the maximum operating current of the GPU converter. The IMAX value is an 8-bit A/D where V

/ 255. Both are latched at start-up.

MAX

GIMON

GOCP-I

30 O Analog current monitor output for the GPU converter. V

220-nF capacitor to GND for stability.

31 I Voltage divider to GIMON. Resistor ratio sets the IMON gain (see GIMON pin). Resistor to GND (R

1 of 8 OCP levels (per phase, latched at start-up) of the GPU converter.

GIMON

= V

ISENSE

× (1 + R

GIMON/RGOCP

= V

IMAX

REF

). Connect a

GOCP

) selects

GPGOOD 23 O IMVP-7_PWRGD output for the GPU converter. Open-drain. GPWM 34 O PWM control for the external driver, 5-V logic level.

GSKIP

GTHERM

GVFB

33 O Skip mode control of the external driver for the GPU converter, 5-V logic level. Logic HI = FCCM, LO = SKIP. R

to GND selects 1 of 8 OSR/USR levels. 0.1 V < V

< 0.3 V at start-up turns OSR off.

GSKIP

32 I/O Thermal sensor input for the GPU converter. A resistor connected to VREF forms a divider with an NTC

thermistor connected to GND.

26 I Voltage sense line tied directly to V

when the microprocessor is not in the socket. The soft-stop transistor is on this pin

of the GPU converter. Tie to V

GFX

with a 10-Ω resistor to close feedback

GFX

PGND 42 – Synchronous N-channel FET gate drive return. SLEWA

V5DRV

22 I The voltage at start-up sets 1 of 7 slew rates for both converters. The SLOW rate is SLEWRATE/4. Soft-start

and soft-stop rates are SLEWRATE/8. This value is latched at start-up. Tie to GND to disable SCLK timer.

48 I 5-V power input for analog circuits; connect through resistor to 5-V plane and bypass to GND with ≥1 µF ceramic

capacitor

43 I Power input for the gate drivers; connected with an external resistor to V5F; decouple with a ≥2.2 µF ceramic

capacitor.

V3R3 15 I 3.3-V power input; bypass to GND with ≥1 µF ceramic cap. VBAT

37 I Provides VBAT information to the on-time circuits for both converters. A 10-kΩ series resistor protects the

adjacent pins from inadvertent shorts due to solder bridges or mis-probing during test. VCLK 18 I SVID clock. 1-V logic level. VDIO 20 I/O SVID digital I/O line. 1-V logic level. VREF 14 O 1.7-V, 500-µA reference. Bypass to GND with a 0.22-µF ceramic capacitor.

TPS51640A, TPS59640, TPS59641

SLUSAQ2 –JANUARY 2012

www.ti.com

NAME NO.

VR_ON 16 I IMVP-7 VR enable; 1V I/O level; 100-ns de-bounce. Regulator enters controlled soft-stop when brought low. VR_HOT PAD GND – Thermal pad and analog circuit reference; tie to a quiet area in the system ground plane with multiple vias.

I/O DESCRIPTION

21 O IMVP-7 thermal flag open drain output – active low. Typically pulled up to 1-V logic level through 56 Ω. Fall time

< 100 ns. 1-ms de-glitch using consecutive 1-ms samples.

0.80

0.85

0.90

0.95

1.00

1.05

Output Voltage (V)

VIN= 9 V VIN= 20 V Nominal

Specified Maximum

Specified Minimum

VID

= 1.05 V

0 10 20 90 100

Output Current (A)

30 40 50 70 8060

0.500

0.525

0.575

0.600

0.625

0.675

0.700

0 2 4 18 20

Output Current (A)

Output Voltage (V)

6 8 10 14 1612

VIN= 9 V VIN= 20 V Nominal

Specified Maximum

Specified Minimum

VID

= 0.6 V

0.550

0.650

Efficiency (%)

VID

= 0.6 V

VIN= 9 V VIN= 20 V

0 2 4 18 20

Output Current (A)

6 8 10 14 1612

Efficiency (%)

VID

= 1.05 V

VIN= 9 V VIN= 20 V

0 10 20 90 100

Output Current (A)

30 40 50 70 8060

100

150

200

350

400

Frequency (Hz)

0 10 20 90 100

Output Current (A)

30 40 50 70 8060

RCF= 24 kW

PS0, V

VID

= 1.05 V, VIN= 9 V

PS0, V

VID

= 1.05 V, VIN= 20 V

PS1, V

VID

= 1.05 V, VIN= 20 V

PS1, V

VID

= 1.05 V, VIN= 9 V

250

300

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TPS51640A, TPS59640, TPS59641

SLUSAQ2 –JANUARY 2012

TYPICAL CHARACTERISTICS

3-Phase Configuration, 94-A CPU

Figure 1. Output Voltage vs. Load Current in PS0 Figure 2. Output Voltage vs. Load Current in PS1

Figure 3. Efficiency vs. Load Current in PS0 Figure 4. Efficiency vs. Load Current in PS1

Figure 5. Frequency vs Load-Current (PS0 and PS1) Figure 6. Switching Ripple in PS0, VIN= 20 V

TPS51640A, TPS59640, TPS59641

SLUSAQ2 –JANUARY 2012

TYPICAL CHARACTERISTICS

3-Phase Configuration, 94-A CPU (continued)

Figure 7. Start-Up and PGOOD Figure 8. Soft-Stop

(TPS51640A and TPS59640 Only)

www.ti.com

Figure 9. Load Transient, VIN= 9 V, Load step = 66 A Figure 10. Load Transient, VIN= 20 V, Load step = 66 A

Figure 11. Load Insertion, VIN= 9 V, Load step = 66 A Figure 12. Load Release, VIN= 20 V, Load step = 66 A

100 1000 10000 100000 1000000

−50

−40

−30

−20

−10

−225

−180

−135

−90

−45

135

180

225

Frequency (Hz)

Magnitude (dB)

Phase (°)

Gain Phase

3−Phase CPU V

OUT

= 1.05 V

OUT

~ 20 A

0.0005

0.001

0.0015

0.002

0.0025

0.003

0.0035

0.004

0.0045

-80

-60

-40

-20

100 1 k 10 k 100 k 1 M

Frequency (Hz)

OUT

Magnitude (W)

OUT

Phase (°)

Magnitude Target Phase

CPU

3-Phase

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TPS51640A, TPS59640, TPS59641

SLUSAQ2 –JANUARY 2012

TYPICAL CHARACTERISTICS

3-Phase Configuration, 94-A CPU (continued)

Figure 13. Dynamic VID: SetVID-Slow/SetVID-Slow Figure 14. Dynamic VID: SetVID-Fast/SetVID-Fast

Figure 15. SetVID-Decay/SetVID-Fast Figure 16. PS Change PS0 to PS1 Toggle

Figure 17. CPU Bode Plot Figure 18. Output Impedance

0.80

0.85

0.90

0.95

1.00

1.05

1.10

Output Voltage (V)

0 10 20

Output Current (A)

30 40 50 60

VID

= 1.05 V

VIN= 9 V VIN= 20 V Nominal

Specified Maximum

Specified Minimum

Efficiency (%)

0 5 10 50 55

Output Current (A)

15 20 25 40 4535

VIN= 9 V VIN= 20 V

VID

= 1.05 V

TPS51640A, TPS59640, TPS59641

SLUSAQ2 –JANUARY 2012

TYPICAL CHARACTERISTICS

2-Phase Configuration, 53-A CPU

Figure 19. Output Voltage Vs. Load Current in PS0 Figure 20. Efficiency Vs. Load Current in PS0

www.ti.com

Figure 21. Switching Ripple in PS0 (Persistence), Figure 22. Switching Ripple in PS0 (Persistence),

Figure 23. Switching Ripple in PS0, VIN= 9 V Figure 24. Switching Ripple in PS0, VIN= 20 V

VIN= 9 V VIN= 20 V

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TPS51640A, TPS59640, TPS59641

SLUSAQ2 –JANUARY 2012

TYPICAL CHARACTERISTICS

2-Phase Configuration, 53-A CPU (continued)

Figure 25. Load Transient, VIN= 9 V, Load Step = 43 A Figure 26. Load Transient, VIN= 20 V, Load Step = 43 A

Figure 27. Load Insertion, VIN= 9 V, Load Step = 43 A, Figure 28. Load Release, VIN= 20 V, Load Step = 43 A,

Figure 29. Load Insertion, VIN= 9 V, Load Step = 43 A, Figure 30. Load Release,VIN= 20 V, Load Step = 43 A,

OSR/USR Setting 39 kΩ (Reduced Output Capacitance) OSR/USR Setting 39 kΩ (Reduced Output Capacitance)

OSR/USR Setting 150 kΩ) OSR/USR Setting 150 kΩ)

0.0005

0.001

0.0015

0.002

0.0025

0.003

0.0035

0.004

0.0045

-80

-60

-40

-20

100 1 k 10 k 100 k 1 M

Frequency (Hz)

OUT

Magnitude (W)

OUT

Phase (°)

Magnitude Target Phase

CPU

2-Phase

TPS51640A, TPS59640, TPS59641

SLUSAQ2 –JANUARY 2012

TYPICAL CHARACTERISTICS

2-Phase Configuration, 53-A CPU (continued)

Figure 31. Dynamic VID: SetVID-Slow/SetVID-Slow Figure 32. Dynamic VID: SetVID-Fast/SetVID-Fast

www.ti.com

Figure 33. Dynamic VID: SetVID-Decay/SetVID-Fast, Figure 34. Dynamic VID: SetVID-Decay/SetVID-Fast,

Figure 35. PS Change PS0 to PS1 Toggle Figure 36. Output Impedance

= 2 A I

LOAD

= 0.5 A

1.050

1.100

1.125

1.150

1.175

1.200

1.250

Output Voltage (V)

0 5 10

Output Current (A)

20 25 30 35

VID

= 1.23 V

VIN= 9 V VIN= 20 V Nominal

Specified Maximum

Specified Minimum

1.225

1.075

0.500

0.525

0.575

0.600

0.625

0 2 4 18 20

Output Current (A)

Output Voltage (V)

6 8 10 14 1612

0.550

0.650

VIN= 9 V VIN= 20 V Nominal

Specified Maximum

Specified Minimum

VID

= 0.6 V

Efficiency (%)

VIN= 9 V

VIN= 20 V

VID

= 1.23 V

0 5 10

Output Current (A)

20 25 30 3515

Efficiency (%)

0 2 4 18 20

Output Current (A)

6 8 10 14 1612

VIN= 9 V VIN= 20 V

VID

= 0.6 V

100

150

200

350

400

Frequency (Hz)

0 5 10

Output Current (A)

3515 25 3020

250

300

RGF= 30 kW

PS0, V

VID

= 1.23 V, VIN= 9 V

PS0, V

VID

= 1.23 V, VIN= 20 V

PS1, V

VID

= 0.06 V, VIN= 20 V

PS1, V

VID

= 0.06 V, VIN= 9 V

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TPS51640A, TPS59640, TPS59641

SLUSAQ2 –JANUARY 2012

TYPICAL CHARACTERISTICS

1-Phase Configuration, 33-A GPU

Figure 37. Output Voltage Vs. Load Current in PS0 Figure 38. Output Voltage Vs. Load Current in PS1

Figure 39. Efficiency Vs. Load Current in PS0 Figure 40. Efficiency Vs. Load Current in PS1

Figure 41. Frequency Vs. Load Current Figure 42. Switching Ripple in PS0

TPS51640A, TPS59640, TPS59641

SLUSAQ2 –JANUARY 2012

TYPICAL CHARACTERISTICS

1-Phase Configuration, 33-A GPU (continued)

Figure 43. Start-Up and PGOOD Figure 44. Soft-Stop

(TPS51640A and TPS59640 Only)

www.ti.com

Figure 45. Load Transient, VIN= 9 V, Load Step = 20 A Figure 46. Load Transient, VIN= 20 V, Load Step = 20 A

Figure 47. Load Insertion, VIN= 9V, Load Step = 20 A Figure 48. Load Release, VIN= 20 V, Load Step = 20 A

100 1000 10000 100000 1000000

−50

−40

−30

−20

−10

−225

−180

−135

−90

−45

135

180

225

Frequency (Hz)

Magnitude (dB)

Phase (°)

Gain Phase

GPU V

OUT

= 1.05 V

OUT

~ 10 A

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TPS51640A, TPS59640, TPS59641

SLUSAQ2 –JANUARY 2012

TYPICAL CHARACTERISTICS

1-Phase Configuration, 33-A GPU (continued)

Figure 49. Dynamic VID: SetVID-Slow/SetVID-Slow Figure 50. Dynamic VID: SetVID-Fast/SetVID-Fast

Figure 51. Dynamic VID: SetVID-Decay/SetVID-Fast, Figure 52. Dynamic VID: SetVID-Decay/SetVID-Fast,

= 0.5 A I

LOAD

Figure 53. Bode Plot

LOAD

= 2 A

11CVFB

12CGFB

4CCSP1

5CCSN1

6CCSP2

7CCSN2

14VREF

16VR_ON

17CPGOOD

18VCLK

19ALERT

20VDIO

21VR_HOT

23GPGOOD

SLEWA

CIMON

GIMON

CTHE RM32GTHERM

COCP-I

GOCP-I

CF-IMAX

GF-IMAX

GVFB

GGFB29GCSP

GCSN

GCOM P

DAC0

Acs

8CCSP3

9CCSN3

Acs

Current

Sharing

Circuitry

CCOMP

Ramp

Comparator

SVID

Interface

DAC0

and

DAC1

OSR/USR

Phase

Manager

CPWM1 CPWM2 CPWM3

+ +

On-Time

CF-IMAX

ISHARE

CLK

CLK1

CLK2

CLK3

CPU

Logic Protection

and Status Circuitry

GPU

Logic Protection

and Status Circuitry

COCP

CPx

CVD

ISUM

IS1 IS2 IS3

GVD

DAC1

Acs

+ +

CLK

Smart Driver

Error

Amplifier

Integrator

Error

Amplifier

Integrator

On-Time

GOCP

GPx

GVD

1GFx

Ramp

Comparator

43 V5DRV

46 CBST1

47 CDH1

42 PGND

CBST2

38 CDH2

45 CSW1

44 CDL1

40 CSW2

41 CDL2

36 CPWM3

35 CSKIP

33 GSKIP

34 GPWM

VBAT

GF-IMAX

DAC0

DAC1

IS3

IS2

IS1

Pad

GND15V3R348V5

GPWM

USR

OSR

UDG-11271

TPS51640A, TPS59640, TPS59641

SLUSAQ2 –JANUARY 2012

TYPICAL CHARACTERISTICS (TPS59641 ONLY)

www.ti.com

Figure 54. Startup to V

Voltage and ALERT Figure 55. Startup to V

BOOT

Voltage and CPGOOD,

BOOT

GPGOOD

FUNCTIONAL BLOCK DIAGRAM

CPU_VSNS

CCSP3

CCSP2

CCSN1

CCSP1

COCP-I

GFX_VSNS

GSCP

GIMON

VREF

GPGOOD

VDIO

ALERT

CPGOOD

VR_ON

GPWM

VCLK

VREF

COCP

-I

VBAT

CSKIP

SVID:ALERT

SVID:CLK

VIN

CCSP

CCSN

3R3V

VREF

VR_HOT

VCLK

VREF

CPU_GSNS

VREF

CCSN2

CCSN3

GSKIP

CIMON

VDIO

CPWM

CIMON

VREF

SVID:DATA

VIN

CCSN

CCSP

GFX_GSNS

GSCN

GOCP-I

V5DRV

ALERT

V5DRV

I_TDC

= 21.5A

I_TDC

= 52A

GOCP

-I

VREF

To CPU SVID

Loadline

= 1.9mohm

Frequency setting

= 300

kHz

I_cc_max

= 33A

I_CC_max

= 94A

I_DYN

_max

= 66A

VCC_CORE

VREF

VCCIO

GFX

: GT2

CPU

: QC

Min. Over Current Limit

= 112

Loadline

= 3.9mohm

Frequency setting

= 385

kHz

I_DYNAMIC

= 20.2A

Note

VR_HOT

, CPGOOD and GPGOOD are open drain outputs

If used

, they would need pull

-up resistors

Min. Over Current Limit

= 37A

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TPS51640A, TPS59640, TPS59641

SLUSAQ2 –JANUARY 2012

APPLICATION INFORMATION

Figure 56. Application for 3-Phase CPU, 1-Phase GPU with Inductor DCR Current Sense (Controller with

2 internal drivers, 1st and 2nd Phase CPU Power)

GSKIP

GPWM V5

GCSN

VIN

GCSP

VGFX_CORE

CSKIP

CPWM3 V5

VCC_CORE

GCSN

VIN

GCSP

TPS51640A, TPS59640, TPS59641

SLUSAQ2 –JANUARY 2012

Figure 57. Application for 3-Phase CPU, 1-Phase GPU with Inductor DCR Current Sense continued

(External driver, 3rd Phase CPU Power)

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Figure 58. Application for 3-Phase CPU, 1-Phase GPU with Inductor DCR Current Sense continued

(External driver, GPU Power)

CPU_VSNS

CCSP2

CCSN1

CCSP1

COCP-I

VREF

VDIO

ALERT

CPGOOD

VR_ON

VCLK

VREF

COCP

-I

VBAT

SVID:ALERT

SVID:CLK

VIN

CCSP

CCSN

3R3V

VREF

VR_HOT

VCLK

VREF

3R3V

CPU_GSNS

VREF

CCSN2

3R3V

CIMON

VDIO

CIMON

VREF

SVID:DATA

VIN

CCSN

CCSP

V5DRV

ALERT

V5DRV

I_TDC

= 36A

To CPU SVID

Loadline

= 1.9mohm

Frequency setting

= 300

kHz

I_CC_max

= 53A

I_DYN

_max

= 43A

VCC_CORE

VREF

VCCIO

CPU

: SV

Note

VR_HOT and CPGOOD are open drain outputs

If used

, they would need pull

-up resistors

Min. Over Current Limit

= 65A

GFX

: External

. GPU Not used

Note

R19 = 39k (OSR

/USR

)

if 3x470

uF bulk is used

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TPS51640A, TPS59640, TPS59641

SLUSAQ2 –JANUARY 2012

Figure 59. Application for Inductor DCR Current Sense Application Diagram for 2-Phase CPU and GPU

Disabled

TPS51640A, TPS59640, TPS59641

SLUSAQ2 –JANUARY 2012

Table 1. Key External Component Recommendations

FUNCTION MANUFACTURER COMPONENT NUMBER

High-side MOSFET Texas Instruments CSD17302Q5A Low-side MOSFET Texas Instruments CSD17303Q5 Powerblock MOSFET Texas Instruments CSD87350Q5D

Panasonic ETQP4LR36AFC NEC-Tokin

Inductors

TOKO ALPS GLMDR3601A

Panasonic EEFLXOD471R4

Bulk Output Capacitors Sanyo 2TPLF470M4E

KEMET T528Z477M2R5AT Murata GRM21BR60J106KE19L

Ceramic Output Capacitors

NTC Thermistors

Sense Resistors

Murata GRM21BR60J226ME39L Panasonic ECJ2FB0J106K Panasonic ECJ2FB0J226K

Murata Panasonic ERTJ1VS104F, ERTJ0ES104F

Vishay WSK0612L7500FEA Stackpole CSSK0612FTL750

www.ti.com

MPCH1040LR36, MPCG1040LR36

FDUE1040J-H-R36, FCUL1040xxR36

NCP15WF104F03RC, NCP18WF104F03RC

DETAILED DESCRIPTION

Functional Overview

The TPS51640A, TPS59640, and TPS59641 are a DCAP+™ mode adaptive on-time controllers. The output voltage is set using a DAC that outputs a reference in accordance with the 8-bit VID code defined in

Intel IMVP-7 PWM Specification document. In adaptive on-time converters, the controller varies the on-time as a function of input and output voltage to maintain a nearly constant frequency during steady-state conditions. In conventional voltage-mode constant on-time converters, each cycle begins when the output voltage crosses to a fixed reference level. However, in these devices, the cycle begins when the current feedback reaches an error voltage level which corresponds to the amplified difference between the DAC voltage and the feedback output voltage. In the case of two-phase or three-phase operation, the current feedback from all the phases is summed up at the output of the internal current-sense amplifiers.

This approach has two advantages:

• The amplifier DC gain sets an accurate linear load-line; this is required for CPU core applications.

• The error voltage input to the PWM comparator is filtered to improve the noise performance.

In addition, the difference of the DAC-to-output voltage and the current feedback goes through an integrator to give a more or less linear load-line even at light loads where the inductor current is in discontinuous conduction mode (DCM).

In a steady-state condition, the phases of the TPS51640A, TPS59640, and TPS59641 switch 180° phase-displacement for two-phase mode and 120° phase-displacement for three-phase mode. The phase displacement is maintained both by the architecture (which does not allow both high-side gate drives to be on in any condition except transients) and the current ripple (which forces the pulses to be spaced equally). The controller forces current sharing adjusting the on-time of each phase. Current balancing requires no user intervention, compensation, or extra components.

TPS51640A, TPS59640, TPS59641

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User Selections

After the 5-V and the 3.3-V power are applied to the controller, the controller must be enabled by the VR_ON signal going high to the VCCIO logic level. At this time, the following information is latched and cannot be changed anytime during operation. The ELECTRICAL CHARACTERISTICS table defines the values of each of the selections.

• Operating Frequency. The resistor from CF-IMAX pin to GND sets the frequency of the CPU channel. The resistor from GF-IMAX to GND sets the frequency of the GPU channel. See the ELECTRICAL

CHARACTERISTICS table for the resistor settings corresponding to each frequency selection. It is to be

noted that the operating frequency is a quasi-fixed frequency in the sense that the ON time is fixed based on the input voltage (at the VBAT pin) and output voltage (set by VID). The OFF time varies based on various factors such as load and power-stage components.

• Maximum Current Limit (I

voltage on the CF-IMAX pin. The I the GF-IMAX pin.

• Overcurrent Protection (OCP) Level. The resistor from COCP-I to GND sets the OCP level of the CPU channel. The resistor from GOCP-I to GND sets the OCP level of the GPU channel.

• Current Monitor (IMON) Gain and Voltage. The resistor from CIMON to COCP-I sets the CIMON gain and the CIMON voltage for the CPU channel. The resistor from GIMON to GOCP-I sets the GIMON gain and the GIMON voltage for the GPU channel.

• Overshoot Reduction (OSR) and Undershoot Reduction (USR) Levels. The resistor from the CSKIP pin to GND sets the OSR and USR for the CPU channel. The resistor from the GSKIP pin to GND sets the OSR and USR level for GPU channel. The OSR can be disabled for CPU and/or GPU by setting a voltage of approximately 200 mV on the corresponding xSKIP pin. This is accomplished by connecting a resistor from VREF to the xSKIP pin.

• Slew Rate. The SetVID-Fast slew rate is set by the voltage on the SLEWA pin. The rate is the same for both the CPU and GPU channels. The SetVID-Slow is ¼ of the SetVID-Fast rate.

) Information. The I

CC(max)

information of the CPU, which can be set by the

information of the GPU channel, which can be set by the voltage on

SLUSAQ2 –JANUARY 2012

CPU (Active Phases)

GPU (Active Phases)

Table 2. Key Selections Summary

SELECTION

RESISTANCE (kΩ)

20 Lowest Lowest 24

30 39 56 75

100 150 Highest Highest

(1) See ELECTRICAL CHARACTERISTICS table for complete settings and values.

FREQUENCY OCP OSR / USR

Rising Rising Rising

(1)

Table 3. Active Channels and Phases

CCSP1 CCSN1 CCSP2 CCSN2 CCSP3 CCSN3 GCSP CGSN

3 CS CS CS CS CS CS n/a n/a 2 CS CS CS CS 3.3 V GND n/a n/a 1 CS CS 3.3 V GND GND GND n/a n/a

OFF 3.3 V GND GND GND GND GND n/a n/a

1 n/a n/a n/a n/a n/a n/a CS CS

OFF n/a n/a n/a n/a n/a n/a 3.3 V GND

Least overshoot, least undershoot

Maximum overshoot,

maximum undershoot

SW_CLK

COMP

Phase 1

Phase 2

Phase 3

SUM

CORE

Time

UDG-11031

TPS51640A, TPS59640, TPS59641

SLUSAQ2 –JANUARY 2012

PWM Operation

Referring to the FUNCTIONAL BLOCK DIAGRAM and Figure 60, in continuous conduction mode, the converter operates as shown in Figure 60.

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Figure 60. D-CAP+ Mode Basic Waveforms

Starting with the condition that the hig-side FETs are off and the low-side FETs are on, the summed current feedback (I

) is higher than the error amplifier output (V

SUM

COMP

). I

falls until it reaches the V

SUM

COMP

level, which contains a component of the output ripple voltage. The PWM comparator senses where the two waveform values cross and triggers the on-time generator. This generates the internal SW_CLK. Each SW_CLK corresponds to one switching ON pulse for one phase.

During single-phase operation, every SW_CLK generates a switching pulse on the same phase. Also, I

SUM

voltage corresponds to just a single-phase inductor current. During multi-phase operation, the SW_CLK is distributed to each of the phases in a cycle. Using the summed

inductor current and then cyclically distributing the ON-pulses to each phase automatically yields the required interleaving of 360/N, where N is the number of phases.

Current Sensing

The TPS51640A, TPS59640 and TPS59641 provide independent channels of current feedback for every phase. This increases the system accuracy and reduces the dependence of circuit performance on layout compared to an externally summed architecture. The current sensing topology can be Inductor DCR Sensing, which yields the best efficiency, or Resistor Current Sensing, which provides the most accuracy across wide temperature range. DCR sensing can be optimized by using a NTC thermistor to reduce the variation of current sense with temperature.

The pins CCSP1, CCSN1, CCSP2, CCSN2 and CCSP3, CCSN3 are used for the three phases of the CPU channel. The pins GCSP and GCSN are used for the single-phase GPU channel.

DROOP

VID

DROOP

= RLLx I

Slope of Loadline R

UDG-11032

( )

´ ´

= ´ =

CS CC

CS eff

DROOP LL CC

DROOP M

R A I

V R I

R G

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Setting the Load-line (DROOP)

TPS51640A, TPS59640, TPS59641

SLUSAQ2 –JANUARY 2012

Figure 61. Load Line

where

• ACS is the gain of the current sense amplifier

• R

is the effective current sense resistance, whether a sense resistor or inductor DCR is used

CS(eff)

• ICCis the load current

• R

is the value of resistor from the DROOP pin to VREF

DROOP

• GMis the gain of the droop amplifier (1)

Load Transients

When there is a sudden load increase, the output voltage immediately drops. This is reflected as a rising voltage on the COMP pin. This forces the PWM pulses to come in sooner and more frequent which causes the inductor current to rapidly increase. As the inductor current reaches the new load current, a steady-state operating condition is reached and the PWM switching resumes the steady-state frequency.

When there is a sudden load release, the output voltage rises. This is reflected as a falling voltage on the COMP pin. This delays the PWM pulses until the inductor current reaches the new load current level. At that point, switching resumes and steady-state switching continues.

For simplicity, neither Figure 62, nor Figure 63 show the ripple on the Output V

nor the COMP waveform.

CORE

LOAD

CORE

SUM

COMP

SW_CLK

Phase 1

Phase 2

Phase 3

UDG-11034

LOAD

CORE

SUM

COMP

SW_CLK

Phase 1

Phase 2

Phase 3

Time

UDG-11033

UDG-11035

+ 10.8 V –

12 V

– 1.2 V +

1.2 V

TPS51640A, TPS59640, TPS59641

SLUSAQ2 –JANUARY 2012

Figure 62. Operating Waveforms During Load Figure 63. needs a title

Transient

Overshoot Reduction (OSR)

In low duty-cycle synchronous buck converters, an overshoot condition results from the output inductor having a too little voltage (V

In Figure 64, a single phase converter is shown for simplicity. In an ideal converter, with typical input voltage of 12 V and 1.2-V output, the inductor has 10.8 V (12 V – 1.2 V) to respond to a transient load increase, but only

1.2 V with which to respond once the load releases.

) with which to respond to a transient load release.

CORE

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Figure 64. Synchronous Converter

When the overshoot reduction feature is enabled, the output voltage increases beyond a value that corresponds to a voltage difference between the ISUM voltage and the COMP voltage, exceeding the specified OSR voltage specified in the ELECTRICAL CHARACTERISTICS. At that instant, the low-side drivers are turned OFF. When the low-side driver is turned OFF, the energy in the inductor is partially dissipated by the body diodes. As the overshoot reduces, the low-side drivers are turned ON again.

Figure 65 shows the overshoot without OSR. Figure 66 shows the overshoot with OSR. The overshoot reduces

by approximately 23 mV. This shows that reduced output capacitance can be used while continuing to meet the specification. Note the low-side driver turning OFF briefly during the overshoot.

TPS51640A, TPS59640, TPS59641

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Figure 65. 43-A Load Transient Release Without Figure 66. 43-A Load Transient Release With OSR

OSR Enabled. Enabled

Undershoot Reduction (USR)

When the transient load increase becomes quite large, it becomes difficult to meet the energy demanded by the load especially at lower input voltages. Then it is necessary to quickly increase the energy tin the inductors during the transient load increase. This is achieved in these devices by enabling pulse overlapping. In order to maintain the interleaving of the multi-phase configuration and yet be able to have pulse-overlapping during load-insertion, the undershoot reduction (USR) mode is entered only when necessary. This mode is entered when the difference between COMP voltage and ISUM voltage exceeds the USR voltage level specified in the

ELECTRICAL CHARACTERISTICS table. Figure 67 shows the performance with undershoot reduction. Figure 68 shows the performance without

undershoot reduction and that it is possible to eliminate undershoot by enabling the undershoot reduction. This allows reduced output capacitance to be used and still meet the specification.

When the transient condition is over, the interleaving of the phases is resumed. For Figure 67, note the overlapping pulses for Phase 1 and Phase 2 with USR enabled.

SLUSAQ2 –JANUARY 2012

Figure 67. Performance for a 43-A Load Transient Figure 68. Performance for a 43-A Load Transient

Release Without USR Enabled Release With USR Enabled

A single-phase GPU operates in a similar way, but instead of pulse-overlap in multi-phase CPU, there is pulse stretching to provide the needs of the transient load increase when USR is enabled.

37VBAT

4CCSP1

5CCSN1

Current

Amplifier

5 ms

Filter

AVG

DAC

T(on)

PWM1

K x (I1-I

AVG

)

7CCSP2

6CCSN2

Current

Amplifier

5 ms

Filter

AVG

DAC

T(on)

PWM2

K x (I2-I

AVG

)

Averaging

Circuit

AVG

8CCSP3

9CCSN3

Current

Amplifier

5 ms

Filter

AVG

DAC

T(on)

PWM3

K x (I3-I

AVG

)

UDG-11036

TPS51640A, TPS59640, TPS59641

SLUSAQ2 –JANUARY 2012

AutoBalance™ Current Sharing

The basic mechanism for current sharing is to sense the average phase current, then adjust the pulse width of each phase to equalize the current in each phase. (See Figure 69.)

The PWM comparator (not shown) starts a pulse when the feedback voltage meets the reference. The VBAT voltage charges C reference, normally the DAC voltage (V

The circuit operates in the following fashion, using Figure 69 as the block diagram. First assume that the 5-µs averaged value of I1 = I2 = I3. In this case, the PWM modulator terminates at V is delivered to the system. If instead, I1 > I Phase 1 is shortened, reducing the current in Phase 1 to compensate. If I1 < I produced, again compensating on a pulse-by-pulse basis.

t(ON)

through R

. The pulse is terminated when the voltage at C

t(ON)

DAC

, then an offset is subtracted from V

AVG

matches the t

t(ON)

, and the normal pulse width

DAC

, and the pulse width for

DAC

, then a longer pulse is

AVG

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(ON)

Figure 69. Schematic Representation of AutoBalance Current Sharing

Dynamic VID and Power-State Changes

In IMVP-7, there are 3 basic types of VID changes:

• SetVID-Fast

• SetVID-Slow

• SetVID-Decay

SetVID-Fast change and a SetVID-Slow change automatically puts the power state in PS0. A SetVID-Decay change automatically puts the power state in PS2.

TPS51640A, TPS59640, TPS59641

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The CPU operates in the maximum phase mode when it is in PS0. This means when the CPU channel of the controller is configured as 3-phase, all 3 phases are active in PS0. When configured in 2-phase mode, the two phases are active in PS0. But in PS1, PS2 and PS3, the operation is in single-phase mode. Additionally, the CPU channel in PS0 mode operates in forced continuous conduction mode (FCCM). But in PS1, PS2 and PS3, the CPU channel operates in diode emulation (DE) mode for additional power savings and higher efficiency.

The single-phase GPU section always operates in diode emulation (DE) mode in all PS states. The slew rate for a SetVID-Fast is the slew rate set at the SLEWA pin. This slew rate is defined in the

ELECTRICAL CHARACTERISTICS table. The SetVID-Slow is ¼ of the SetVID-Fast slew rate. On a

SetVID-Decay the output voltage decays by the rate of the load current or 1/8 of the slew rate whichever is slower.

Additionally, on a SetVID-Fast change for a VID-up transition, the gain of the gMamplifier is increased to speed up the response of the output voltage to meet the Intel timing requirement. So, it is possible to observe an overshoot at the output voltage on a VID-up transition. This overshoot is allowed by the Intel specification.

XXX

Table 4. VID (continued)

Table 4. VID

VID VID VID VID VID VID VID VID

7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 00 0.000 0 0 0 0 0 0 0 1 01 0.250 0 0 0 0 0 0 1 0 02 0.255 0 0 0 0 0 0 1 1 03 0.260 0 0 0 0 0 1 0 0 04 0.265 0 0 0 0 0 1 0 1 05 0.270 0 0 0 0 0 1 1 0 06 0.275 0 0 0 0 0 1 1 1 07 0.280 0 0 0 0 1 0 0 0 08 0.285 0 0 0 0 1 0 0 1 09 0.290 0 0 0 0 1 0 1 0 0A 0.295 0 0 0 0 1 0 1 1 0B 0.300 0 0 0 0 1 1 0 0 0C 0.305 0 0 0 0 1 1 0 1 0D 0.310 0 0 0 0 1 1 1 0 0E 0.315 0 0 0 0 1 1 1 1 0F 0.320 0 0 0 1 0 0 0 0 10 0.325 0 0 0 1 0 0 0 1 11 0.330 0 0 0 1 0 0 1 0 12 0.335 0 0 0 1 0 0 1 1 13 0.340 0 0 0 1 0 1 0 0 14 0.345 0 0 0 1 0 1 0 1 15 0.350 0 0 0 1 0 1 1 0 16 0.355 0 0 0 1 0 1 1 1 17 0.360 0 0 0 1 1 0 0 0 18 0.365 0 0 0 1 1 0 0 1 19 0.370 0 0 0 1 1 0 1 0 1A 0.375 0 0 0 1 1 0 1 1 1B 0.380 0 0 0 1 1 1 0 0 1C 0.385 0 0 0 1 1 1 0 1 1D 0.390 0 0 0 1 1 1 1 0 1E 0.395 0 0 0 1 1 1 1 1 1F 0.400

HEX V

DAC

0 0 1 0 0 0 0 0 20 0.405 0 0 1 0 0 0 0 1 21 0.410 0 0 1 0 0 0 1 0 22 0.415 0 0 1 0 0 0 1 1 23 0.420 0 0 1 0 0 1 0 0 24 0.425 0 0 1 0 0 1 0 1 25 0.430 0 0 1 0 0 1 1 0 26 0.435 0 0 1 0 0 1 1 1 27 0.440 0 0 1 0 1 0 0 0 28 0.445 0 0 1 0 1 0 0 1 29 0.450 0 0 1 0 1 0 1 0 2A 0.455 0 0 1 0 1 0 1 1 2B 0.460 0 0 1 0 1 1 0 0 2C 0.465 0 0 1 0 1 1 0 1 2D 0.470 0 0 1 0 1 1 1 0 2E 0.475 0 0 1 0 1 1 1 1 2F 0.480 0 0 1 1 0 0 0 0 30 0.485 0 0 1 1 0 0 0 1 31 0.490 0 0 1 1 0 0 1 0 32 0.495 0 0 1 1 0 0 1 1 33 0.500 0 0 1 1 0 1 0 0 34 0.505 0 0 1 1 0 1 0 1 35 0.510 0 0 1 1 0 1 1 0 36 0.515 0 0 1 1 0 1 1 1 37 0.520 0 0 1 1 1 0 0 0 38 0.525 0 0 1 1 1 0 0 1 39 0.530 0 0 1 1 1 0 1 0 3A 0.535 0 0 1 1 1 0 1 1 3B 0.540 0 0 1 1 1 1 0 0 3C 0.545 0 0 1 1 1 1 0 1 3D 0.550 0 0 1 1 1 1 1 0 3E 0.555 0 0 1 1 1 1 1 1 3F 0.560 0 1 0 0 0 0 0 0 40 0.565 0 1 0 0 0 0 0 1 41 0.570 0 1 0 0 0 0 1 0 42 0.575

SLUSAQ2 –JANUARY 2012

TPS51640A, TPS59640, TPS59641

SLUSAQ2 –JANUARY 2012

Table 4. VID (continued) Table 4. VID (continued)

0 1 0 0 0 0 1 1 43 0.580 0 1 1 1 0 0 1 1 73 0.820 0 1 0 0 0 1 0 0 44 0.585 0 1 1 1 0 1 0 0 74 0.825 0 1 0 0 0 1 0 1 45 0.590 0 1 1 1 0 1 0 1 75 0.830 0 1 0 0 0 1 1 0 46 0.595 0 1 1 1 0 1 1 0 76 0.835 0 1 0 0 0 1 1 1 47 0.600 0 1 1 1 0 1 1 1 77 0.840 0 1 0 0 1 0 0 0 48 0.605 0 1 1 1 1 0 0 0 78 0.845 0 1 0 0 1 0 0 1 49 0.610 0 1 1 1 1 0 0 1 79 0.850 0 1 0 0 1 0 1 0 4A 0.615 0 1 1 1 1 0 1 0 7A 0.855 0 1 0 0 1 0 1 1 4B 0.620 0 1 1 1 1 0 1 1 7B 0.860 0 1 0 0 1 1 0 0 4C 0.625 0 1 1 1 1 1 0 0 7C 0.865 0 1 0 0 1 1 0 1 4D 0.630 0 1 1 1 1 1 0 1 7D 0.870 0 1 0 0 1 1 1 0 4E 0.635 0 1 1 1 1 1 1 0 7E 0.875 0 1 0 0 1 1 1 1 4F 0.640 0 1 1 1 1 1 1 1 7F 0.880 0 1 0 1 0 0 0 0 50 0.645 1 0 0 0 0 0 0 0 80 0.885 0 1 0 1 0 0 0 1 51 0.650 1 0 0 0 0 0 0 1 81 0.890 0 1 0 1 0 0 1 0 52 0.655 1 0 0 0 0 0 1 0 82 0.895 0 1 0 1 0 0 1 1 53 0.660 1 0 0 0 0 0 1 1 83 0.900 0 1 0 1 0 1 0 0 54 0.665 1 0 0 0 0 1 0 0 84 0.905 0 1 0 1 0 1 0 1 55 0.670 1 0 0 0 0 1 0 1 85 0.910 0 1 0 1 0 1 1 0 56 0.675 1 0 0 0 0 1 1 0 86 0.915 0 1 0 1 0 1 1 1 57 0.680 1 0 0 0 0 1 1 1 87 0.920 0 1 0 1 1 0 0 0 58 0.685 1 0 0 0 1 0 0 0 88 0.925 0 1 0 1 1 0 0 1 59 0.690 1 0 0 0 1 0 0 1 89 0.930 0 1 0 1 1 0 1 0 5A 0.695 1 0 0 0 1 0 1 0 8A 0.935 0 1 0 1 1 0 1 1 5B 0.700 1 0 0 0 1 0 1 1 8B 0.940 0 1 0 1 1 1 0 0 5C 0.705 1 0 0 0 1 1 0 0 8C 0.945 0 1 0 1 1 1 0 1 5D 0.710 1 0 0 0 1 1 0 1 8D 0.950 0 1 0 1 1 1 1 0 5E 0.715 1 0 0 0 1 1 1 0 8E 0.955 0 1 0 1 1 1 1 1 5F 0.720 1 0 0 0 1 1 1 1 8F 0.960 0 1 1 0 0 0 0 0 60 0.725 1 0 0 1 0 0 0 0 90 0.965 0 1 1 0 0 0 0 1 61 0.730 1 0 0 1 0 0 0 1 91 0.970 0 1 1 0 0 0 1 0 62 0.735 1 0 0 1 0 0 1 0 92 0.975 0 1 1 0 0 0 1 1 63 0.740 1 0 0 1 0 0 1 1 93 0.980 0 1 1 0 0 1 0 0 64 0.745 1 0 0 1 0 1 0 0 94 0.985 0 1 1 0 0 1 0 1 65 0.750 1 0 0 1 0 1 0 1 95 0.990 0 1 1 0 0 1 1 0 66 0.755 1 0 0 1 0 1 1 0 96 0.995 0 1 1 0 0 1 1 1 67 0.760 1 0 0 1 0 1 1 1 97 1.000 0 1 1 0 1 0 0 0 68 0.765 1 0 0 1 1 0 0 0 98 1.005 0 1 1 0 1 0 0 1 69 0.770 1 0 0 1 1 0 0 1 99 1.010 0 1 1 0 1 0 1 0 6A 0.775 1 0 0 1 1 0 1 0 9A 1.015 0 1 1 0 1 0 1 1 6B 0.780 1 0 0 1 1 0 1 1 9B 1.020 0 1 1 0 1 1 0 0 6C 0.785 1 0 0 1 1 1 0 0 9C 1.025 0 1 1 0 1 1 0 1 6D 0.790 1 0 0 1 1 1 0 1 9D 1.030 0 1 1 0 1 1 1 0 6E 0.795 1 0 0 1 1 1 1 0 9E 1.035 0 1 1 0 1 1 1 1 6F 0.800 1 0 0 1 1 1 1 1 9F 1.040 0 1 1 1 0 0 0 0 70 0.805 1 0 1 0 0 0 0 0 A0 1.045 0 1 1 1 0 0 0 1 71 0.810 1 0 1 0 0 0 0 1 A1 1.050 0 1 1 1 0 0 1 0 72 0.815 1 0 1 0 0 0 1 0 A2 1.055

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TPS51640A, TPS59640, TPS59641

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Table 4. VID (continued) Table 4. VID (continued)

1 0 1 0 0 0 1 1 A3 1.060 1 1 0 1 0 0 1 1 D3 1.300 1 0 1 0 0 1 0 0 A4 1.065 1 1 0 1 0 1 0 0 D4 1.305 1 0 1 0 0 1 0 1 A5 1.070 1 1 0 1 0 1 0 1 D5 1.310 1 0 1 0 0 1 1 0 A6 1.075 1 1 0 1 0 1 1 0 D6 1.315 1 0 1 0 0 1 1 1 A7 1.080 1 1 0 1 0 1 1 1 D7 1.320 1 0 1 0 1 0 0 0 A8 1.085 1 1 0 1 1 0 0 0 D8 1.325 1 0 1 0 1 0 0 1 A9 1.090 1 1 0 1 1 0 0 1 D9 1.330 1 0 1 0 1 0 1 0 AA 1.095 1 1 0 1 1 0 1 0 DA 1.335 1 0 1 0 1 0 1 1 AB 1.100 1 1 0 1 1 0 1 1 DB 1.340 1 0 1 0 1 1 0 0 AC 1.105 1 1 0 1 1 1 0 0 DC 1.345 1 0 1 0 1 1 0 1 AD 1.110 1 1 0 1 1 1 0 1 DD 1.350 1 0 1 0 1 1 1 0 AE 1.115 1 1 0 1 1 1 1 0 DE 1.355 1 0 1 0 1 1 1 1 AF 1.120 1 1 0 1 1 1 1 1 DF 1.360 1 0 1 1 0 0 0 0 B0 1.125 1 1 1 0 0 0 0 0 E0 1.365 1 0 1 1 0 0 0 1 B1 1.130 1 1 1 0 0 0 0 1 E1 1.370 1 0 1 1 0 0 1 0 B2 1.135 1 1 1 0 0 0 1 0 E2 1.375 1 0 1 1 0 0 1 1 B3 1.140 1 1 1 0 0 0 1 1 E3 1.380 1 0 1 1 0 1 0 0 B4 1.145 1 1 1 0 0 1 0 0 E4 1.385 1 0 1 1 0 1 0 1 B5 1.150 1 1 1 0 0 1 0 1 E5 1.390 1 0 1 1 0 1 1 0 B6 1.155 1 1 1 0 0 1 1 0 E6 1.395 1 0 1 1 0 1 1 1 B7 1.160 1 1 1 0 0 1 1 1 E7 1.400 1 0 1 1 1 0 0 0 B8 1.165 1 1 1 0 1 0 0 0 E8 1.405 1 0 1 1 1 0 0 1 B9 1.170 1 1 1 0 1 0 0 1 E9 1.410 1 0 1 1 1 0 1 0 BA 1.175 1 1 1 0 1 0 1 0 EA 1.415 1 0 1 1 1 0 1 1 BB 1.180 1 1 1 0 1 0 1 1 EB 1.420 1 0 1 1 1 1 0 0 BC 1.185 1 1 1 0 1 1 0 0 EC 1.425 1 0 1 1 1 1 0 1 BD 1.190 1 1 1 0 1 1 0 1 ED 1.430 1 0 1 1 1 1 1 0 BE 1.195 1 1 1 0 1 1 1 0 EE 1.435 1 0 1 1 1 1 1 1 BF 1.200 1 1 1 0 1 1 1 1 EF 1.440

1 0 0 0 0 0 0 C0 1.205 1 1 1 1 0 0 0 0 F0 1.445 1 1 0 0 0 0 0 1 C1 1.210 1 1 1 1 0 0 0 1 F1 1.450 1 1 0 0 0 0 1 0 C2 1.215 1 1 1 1 0 0 1 0 F2 1.455 1 1 0 0 0 0 1 1 C3 1.220 1 1 1 1 0 0 1 1 F3 1.460 1 1 0 0 0 1 0 0 C4 1.225 1 1 1 1 0 1 0 0 F4 1.465 1 1 0 0 0 1 0 1 C5 1.230 1 1 1 1 0 1 0 1 F5 1.470 1 1 0 0 0 1 1 0 C6 1.235 1 1 1 1 0 1 1 0 F6 1.475 1 1 0 0 0 1 1 1 C7 1.240 1 1 1 1 0 1 1 1 F7 1.480 1 1 0 0 1 0 0 0 C8 1.245 1 1 1 1 1 0 0 0 F8 1.485 1 1 0 0 1 0 0 1 C9 1.250 1 1 1 1 1 0 0 1 F9 1.490 1 1 0 0 1 0 1 0 CA 1.255 1 1 1 1 1 0 1 0 FA 1.495 1 1 0 0 1 0 1 1 CB 1.260 1 1 1 1 1 0 1 1 FB 1.500 1 1 0 0 1 1 0 0 CC 1.265 1 1 1 1 1 1 0 0 FC 1.505 1 1 0 0 1 1 0 1 CD 1.270 1 1 1 1 1 1 0 1 FD 1.510 1 1 0 0 1 1 1 0 CE 1.275 1 1 1 1 1 1 1 0 FE 1.515 1 1 0 0 1 1 1 1 CF 1.280 1 1 1 1 1 1 1 1 FF 1.520 1 1 0 1 0 0 0 0 D0 1.285 1 1 0 1 0 0 0 1 D1 1.290 1 1 0 1 0 0 1 0 D2 1.295

SLUSAQ2 –JANUARY 2012

TPS51640A, TPS59640, TPS59641

SLUSAQ2 –JANUARY 2012

Gate Driver

The TPS51640A, TPS59640, and TPS59641 incorporate two internal strong, high-performance gate drives with adaptive cross-conduction protection. These drivers are for two phases in the CPU channel. The third phase of the CPU and the single-phase GPU channel require external drivers.

The internal driver in these devices uses the state of the CDLx and CSWx pins to be sure the high-side or low-side FET is OFF before turning the other ON. Fast logic and high drive currents (up to 8-A typical) quickly charge and discharge FET gates to minimize dead-time to increase efficiency. The high-side gate driver also includes an integrated boost FET instead of merely a diode to increase the effective drive voltage for higher efficiency. A zero-crossing detection logic, which detects the switch-node voltage before turning OFF the low-side FET, is used to minimize losses during DCM operation.

Input Under Voltage Protection (5V and 3.3V)

The TPS51640A, TPS59640, and TPS59641 continuously monitor the voltage on the V5DRV, V5 and V3R3 pin to be sure the value is high enough to bias the device properly and provide sufficient gate drive potential to maintain high efficiency. The converter starts with approximately 4.4-V and has a nominal 200 mV of hysteresis. The input (V approximately 3 x V

) does not have a UVLO function, so the circuit operates with power inputs as low as

BAT

CORE

Power Good (CPGOOD and GPGOOD)

These devices have two open-drain power good pins that follow the requirements for IMVP-7. CPGOOD is used for the CPU channel output voltage and GPGOOD is used for the GPU channel output voltage. Both of these signals are active high. The upper and the lower limits for the output voltage for xPGOOD active are:

• Upper: V

• Lower : V

xPGOOD goes inactive (low) as soon as the VR_ON pin is pulled low or an undervoltage condition on V5 or V3R3 is detected. The xPGOOD signals are masked during DAC transitions to prevent false triggering during voltage slewing.

DAC

+220 mV

–315 mV

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Output Under Voltage Protection

Output undervoltage protection works in conjunction with the current protection described below. If V below the low PGOOD threshold, then the drivers are turned OFF until VR_ON is cycled.

CORE

drops

Overcurrent Protection

The TPS51640A, TPS59640, and TPS59641 use a valley current limiting scheme, so the ripple current must be considered. The DC current value at OCP is the OCP limit value plus half of the ripple current. Current limiting occurs on a phase-by-phase and pulse-by-pulse basis. If the voltage between xCSPx and xCSNx is above the OCP value, the converter delays the next ON pulse until it drops below the OCP limit. For inductor current sensing circuits, the voltage between xCSPx and xCSNx is the inductor DCR value multiplied by the resistor divider which is part of the NTC compensation network. As a result, a wide range of OCP values can be obtained by changing the resistor divider value. In general, use the highest OCP setting possible with the least attenuation in the resistor divider to provide as much signal to the device as possible. This provides the best performance for all parameters related to current feedback.

In OCP mode, the voltage drops until the UVP limit is reached. Then, the converter sets the xPGOOD to inactive, and the drivers are turned OFF. The converter remains in this state until the device is reset by the VR_ON.

Overvoltage Protection

An OVP condition is detected when V sets xPGOOD inactive, and turns ON the drive for the Low-side FET. The converter remains in this state until the device is reset by cycling VR_ON. However, because of the dynamic nature of IMVP-7 systems, the +220 mV OVP threshold is blanked much of the time. In order to provide protection to the processor 100% of the time, there is a second OVP level fixed at 1.7 V which is always active. If the fixed OVP condition is detected, the PGOOD are forced inactive and the low-side FETs are tuned ON. The converter remains in this state until VR_ON is cycled.

is more than 220 mV greater than V

CORE

. In this case, the converter

DAC

æ ö

= ´ + ´

ç ÷ è ø

CIMON

CIMON CS CCSn

COCP

V A 1 V

æ ö

= ´ + ´

ç ÷ è ø

GIMON

GIMON CS GCS

GOCP

V A 1 V

TPS51640A, TPS59640, TPS59641

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Over Temperature Protection

Two types of thermal protection are provided in these devices:

• VR_HOT

• Thermal Shutdown

VR_HOT

The VR_HOT signal is an Intel-defined open-drain signal that is used to protect the V VR_HOT, place an NTC thermistor at the hottest area of the CPU channel and connect it from CTHERM pin to GND. Similarly for GPU channel, place the NTC thermistor at the hottest area and connect it from GTHERM to GND. Also, connect a resistor from VREF to GTHERM and CTHERM. As the temperature increases, the xTHERM voltage drops below the THERM threshold, VR_HOT is activated. A small capacitor may be connected to the xTHERM pins for high frequency noise filtering.

lists the thermal zone register bits based on the xTHERM pin voltage.

Table 5. Thermal Zone Register Bits

OUTPUT IS VR_HOT xTHERM THRESHOLD VOLTAGE FOR THE TEMPERATURE

SHUTDOWN ASSERTED ZONE REGISTER BITS TO BE ASSERTED.

b7 b6 b5 b4 b3 b2 b1 b0

410 mV 455 mV 458 mV 523 mV 559 mV 598 mV 638 mV 680 mV 783 mV

Thermal Shutdown

When the xTHERM pin voltage continues to drop even after VR_HOT is asserted, the drivers turn OFF and the output is shutdown. These devices also have an internal temperature sensor. When the temperature reaches a nominal 155°C, the device shuts down until the temperature cools approximately 20°C. Then, the circuit can be re-started by cycling VR_ON.

SVID ALERT ASSERTED

SLUSAQ2 –JANUARY 2012

power chain. To use

CORE

Current Monitor, IMON

The TPS51640A, TPS59640, and TPS59641 includes a current monitor (IMON) function each for CPU channel and GPU channel. The current monitor puts out an analog voltage proportional to the output current on the xIMON pins.

The current monitor function is tied with the OCP selection resistors. The R from COCP-I and GOCP-I respectively to select the OCP levels. R set the CIMON gain. Similarly, R

is the resistor from GIMON to GOCP-I to set the GIMON gain.

GIMON

is the resistor from CIMON to COCP-I to

CIMON

The calculation for the CIMON voltage is shown in Equation 2. The calculation for the GIMON voltages is shown in Equation 3.

where

• ACSis given in the ELECTRICAL CHARACTERISTICS table

• Σ V

• V

is the sum of the DC voltages at the inputs to the CPU channel current sense amplifiers

CCS

is the DC voltage at the GPU channel current sense amplifier (3)

GCS

For the current monitor function to be stable, connect a 220-nF capacitor from CIMON and GIMON to GND.

COCP

and R

are resistors to GND

GOCP

(2)

( )

æ ö

= ´

ç ÷

è ø

CC max CPU

CF CIMAX

I 255

R R

( )

æ ö

= ´

ç ÷

è ø

CC max GPU

GF GIMAX

I 255

R R

TPS51640A, TPS59640, TPS59641

SLUSAQ2 –JANUARY 2012

www.ti.com

Setting the Maximum Processor Current (I

CC(max)

)

The TPS51640 controller allows the user to set the maximum processor current with the multi-function pins CF-IMAX and GF-IMAX. The voltage on the CF-IMAX and GF-IMAX at start-up sets the maximum processor current (I

) for CPU and GPU respectively.

CC(max)

The RCFand RGFare resistors to GND from CF-IMAX and GF-IMAX respectively to select the frequency setting. R

Equation 4 describes the setting the I

is the resistor from VREF to CF-IMAX and R

CIMAX

CC(max)

for the GPU channel.

CC(max)

is the resistor from VREF to GF-IMAX.

GIMAX

for the CPU channel and Equation 5 describes the setting the

(4)

(5)

Internal Driver Bypass Mode

The controller can be configured to operate in internal driver bypass mode for use with DrMOS type devices and driver-integrated PowerBlock devices. Consider the following items when designing for operation in this mode.

• Tie CSW2, CSW1 to V5DRV.

• CDL1 becomes the PWM input to the Phase 1 DrMOS device (or external driver)

• CDL2 becomes the PWM input to the Phase 2 DrMOS device (or external driver)

• CSKIP pin becomes the input to the SKIP/FCCM pin of the DrMOS device (or external driver)

• The Phase-2 and Phase-3 DrMOS device (or the external driver) must be configured in FCCM mode.

= ´ =

P P

94 A

I 0.3 9.4 A

TPS51640A, TPS59640, TPS59641

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DESIGN STEPS

The design procedure using the TPS51640A, TPS59640, and TPS59641 is very simple . An excel-based component value calculation tool is available. Contact your local TI representative to get a copy of the spreadsheet.

The procedure is explained here below with the following design example:

SLUSAQ2 –JANUARY 2012

CPU V

No. of phases 3 1

Input Voltage Range 9 V to 20 V 9 V to 20 V

VHFM 0.9 V 1.23 V

CC(max)

IDYN-MAX 66 A 20 A

ICC-TDC 52 21.5 Load-line 1.9 mV/A 3.9 mV/A

Fast Slew Rate (minimum) 10 mV/µs 10 mV/µs

SPECIFICATIONS GFX V

CORE

94 A 33 A

SPECIFICATIONS

CORE

Step One: Select Switching Frequency.

The CPU channel switching frequency is selected by a resistor from CF-IMAX to GND (RCF) and GPU channel switching frequency is selected by a resistor from GF-IMAX to GND (RGF). The frequency is an approximate frequency and is expected to vary based on load and input voltage.

SELECTION RESISTANCE (kΩ)

20 250 275 24 300 330 30 350 385 39 400 440 56 450 495

75 500 550 100 550 605 150 600 660

CPU CHANNEL FREQUENCY GPU CHANNEL FREQUENCY

(kHz) (kHz)

For this design, the switching frequency for CPU channel is chosen to be 300 kHz and GPU channel is chosen to be 385 kHz. Therefore,

RCF= 24 kΩ and RGF= 30 kΩ Step Two: Set I The I

CC(max)

resistors from VREF to CF-IMAX (R

CC(max)

is set by the voltage on CF-IMAX for CPU channel and GF-IMAX for GPU channel. This is set by the

) and from VREF to GF-IMAX (R

CMAX

GMAX

)

From Equation 4 and Equation 5,

= 42.2 kΩ and R

CMAX

GMAX

= 200 kΩ. Step Three: Set the Slew Rate The slew rate is set by the voltage setting on SLEWA pin. For a minimum 10 mV/ms slew rate, the voltage on the

SLEWA pin must be: 0.8 V. This is set by a resistor divider on SLEWA pin from VREF. The low-side resistor is chosen to be 150 kΩ and the high-side resistor is calculated as 169 kΩ.

Step Four: Determine inductor value and choose inductor. Smaller values of inductor have better transient performance but higher ripple and lower efficiency. Higher values

have the opposite characteristics. It is common practice to limit the ripple current to 20% to 40% of the maximum current per phase. In this case, we use 30%:

(6)

P P

V dT

( )

æ ö ç ÷

= + ´ =

ç ÷ è ø

CC max

P P

SAT

PHASE

I 1.2 43.2 A

N 2

UDG-11039

CSN

DCR

NTC

PAR

SENSE

SERIES

SEQU

CSP

TPS51640A, TPS59640, TPS59641

SLUSAQ2 –JANUARY 2012

In this equation, V = V An inductance value of 0.36 µH is chosen as this is a commonly used inductor for V

IN-MAX

– V

= 19. 1V; dT = V

HFM

/ (F x V

) = 150 ns; Ipp= 9.4A. So, calculating, L = 0.304 µH.

IN-MAX

CORE

application. The

inductor must not saturate during peak loading conditions.

The factor of 1.2 allows for current sensing and current limiting tolerances; the factor of 1.25 is the Intel 25% momentary OCP requirement.

The chosen inductor should have the following characteristics:

• An inductance to current curve ratio equal to 1 (or as close possible). Inductor DCR sensing is based on the

idea L/DCR is approximately a constant through the current range of interest.

• Either high saturation or soft saturation.

• Low DCR for improved efficiency, but at least 0.7 mΩ for proper signal levels.

• DCR tolerance as low as possible for load-line accuracy.

For this application, a 0.36-µH, 0.825-mΩ inductor is chosen. Because the per phase current for GPU is same as CPU, the same inductor for GPU channel is chosen.

Step Five: Determine current sensing method. The TPS51640A, TPS59640, and TPS59641 support both resistor sensing and inductor DCR sensing. Inductor

DCR sensing is chosen. For resistor sensing, substitute the resistor value (0.75 mΩ recommended for a 3-phase 94-A application) for RCS in the subsequent equations and skip Step Four.

Step Six: Design the thermal compensation network and selection of OCP. In most designs, NTC thermistors are used to compensate thermal variations in the resistance of the inductor

winding. This winding is generally copper, and so has a resistance coefficient of 3900 PPM/°C. NTC thermistors, on the other hand, have very non-linear characteristics and need two or three resistors to linearize them over the range of interest. The typical DCR circuit is shown in Figure 70.

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(7)

(8)

In this circuit, the voltage across the C

Figure 70. Typical DCR Sensing Circuit

exactly equals the voltage across R

SENSE

when Equation 9 is true.

DCR

= ´

SENSE EQ

DCR

C R

P _ N

SEQU P _ N

R R

( )

´ +

+ +

PAR NTC SERIES

P _ N

PAR NTC SERIES

R R R

( )

= ´

P _ N

DCR

CS eff

SEQU P _ N

R R

( )

W ´

= = = W

´ W´

CS eff

GDROOP

LL M

R A

0.66m 12

R 4.12 k

R G 3.9m 0.497mS

( )

W ´

= = = W

´ W ´

CS eff

CDROOP

LL M

R A

0.66m 12

R 8.45k

R G 1.9m 0.497 mS

TPS51640A, TPS59640, TPS59641

www.ti.com

where

SENSE

• REQis the series/parallel combination of R

should be a capacitor type which is stable over temperature. Use X7R or better dielectric (C0G

SEQU

, R

NTC

, R

SERIES

and R

PAR

preferred). Since calculating these values by hand is difficult, TI has a spreadsheet using the Excel Solver function available

to calculate them. Contact a local TI representative to get a copy of the spreadsheet. In this design, the following values are input to the spreadsheet:

• L = 0.36 µH

• R

• Load Line, R

= 0.825 mΩ

DCR

IMVP

= -1.9 mΩ

• Minimum overcurrent limit = 112 A

• Thermistor R25= 100 kΩ and "B" value = 4250 kΩ

The spreadsheet then calculates the OCP (overcurrent protection) setting and the values of R R

PAR

, and C

. In this case, the OCP setting is the resistor value selection of 56 kΩ from COCP-I to GND and

SENSE

GOCP-I to GND. The nearest standard component values are:

• R

• C

SEQU SERIES PAR SENSE

= 17.8 kΩ;

= 28.7 kΩ;

= 162 kΩ

=33 nF

Note the effective divider ratio for the inductor DCR. The effective current sense resistance (R

Equation 12.

SLUSAQ2 –JANUARY 2012

(9)

(10)

(11)

, R

SEQU

CS(eff)

SERIES

) is shown in

where

CS(eff)

• R

is 0.66 mΩ.

is the series/parallel combination of R

P_N

Step Seven: Set current monitor (IMON) setting resistor. After the OCP selection resistor is selected in Step 6, the IMON is set by the resistor from CIMON to COCP-I

(R R

) and GIMON to GOCP-I (R

CIMON

= 71.5 kΩ and R

CIMON

GIMON

= 309 kΩ

). Based on Equation 2 and Equation 3,

Step Eight: Set the load line. The load-line for CPU channel is set by the resistor, R

channel is set by the resistor, R

GDROOP

from the GCOMP pin to VREF. Using the Equation 1, the droop setting

resistors are calculated in Equation 14 and Equation 15.

NTC

, R

SERIES

CDROOP

and R

. (12)

PAR

from CCOMP to VREF. The load-line for GPU

(13)

(14)

( )

W ´

= = = W

´ W´

CS eff

GDROOP

LL M

R A

0.66m 12

R 4.12 k

R G 3.9m 0.497mS

TPS51640A, TPS59640, TPS59641

SLUSAQ2 –JANUARY 2012

Step Nine: Programming the CTHERM and GTHERM pins. The CTHERM and GTHERM pins should be set so that the resistor divider voltage would be greater than 458

mV at normal operation. For VR_HOT to be asserted, the xTHERM pin voltage should fall below 458 mV. The NTC resistor from xTHERM to GND is chosen as 100 kΩ with a B of 4250K. With this, for a VR_HOT assertion temperature of 105°C, the resistor from xTHERM to VREF can be calculated as 15.4 kΩ.

Step Ten: Determine the output capacitor configuration. For the output capacitor, the Intel Power Delivery guideline gives the output capacitor recommendations. Using

these devices, it is possible to meet the load transient with lower capacitance by using the OSR and USR feature. Eight settings are available and this selection has to be tuned based on transient measurement.

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(15)

GND

14VREF

V3R3

VCLK

VDIO

ALERT

VR_HOT

CTHERM

GTHERM

CIMON

GIMON

CGFB

CVFB

GPGOOD

CPGOOD

GGFB

GVFB

COCP-I

CF-IMAX

CCOMP

VBAT

CCSN3

CCSP3

CCSN2

CSKIP

GPWM

GSKIP

GOCP-I

VR_ON

CPWM3

SLEWA

CCSP2

CCSN1

CCSP1

GCOMP

GCSP

GCSN

CDH2

CBST2

CSW2

CDL2

V5DRV

PGND

CDL1

CSW1

CBST1

CDH1

GF-IMAX

Drivers Analog Digital Power

TPS51640A, TPS59640, TPS59641

www.ti.com

PCB LAYOUT GUIDELINE

SCHEMATIC REVIEW

Because the voltage and current feedback signals are fully differential it is a good idea to double check their polarity.

1. CCSP1/CCSN1

2. CCSP2/CCSN2

3. CCSP2/CCSN2

4. GCSP/GCSN

5. VCCSENSE to CVFB/VSSSENSE to CGFB (for CPU)

6. VCCGTSENSE to GVFB/VSSGTSENSE to GGFB (for GPU)

Also, note the order of the current sense inputs on Pin 4 to Pin 9 as the second phase has a reverse order.

CAUTION

Separate noisy driver interface lines from sensitive analog interface lines: (This is the MOST CRITICAL LAYOUT RULE)

The TPS51640A, TPS59640, and TPS59641 make this as easy as possible. The pin-out arrangement for TPS51640A is shown in Figure 71. The driver outputs clearly separated from the sensitive analog and digital circuitry. The driver has a separate PGND and this should be directly connected to the decoupling capacitor that connects from V5DRV to PGND. The thermal pad of the package is the analog ground for these devices and should NOT be connected directly to PGND (Pin 42).

SLUSAQ2 –JANUARY 2012

Figure 71. TPS51640A Pin-out Arranged by Pin Function

UDG-11038

CORE

Noisy Quiet

Inductor

Outline

SEQ

Thermistor

SERIES

CSNx

CSPx

TPS51640A, TPS59640, TPS59641

SLUSAQ2 –JANUARY 2012

Given the physical layout of most systems, the current feedback (xCSPx, xCSNx) may have to pass near the power chain. Clean current feedback is required for good load-line, current sharing, and current limiting performance of these devices, so please take the following precautions:

• Make a Kelvin connection to the pads of the resistor or inductor used for current sensing. See Figure 72 for a

layout example.

• Run the current feedback signals as a differential pair to the device.

• Run the lines in a quiet layer. Isolate them from noisy signals by a voltage or ground plane.

• Put the compensation capacitor for DCR sensing (C

) as close to the CS pins as possible.

SENSE

• Place any noise filtering capacitors directly underneath these devices and connect to the CS pins with the

shortest trace length possible.

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Figure 72. Make Kelvin Connections to the Inductor for DCR Sensing

UDG-11040

OUT

DRVH

DRVL

PGND

CORE

BAT

TPS51640A, TPS59640, TPS59641

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Minimize High-Current Loops

Figure 73 shows the primary current loops in each phase, numbered in order of importance.

The most important loop to minimize the area of is Loop 1, the path from the input capacitor through the high and low side FETs, and back to the capacitor through ground.

Loop 2 is from the inductor through the output capacitor, ground and Q2. The layout of the low side gate drive (Loops 3a and 3b) is important. The guidelines for gate drive layout are:

• Make the low-side gate drive as short as possible (1 inch or less preferred).

• Make the DRVL width to length ratio of 1:10, wider (1:5) if possible.

• If changing layers is necessary, use at least two vias.

SLUSAQ2 –JANUARY 2012

Figure 73. Major Current Loops to Minimize

Power Chain Symmetry

The TPS51640A, TPS59640, and TPS59641 do not require special care in the layout of the power chain components. This is because independent isolated current feedback is provided. If it is possible to lay out the phases in a symmetrical manner, then please do so. The rule is: the current feedback from each phase needs to be clean of noise and have the same effective current sense resistance.

Place analog components as close to the device as possible.

Place components close to the device in the following order.

1. CS pin noise filtering components

2. xCOMP pin compensation components

3. Decoupling capacitors for VREF, V3R3, V5

4. xTHERM filter capacitor

5. xIMON capacitor, resistors

6. xF-IMAX resistors

TPS51640A, TPS59640, TPS59641

SLUSAQ2 –JANUARY 2012

Grounding Recommendations

These devices have separate analog and power grounds, and a thermal pad. The normal procedure for connecting these is:

• The thermal pad is the analog ground.

• DO NOT connect the thermal pad to Pin 42 directly as Pin 42 is the PGND which is the Gate driver

Ground.

• Pin 42 (PGND) must be connected directly to the gate driver decoupling capacitor ground terminal.

• Tie the thermal pad (analog ground pin) to a ground island with at least 4 small vias or one large via.

• All the analog components can connect to this analog ground island.

• The analog ground can be connected to any quiet spot on the system ground. A quiet area is defined as a

area where no power supply switching currents are likely to flow. This applies to both the V

CORE

other regulators. Use a single point connection from analog ground to the system ground

• Make sure the low-side FET source connection and the decoupling capacitors have plenty of vias.

Decoupling Recommendations

• Decouple V5IN to PGND with at least a 2.2 µF ceramic capacitor.

• Decouple V5 and V3R3 with 1 µF to AGND with leads as short as possible,

• VREF to AGND with 0.33 µF, with short leads also

Conductor Widths

• Follow Intel guidelines with respect to the voltage feedback and logic interface connection requirements.

• Maximize the widths of power, ground and drive signal connections.

• For conductors in the power path, be sure there is adequate trace width for the amount of current flowing

through the traces.

• Make sure there are sufficient vias for connections between layers. A good guideline is to use a minimum of 1

via per ampere of current.

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regulator and

PACKAGE OPTION ADDENDUM

www.ti.com

13-Jun-2012

PACKAGING INFORMATION

Orderable Device

TPS51640ARSLR ACTIVE VQFN RSL 48 2500 Green (RoHS

TPS51640ARSLT ACTIVE VQFN RSL 48 250 Green (RoHS

TPS59640RSLR ACTIVE VQFN RSL 48 2500 Green (RoHS

TPS59640RSLT ACTIVE VQFN RSL 48 250 Green (RoHS

TPS59641RSLR ACTIVE VQFN RSL 48 2500 Green (RoHS

TPS59641RSLT ACTIVE VQFN RSL 48 250 Green (RoHS

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

Status

(1)

Package Type Package

Drawing

Pins Package Qty

Eco Plan

& no Sb/Br)

(2)

Lead/

Ball Finish

CU NIPDAUAGLevel-2-260C-1 YEAR

MSL Peak Temp

(3)

Samples

(Requires Login)

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

13-Jun-2012

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

TPS51640ARSLR VQFN RSL 48 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2

TPS51640ARSLT VQFN RSL 48 250 180.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2

TPS59640RSLR VQFN RSL 48 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2 TPS59640RSLT VQFN RSL 48 250 180.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2 TPS59641RSLR VQFN RSL 48 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2 TPS59641RSLT VQFN RSL 48 250 180.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2

Type

Package Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm)B0(mm)K0(mm)P1(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TPS51640ARSLR VQFN RSL 48 2500 367.0 367.0 38.0

TPS51640ARSLT VQFN RSL 48 250 210.0 185.0 35.0

TPS59640RSLR VQFN RSL 48 2500 367.0 367.0 38.0 TPS59640RSLT VQFN RSL 48 250 210.0 185.0 35.0 TPS59641RSLR VQFN RSL 48 2500 367.0 367.0 38.0 TPS59641RSLT VQFN RSL 48 250 210.0 185.0 35.0

Pack Materials-Page 2

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Texas Instruments TPS51640A, TPS59640, TPS59641 Schematic [ru]

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

DESCRIPTION

APPLICATIONS

SIMPLIFIED APPLICATION

ABSOLUTE MAXIMUM RATINGS

THERMAL INFORMATION

RECOMMENDED OPERATING CONDITIONS

ELECTRICAL CHARACTERISTICS

DEVICE INFORMATION

PIN FUNCTIONS

TYPICAL CHARACTERISTICS (TPS59641 ONLY)

FUNCTIONAL BLOCK DIAGRAM

APPLICATION INFORMATION

DETAILED DESCRIPTION

Functional Overview

User Selections

PWM Operation

Current Sensing

Setting the Load-line (DROOP)

Load Transients

Overshoot Reduction (OSR)

Undershoot Reduction (USR)

AutoBalance™ Current Sharing

Dynamic VID and Power-State Changes

Gate Driver

Input Under Voltage Protection (5V and 3.3V)

Power Good (CPGOOD and GPGOOD)

Output Under Voltage Protection

Overcurrent Protection

Overvoltage Protection

Over Temperature Protection

VR_HOT

Thermal Shutdown

Current Monitor, IMON

Internal Driver Bypass Mode

DESIGN STEPS

PCB LAYOUT GUIDELINE

SCHEMATIC REVIEW

Minimize High-Current Loops

Power Chain Symmetry

Grounding Recommendations

Decoupling Recommendations

Conductor Widths