Texas Instruments tps51461 Datasheet

TPS51461

VIN

VIN

SW

SW

VIN

PGND

PGND

PGND

SW

SW

SW

BST

EN

MODE

VOUT

COMP

SLEW

VREF

GND

VID0

VID1

PGOOD

V5DRV

V5FILT

19

20

21

22

23

24

1 2 3 4 5 6

12

11

10

9

8

7

18 17 16 15 14 13

VCCSA

VCCSASNS

UDG-10183

ENABLE

VIN

VID0
VID1

+5V

PGOOD

TPS51461

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SLUSAD9B –DECEMBER 2010– REVISED SEPTEMBER 2011

3.3-V/5-V Input, 6-A, D-CAP+™ Mode Synchronous Step-Down Integrated FETs Converter
With 2-Bit VID

Check for Samples: TPS51461

1

FEATURES

2

• Integrated FETs Converter w/TI Proprietary
D-CAP+™ Mode Architecture

• 6-A Maximum Output Current

• Minimum External Parts Count

• Support all MLCC Output Capacitor and

SP/POSCAP

• Auto Skip Mode

• Selectable 700-kHz and 1-MHz Frequency

• Small 4 × 4, 24-Pin, QFN Package

APPLICATIONS

• Low-Voltage Applications Stepping Down from
5-V or 3.3-V Rail

• Notebook/Desktop Computers

DESCRIPTION

The TPS51461 is a fully integrated synchronous buck
regulator employing D-CAP+™. It is used for up to
5-V step-down where system size is at its premium,
performance and optimized BOM are must-haves.

This device fully supports Intel system agent
applications with integrated 2-bit VID function.

The TPS51461 also features two switching frequency
settings (700 kHz and 1 MHz), skip mode, pre-bias
startup, programmable external capacitor soft-start
time/voltage transition time, output discharge, internal
VBST Switch, 2-V reference (±1%), power good and
enable.

The TPS51461 is available in a 4 mm × 4 mm,
24-pin, QFN package (Green RoHs compliant and Pb
free) and is specified from -40°C to 85°C.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2D-CAP+ is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Copyright © 2010–2011, Texas Instruments Incorporated

TPS51461

SLUSAD9B –DECEMBER 2010– REVISED SEPTEMBER 2011

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

(1)

MINIMUM

QUANTITY

no Pb/Br)

T

A

-40°C to 85°C

PACKAGE

Plastic QFN

(RGE)

ORDERING INFORMATION

(2)

ORDERING NUMBER PINS OUTPUT SUPPLY ECO PLAN

TPS51461RGER 24 Tape and reel 3000 Green (RoHS and
TPS51461RGET 24 Mini reel 250

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the TI

website at www.ti.com.

(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

THERMAL INFORMATION

(1)

θ

θ

θ

ψ

ψ

θ

JA
JCtop
JB

JT
JB

JCbot

THERMAL METRIC

Junction-to-ambient thermal resistance 33.6
Junction-to-case (top) thermal resistance 45.0
Junction-to-board thermal resistance 10.8
Junction-to-top characterization parameter 0.2
Junction-to-board characterization parameter 10.4
Junction-to-case (bottom) thermal resistance 3.8

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

TPS51461

RGE (24) PIN

UNITS

°C/W

ABSOLUTE MAXIMUM RATINGS

(1)

over operating free-air temperature range (unless otherwise noted)

VALUE UNIT

MIN MAX

VIN, EN, MODE –0.3 7.0
V5DRV, V5FILT, VBST (with respect to SW) –0.3 7.0

Input voltage range VBST –0.3 12.5 V

VID0, VID1 –0.3 3.6
VOUT –1.0 3.6
SW –2.0 7.0
SW (transient 20 ns and E=5 µJ) –3.0

Output voltage range COMP, SLEW, VREF –0.3 3.6 V

PGND –0.3 0.3
PGOOD –0.3 7.0

Electrostatic Discharge V

Storage temperature T
Junction temperature T
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300 ˚C

(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

Human Body Model (HBM) 2000
Charged Device Model (CDM) 500

stg
J

–55 150 ˚C
–40 150 ˚C

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SLUSAD9B –DECEMBER 2010– REVISED SEPTEMBER 2011

RECOMMENDED OPERATING CONDITIONS

VALUE

MIN TYP MAX

VIN, EN, MODE –0.1 6.5
V5DRV, V5FILT, VBST(with respect to SW) –0.1 5.5

Input voltage range VBST –0.1 11.75 V

VID0, VID1 –0.1 3.5
VOUT –0.8 2.0
SW –1.8 6.5

Output voltage range V

Ambient temperature range, T

COMP, SLEW, VREF –0.1 3.5
PGOOD –0.1 6.5
PGND –0.1 0.1

A

-40 85 °C

UNIT

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TPS51461

SLUSAD9B –DECEMBER 2010– REVISED SEPTEMBER 2011

ELECTRICAL CHARACTERISTICS

over recommended free-air temperature range, V
otherwise noted)

PARAMETER CONDITIONS MIN TYP MAX UNIT

SUPPLY: VOLTAGE, CURRENTS AND 5 V UVLO

I

VINSD

V

5VIN

I

5VIN

I

5VINSD

V

V5UVLO

V

V5UVHYS

V

VREFUVLO

V

VREFUVHYS

V

POR5VFILT

VOLTAGE FEEDBACK LOOP: VREF, VOUT, AND VOLTAGE GM AMPLIFIER

V

OUTTOL

V

VREF

I

VREFSNK

G

M

V

DM

I

COMPSRC

V

OFFSET

R

DSCH

f

–3dbVL

CURRENT SENSE: CURRENT SENSE AMPLIFIER, OVER CURRENT AND ZERO CROSSING

A

CSINT

I

OCL

I

OCL(neg)

V

ZXOFF

DRIVERS: BOOT STRAP SWITCH

R

DSONBST

I

BSTLK

(1) Ensured by design, not production tested.

VIN shutdown current EN = 'LO' 0.02 5 µA
5VIN supply voltage V5DRV and V5FILT voltage range 4.5 5.0 5.5 V
5VIN supply current EN =’HI’, V5DRV + V5FILT supply current 1.1 2 mA
5VIN shutdown current EN = ‘LO’, V5DRV + V5FILT shutdown current 10 50 µA
V5FILT UVLO Ramp up; EN = 'HI' 4.2 4.3 4.5 V
V5FILT UVLO hysteresis Falling hysteresis 440 mV
REF UVLO
REF UVLO hysteresis

(1)

(1)

Rising edge of VREF, EN = 'HI' 1.8 V

Reset OVP latch is reset by V5FILT falling below the reset threshold 1.5 2.3 3.1 V

VOUT accuracy V
VREF I

VREF

VREF sink current VREF within tolerance, V
Transconductance 1 mS
Differential mode input voltage 0 80 mV
COMP pin maximum sourcing current V
Input offset voltage TA= 25°C –5 0 5 mV
Output voltage discharge resistance 42 Ω
–3dB Frequency

Internal current sense gain 43 53 57 mV/A

(1)

Gain from the current of the low-side FET to PWM comparator

when PWM = "OFF"
Positive overcurrent limit (valley) 6 7.5 A
Negative overcurrent limit (valley) –6.5 –5.0 A
Zero crossing comp internal offset 0 mV

Internal BST switch on-resistance I

VBST

Internal BST switch leakage current V

= 5.0 V, V

VIN

= 0.8V, No droop –1.5% 0% 1.5%

VOUT

V5DRV

= V

V5FILT

= 0 µA, TA= 25°C 2.01 V

= 2.05 V 2.5 mA

VREF

= 2 V –80 µA

COMP

= 10 mA, TA= 25°C 5 10 Ω

= 14 V, VSW= 7 V, TA= 25°C 1 µA

VBST

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= 5 V, MODE = OPEN, PGND = GND (unless

100 mV

6 MHz

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ELECTRICAL CHARACTERISTICS (continued)

over recommended free-air temperature range, V
otherwise noted)

PARAMETER CONDITIONS MIN TYP MAX UNIT

PROTECTION: OVP, UVP, PGOOD, and THERMAL SHUTDOWN

V

PGDLL

V

PGHYSHL

V

PGDLH

V

PGHYSHH

V

INMINPG

V

OVP

V

UVP

TH

SD

TH

SD(hys)

TIMERS: ON-TIME, MINIMUM OFF TIME, SS, AND I/O TIMINGS

t

ONESHOTC

t

MIN(off)

t

PGDDLY

t

PGDPDLYH

t

PGDPDLYL

t

OVPDLY

t

UVDLYEN

t

UVPDLY

I

SLEW

LOGIC PINS: I/O VOLTAGE AND CURRENT

V

PGDPD

I

PGDLKG

V

ENH

V

ENL

I

EN

V

VIDH

V

VIDL

V

MODETH

I

MODE

R

PD

(2) Ensured by design, not production tested.
(3) See Table 3 for descriptions of MODE parameters.

PGOOD deassert to lower
(PGOOD → Low)

Measured at the VOUT pin w/r/t V
PGOOD high hysteresis 8%

PGOOD de-assert to higher
(PGOOD → Low)

Measured at the VOUT pin w/r/t V
PGOOD high hysteresis -8%

Minimum VIN voltage for valid Measured at the VIN pin with a 2-mA sink current on PGOOD
PGOOD pin

OVP threshold Measured at the VOUT pin w/r/t V
UVP threshold 66% 68% 70%
Thermal shutdown

Thermal Shutdown hysteresis

PWM one-shot

(2)

(2)

(2)

Minimum OFF time 357 ns

Measured at the VOUT pin w/r/t V

begins soft-stop

Latch off controller, attempt soft-stop. 130 °C

Controller re-starts after temperature has dropped 10 °C

V

V

V

SW = PGND, V
PGOOD startup delay time (excl. Delay starts from VOUT = VID code 00 and excludes SLEW

SLEW ramp up time) ramp up time
PGOOD high propagation delay time 50 mV over drive, rising edge 0.8 1 1.2 ms
PGOOD low propagation delay time 50 mV over drive, falling edge 10 µs
OVP delay time Time from the VOUT pin out of +20% of V
Undervoltage fault enable delay (excl. Time from (VOUT = VID code 00) going high to undervoltage

SLEW ramp up time) fault is ready
UVP delay time Time from the VOUT pin out of –30% of V
Soft-start and voltage transition CSS= 10 nF assuming voltage slew rate of 1 mV/µs 9 10 11 µA

PGOOD pull down voltage PGOOD low impedance, I
PGOOD leakage current PGOOD high impedance, forced to 5.5 V –1 0 1 µA
EN logic high EN, VCCP logic 0.8 V
EN logic low EN,VCCP logic 0.3 V
EN input current 1 µA
VID logic high VID0, VID1 0.8 V
VID logic low VID0, VID1 0.3 V

MODE 1 0.08 0.13 0.18

MODE 3 0.37 0.42 0.47
MODE threshold voltage

(3)

MODE 4 0.55 0.60 0.65 V

MODE 5 0.83 0.88 0.93

MODE 7 1.75 1.80 1.85
MODE current 15 µA
VID pull-down resistance 10 kΩ

VIN
VIN
VIN

= 5.0 V, V

VIN

= 5 V, V
= 5 V, V
= 5 V, V

VOUT
VOUT
VOUT

VOUT

SLUSAD9B –DECEMBER 2010– REVISED SEPTEMBER 2011

V5DRV

= V

= 5 V, MODE = OPEN, PGND = GND (unless

V5FILT

SLEW

SLEW

82% 84% 86%

114% 116% 118%

0.9 1.3 1.5 V

SLEW

, device latches OFF,

SLEW

118% 120% 122%

= 0.8 V, fSW= 667 kHz, fixed VID mode 240 ns
= 0.8 V, fSW= 1 MHz, fixed VID mode 160 ns
= 0.8 V, fSW= 1 MHz, DRVL on,

< V

SLEW

3 ms

to OVP fault 0.2 µs

SLEW

3 ms

to UVP fault 8.5 µs

SLEW

SINK

= 4 mA, V

VIN

= V

= 4.5 V 0.3 V

V5FILT

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TPS51461RGE

VIN

VIN

SW

SW

VIN

PGND

PGND

PGND

SW

SW

SW

BST

EN

MODE

VOUT

COMP

SLEW

VREF

GND

VID0

VID1

PGOOD

V5DRV

V5FILT

2

3

4

5

6

7 8

9 10

11

1

12

13

14

15

16

17

18

24 23

22 21

20 19

Thermal Pad

TPS51461

SLUSAD9B –DECEMBER 2010– REVISED SEPTEMBER 2011

PIN

NO. NAME

19
20 PGND I Power ground. Source terminal of the rectifying low-side power FET. Positive input for current sensing.
21
22
23 VIN I Power supply input pin. Drain terminal of the switching high-side power FET.
24

1 GND – Signal ground.
2 VREF O 2.0-V reference output. Connect a 0.22-µF ceramic capacitor to GND.
3 COMP O Connect series R/C or R between this pin and VREF for loop compensation.
4 SLEW I/O Program the startup and voltage transition time using an external capacitor via 10-µA current source.
5 VOUT I Output voltage monitor input pin.
6 MODE I Allows selection of switching frequencies and output voltage. (See Table 3)
7
8

9 SW I/O Switching node output. Connect to the external inductor. Also serve as current-sensing negative input.
10
11
12 Power supply for internal high-side gate driver. Connect a 0.1-µF bootstrap capacitor between this pin and

13 EN I Enable of the SMPS.
14 VID0
15 VID1
16 PGOOD O Power good output. Connect pull-up resistor.
17 V5FILT I 5-V power supply for analog circuits.
18 V5DRV I 5-V power supply for the gate driver.

BST I

I/O DESCRIPTION

the SW pin.

I 2-bit VID input.

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RGE PACKAGE

PIN FUNCTIONS

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19

7

PGND

SW

TPS51461

OC

ZC

XCON

12 BST

18 V5DRV

PWM

5

EN

16 PGOOD

Control Logic

UDG-10184

+

+

V

REFIN

+20%

+

+

13

VOUT

+

VIN

t

ON

One-

Shot

UV

OV

V

REFIN

–32%

4SLEW

+

8 R

3COMP

R

1GND

2VREF

On-Time

and LL

Selection

15 mA

6 MODE

V

REFIN

+8/16 %

V

REFIN

–8/16 %

+

+

Discharge

UVP

OVP

17 V5FILT

Bandgap

Sense

+

00 01 10 11

+

VS

CS

14 VID0

15 VID1

10 mA

SW

PGND

22

23

24

VIN

VIN

8 SW

9 SW

10 SW

11 SW

20 PGND

21 PGND

VCS

TPS51461

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BLOCK DIAGRAM

SLUSAD9B –DECEMBER 2010– REVISED SEPTEMBER 2011

VID 0 VID 1 VCCSA

0 0 0.9 V
0 1 0.80V
0 1 0.85V

Table 1. Intel SA VID

(1)

MODE = Open

(1)

MODE = 33 kΩ
1 0 0.725 V
1 1 0.675 V

(1) 0.80V for 2011 SV processor and 0.85V for 2011 LV/ULV processor

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TPS

51461

VIN

VIN

SW

SW

VIN

PGND

PGND

PGND

SWSWSW

BST

EN

MODE

VOUT

COMP

SLEW

VREF

GND

VID0

VID1

PGOOD

V5DRV

V5FILT

19

20

21

22

23

24

1

2

3

4

5

6

12

11

10

9

8

7

18

17

16

15

14

13

0.1

mF

DNP

L

0.42

mH

22 mF

DNP

DNP

VCCSA

VCCSASNS

UDG-10185

0.22

mF

10 k

W

10 nF

ENABLE

VID0VID

1

+5V

0 W

1 mF

2 kW

PGOOD

0.1

mF

10 mF

10 mF

VIN

22 mF

22 mF

22 mF

22 mF

22 mF

2.2

mF

2 kW

100

kW

2 kW

TPS51461

SLUSAD9B –DECEMBER 2010– REVISED SEPTEMBER 2011

APPLICATION SCHEMATIC WITH TPS51461

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and Recommended Reference Design for Intel SA Application

Figure 1. Application Schematic Using Droop Configuration,

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TPS

51461

VIN

VIN

SW

SW

VIN

PGND

PGND

PGND

SWSWSW

BST

EN

MODE

VOUT

COMP

SLEW

VREF

GND

VID0

VID1

PGOOD

V5DRV

V5FILT

19

20

21

22

23

24

1

2

3

4

5

6

12

11

10

9

8

7

18

17

16

15

14

13

0.1

mF

DNP

L

0.42

mH

22 mF

100

W

DNP

DNP

VCCSA

VCCSASNS

UDG-10186

0.22

mF

5 kW

10 nF

ENABLE

VID0VID

1

+5V

0 W

1 mF

2 kW

100

kW

PGOOD

0.1

mF

10 mF

10 mF

VIN

22 mF

22 mF

22 mF

2.2

mF

3.3 nF

2 kW

TPS51461

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SLUSAD9B –DECEMBER 2010– REVISED SEPTEMBER 2011

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Figure 2. Application Schematic Using Non-Droop Configuration

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TPS51461

SLUSAD9B –DECEMBER 2010– REVISED SEPTEMBER 2011

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Application Circuit List of Materials

Recommended parts for key external components for the circuits in Figure 1 and Figure 2 are listed in Table 2.

Table 2. Key External Component Recommendations

(Figure 1 and Figure 2)

FUNCTION MANUFACTURER PART NUMBER

Output Inductor Nec-Tokin MPCG0740LR42C

Ceramic Output Capacitors

Panasonic ECJ2FB0J226M
Murata GRM21BR60J226ME39L

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