Texas Instruments TPS51220RHBR Schematic [ru]

1

2

3

4

24

23

22

21

DRVH2

VIN

VREG3

EN2

DRVH1

V5SW

RF

EN1

TPS51220RHB

(QFN32)

5

6

7

8

20

19

18

17

PGOOD2

SKIPSEL2

CSP2

CSN2

PGOOD1

SKIPSEL1

CSP1

CSN1

9

VFB1

32

SW1

31

VBST1

30

DRVL1

29

VREG5

28

GND

27

DRVL2

26

VBST2

25

SW2

10

COMP111FUNC12EN13VREF214TRIP15COMP216VFB2

VO1

5.0V

L1

C22

VBAT

PowerPAD

C02

C01

VREG5
5V/100mA

R23

R13

C11

R11

PGOOD1

EN

EN1

VREG3

3.3V/10mA

Q11

Q12

Q22

Q21

C13

R12

GND

R14

GND

GND

GND

L2

R24

GND

C23

C21

R21

R22

GND

PGOOD2

EN2

VO2

3.3V

C03

R01

PGND

GND

SKIPSEL1 SKIPSEL2

VBAT

VO2

C12

VBAT

VO1

VO1

VREG5

C14

PGND

PGND

PGND

PGND

PGND

PGND PGND

C24

GND

TPS51220

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SLVS785C –OCTOBER 2007–REVISED JULY 2009

Fixed Frequency, 99% Duty Cycle Peak Current Mode Notebook System Power Controller

Check for Samples: TPS51220

1

FEATURES

2

• Input Voltage Range: 4.5 V to 28 V

• Output Voltage Range: 1 V to 12 V • OCL/OVP/UVP/UVLO Protections

• Selectable Light Load Operation
(Continuous / Auto Skip / Out-Of-Audio™ Skip) • Thermal Shutdown (Non-Latch)

• Programmable Droop Compensation • Output Discharge Function (Disable Option)

• Voltage Servo Adjustable Soft Start • Integrated Boot Strap MOSFET Switch

• 200 kHz to 1 MHz Fixed Frequency PWM • QFN-32 (RHB)

• Selectable Current/ D-CAP™ Mode
Architecture

• 180° Phase Shift Between Channels

• Resistor or Inductor DCR Current Sensing

DESCRIPTION

The TPS51220 is a dual synchronous buck regulator controller with 2 LDOs. It is optimized for 5-V/3.3-V system
controller, enabling designers to cost effectively complete 2-cell to 4-cell notebook system power supply. The
TPS51220 supports high efficiency, fast transient response and 99% duty cycle operation. It supports supply
input voltage ranging from 4.5 V to 28 V, and output voltages from 1 V to 12 V. Two types of control schemes
can be chosen depending on the application. Peak current mode supports stability operation with lower ESR
capacitor and output accuracy. The D-CAP mode supports fast transient response. The high duty (99%)
operation and the wide input/output voltage range supports flexible design for small mobile PCs and a wide
variety of other applications. The fixed frequency can be adjusted from 200 kHz to 1 MHz by a resistor, and each
channel runs 180° out of phase. The TPS51220 can also synchronize to the external clock, and the interleaving
ratio can be adjusted by its duty. The TPS51220 is available in the 32 pin 5x5 QFN package and is specified
from –40°C to 85°C.

• Powergood Output for Each Channel

(OVP Disable Option)

APPLICATIONS

• Notebook Computer System and I/O Bus

• Point of Load in LCD TV, MFP

Figure 1. TYPICAL APPLICATION CIRCUIT

1

2Out-Of-Audio, D-CAP, PowerPAD are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright © 2007–2009, Texas Instruments Incorporated

XCON

VBST1

DRVH1

SW1

DRVL1

GND

VREG5

VREG5

GND

Control

Logic

PGOOD1

GND

Delay

+

+

+

+

1V+5%/10%

1V-5%/10%

1V-30%

1V+15%

+

PWM

Skip

Ramp
Comp

+

+

VFB1

COMP1

EN1

Enable/

Soft-start

1V

+

CSN1

CSP1

TRIP

Discharge

Control

GND

100mV

+

V5SW

4.7V/4.5V

GND

VREG5

+

VREF2

GND

GND

1.25V

GND

1.25V

GND

+

VREG3

+

4.7V/4.5V

VIN

EN

+

4.2V/3.8V

150/140

Deg-C

V5OK

THOK

Ready

+

SKIPSEL1

FUNC

OSC

RF

CLK1

CLK2

Fault1

SDN1

UVP

OVP

Fault2

SDN2

Ready

GND

Channel-1Switchershown

+

VREF2

D-CAP

CUR

CLK1

VREF2

+

OCP

Ramp
Comp

+

N-OCP

100mV

OOA

Ctrl

+

VFB-AMP

CS-AMP

TPS51220

SLVS785C –OCTOBER 2007–REVISED JULY 2009

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

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FUNCTIONAL BLOCK DIAGRAM

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TPS51220

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ABSOLUTE MAXIMUM RATINGS

(1)

over operating free-air temperature range (unless otherwise noted)

VIN –0.3 to 30 V
VBST1, VBST2 –0.3 to 35 V
VBST1, VBST2
SW1, SW2 –7 to 30 V

V

I

Input voltage range

(2)

CSP1, CSP2, CSN1, CSN2 –1 to 13.5 V
EN, EN1, EN2, VFB1, VFB2, TRIP, SKIPSEL1, SKIPSEL2, FUNC –0.3 to 7 V
V5SW –0.3 to 7 V
V5SW (to VREG5)
DRVH1, DRVH2 –7 to 35 V
DRVH1, DRVH2

V

O

Output voltage range

(2)

DRVL1, DRVL2, COMP1, COMP2, VREG5, RF, VREF2,
PGOOD1, PGOOD2

VREG3 –0.3 to 3.6 V

T

J

T

stg

Operating junction temperature range –40 to 125 °C
Storage temperature –55 to 150 °C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the network ground terminal unless otherwise noted.
(3) Voltage values are with respect to the corresponding SW terminal.
(4) When EN is high and V5SW is grounded, or voltage is applied to V5SW when EN is low.

(3)

(4)

(3)

SLVS785C –OCTOBER 2007–REVISED JULY 2009

VALUE UNIT

–0.3 to 7 V

–7 to 7 V

–0.3 to 7 V
–0.3 to 7 V

DISSIPATION RATINGS (2 oz. Trace and Copper Pad with Solder)

PACKAGE

32 pin RHB 2.2 W 23 mW/°C 0.9 W

TA< 25°C DERATING FACTOR TA= 85°C

POWER RATING ABOVE TA= 25°C POWER RATING

RECOMMENDED OPERATING CONDITIONS

V

V
V

T

Supply

SS

voltage

I

I/O voltage V

O

Operating free-air temperature –40 85 °C

A

VIN 4.5 28 V
V5SW –0.8 6
DRVH1, DRVH2 –4.0 33
VBST1, VBST2, –0.1 33
DRVH1, DRVH2 (wrt SW1, SW2) –0.1 6
DRVH1, DRVH2 (negative overshoot -6 V for t< 20% duration of switching period) –6 33
SW1, SW2 –4.0 28
SW1, SW2 (negative overshoot -6 V for t< 20% duration of switching period) –6 28
CSP1, CSP2, CSN1, CSN2 –0.8 13
EN, EN1, EN2, VFB1, VFB2, TRIP, DRVL1, DRVL2, COMP1, COMP2, VREG5,

RF, VREF2, PGOOD1, PGOOD2, SKIPSEL1, SKIPSEL2, FUNC
VREG3 –0.1 3.5

MIN TYP MAX UNIT

–0.1 6

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TPS51220

SLVS785C –OCTOBER 2007–REVISED JULY 2009

ORDERING INFORMATION

T

A

-40°C to 85°C

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

PACKAGE

Plastic Quad Flat Pack

(32 Pin QFN)

(1)

ORDERABLE PART

NUMBER

TPS51220RHBT Tape and Reel 250

TPS51220RHBR Tape and Reel 3000

TRANSPORT MEDIA QUANTITY

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ELECTRICAL CHARACTERISTICS

over operating free-air temperature range, EN = 3.3V, VIN = 12V, V5SW = 5V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SUPPLY CURRENT

I

(VINSDN)

I

(VINSTBY)

I

(VBATSTBY)

I

(V5SW)

VIN shutdown current 7 15 μA

VIN standby current 80 120 μA

V

standby current 500 μA

BAT

V5SW supply current

VREF2 OUTPUT

V

(VREF2)

VREF2 output voltage V

VREG3 OUTPUT

V

(VREG3)

I

(VREG3)

VREG3 output voltage V

VREG3 output current VREG3 = 3 V 10 15 20 mA

VREG5 OUTPUT

V

(VREG5)

I

(VREG5)

V

(THV5SW)

t

d(V5SW)

R

(V5SW)

VREG5 output voltage 6 V < VIN < 25 V

VREG5 output current mA

Switchover threshold V

Switchover delay Turning on 7.7 ms
5V SW on-resistance I

OUTPUT

V

regulation voltage

V

(VFB)

I

(VFB)

R

(Dischg)

F B

tolerance
V

input current VFBx = 1.05 V, COMPx = 1.8 V, TA= 25°C –50 50 nA

F B

CSNx discharge resistance ENx = 0 V, CSNx = 0.5 V, TA= 25°C 20 40 Ω

VOLTAGE TRANSCONDUCTANCE AMPLIFIER

Gmv Gain TA= 25°C 500 μS
V

ID

I

(COMPSINK)

I

(COMPSRC)

Differential input voltage
range

COMP maximum sink
current

COMP maximum source
current

(1) Specified by design. Detail external condition follows application circuit of Figure 53.

VIN shutdown current, TA= 25°C,
No Load, EN = 0V, V5SW = 0 V

VIN standby current, TA= 25°C, No Load,
EN1 = EN2 = V5SW = 0 V

V

standby current, TA= 25°C, No Load

BAT

SKIPSEL2 = 2V, EN2 = open, EN1 = V5SW = 0V
V5SW current, TA= 25°C, No Load,

ENx = 5V, VFBx = 1.05 V

I

< ±10 μA, TA= 25°C 1.98 2.00 2.02

(VREF2)

I

< ±100 μA, 4.5V < VIN < 25 V 1.97 2.00 2.03

(VREF2)

V5SW = 0 V, I
V5SW = 0 V, 0 mA < I

5.5 V < VIN < 25 V

V5SW = 0 V, I
V5SW = 0 V, 0 mA < I

V5SW = 0 V, 0 mA < I

5.5 V < VIN < 25 V

= 0 mA, TA= 25°C 3.279 3.313 3.347

(VREG3)

< 10 mA,

(VREG3)

= 0 mA, TA= 25°C 4.99 5.04 5.09

(VREG5)

< 100 mA,

(VREG5)

< 100 mA,

(VREG5)

TRIP = 5 V 1.2 mA
TRIP = 0 V 1.4 mA

V5SW = 0 V, VREG5 = 4.5 V 100 150 200
V5SW = 5 V, VREG5 = 4.5 V 200 300 400
Turning on 4.55 4.7 4.8
Hysteresis 0.15 0.20 0.25

= 100 mA 0.5 Ω

(VREG5)

TA= 25°C, No Load 0.9925 1.000 1.0075
TA= –40°C to 85°C , No Load 0.990 1.000 1.010

COMPx = 1.8 V 33 μA

COMPx = 1.8 V –33 μA

SLVS785C –OCTOBER 2007–REVISED JULY 2009

(1)

3.135 3.300 3.400

4.90 5.03 5.15

4.50 5.03 5.15 V

–30 30 mV

V

V

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TPS51220

SLVS785C –OCTOBER 2007–REVISED JULY 2009

ELECTRICAL CHARACTERISTICS (continued)

over operating free-air temperature range, EN = 3.3V, VIN = 12V, V5SW = 5V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

CURRENT AMPLIFIER

G

C

V

IC

V

ID

Gain

Common mode input
voltage range

Differential input voltage
range

POWERGOOD

V

(THPG)

I

(PG)

t

(PGDLY)

PG threshold PG in from higher 102.5% 105% 107.5%

PG sink current PGOOD = 0.5 V 5 mA
PGOOD delay Delay for PG in 0.8 1 1.2 ms

SOFTSTART

t

(SSDYL)

t

(SS)

Soft-start delay time Delay for Soft Start, ENx = Hi to SS-ramp starts 200 μs
Soft-start Time Internal Soft Start 960 μs

FREQUENCY AND DUTY CONTROL

f

(SW)

V

(THRF)

f

(SYNC)

Switching frequency Rf = 330 kΩ 273 303 333 kHz

RF threshold

Syncronization Input
Frequency Range

(2)

tONmin Minimum On Time V
t

min Minimum Off Time V

OFF

t

V
V

D

(DTH)
(DTL)

Dead time

DRVH-off threshold DRVH to GND
DRVL-off threshold DRVL to GND

OUTPUT DRIVERS

R

(DRVH)

R

(DRVL)

DRVH resistance Ω

DRVL resistance Ω

CURRENT SENSE

V

(OCL-ULV)

V

(OCL-LV)

V

(ZC)

Current limit threshold
(ultra-low voltage)

Current limit threshold
(low voltage)

Zero cross detection
comparator Offset

Negative current limit TRIP = 0V/2V, TA= 25°C –24 –31 –38

V

(OCLN-ULV)

threshold
(ultra-low voltage)

Negative current limit TRIP = 3.3V/5V, TA= 25°C –51 –60 –69

V

(OCLN-LV)

threshold
(low voltage)

(2) Specified by design.

TRIP = 0V/2V, CSN = 5V, TA= 25°C
TRIP = 3.3V/5V, CSN = 5V, TA= 25°C

TA= 25°C –75 75 mV

PG in from lower 92.5% 95% 97.5%

PG hysteresis 5%

Lo to Hi 0.7 1.3 2 V
Hysteresis 0.2 V

= 90% to 10%, No Load 120 150 ns

(DRVH)

= 10% to 90%, No Load 290 440 ns

(DRVH)

DRVH-off to DRVL-on 10 30 50 ns
DRVL-off to DRVH-on 30 40 70 ns

(2)

(2)

Source, V
Sink, V

(DRVH-SW)

Source, V
Sink, V

(DRVL-GND)

(VBST-DRVH)

(VREG5-DRVL)

= 0.1 V 1.7 5

= 0.1 V 1 3

= 0.1 V 1.3 4

= 0.1 V 0.7 2

TRIP = 0V/2V, TA= 25°C 27 31 35
TRIP = 0V/2V 25 31 37
TRIP = 3.3V/5V, TA= 25°C 56 60 64
TRIP = 3.3V/5V 54 60 66

0.95V < CSNx < 12.6V –4 0 4 mV

TRIP = 0V/2V –22 –31 –40

TRIP = 3.3V/5V –49 –60 –71

(2)

(2)

0 13 V

200 1000 kHz

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3.333

1.667

1 V
1 V

mV

mV

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SLVS785C –OCTOBER 2007–REVISED JULY 2009

ELECTRICAL CHARACTERISTICS (continued)

over operating free-air temperature range, EN = 3.3V, VIN = 12V, V5SW = 5V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

UVP, OVP AND UVLO

V

(OVP)

t

(OVPDLY)

V

(UVP)

t

(UVPDLY)

V

(UVREF2)

V

(UVREG3)

V

(UVREG5)

INTERFACE AND LOGIC THRESHOLD

V

(EN)

V

(EN12)

V

(EN12SS)

V

(EN12SSEND)

I

(EN12)

V

(SKIPSEL)

V

(TRIP)

V

(FUNC)

I

(TRIP)

I

(SKIPSEL)

BOOT STRAP SW

V

(FBST)

I

(BSTLK)

THERMAL SHUTDOWN

T

(SDN)

OVP Trip Threshold OVP detect 110% 115% 120%
OVP Prop Delay 1.5 μs
UVP Trip Threshold UVP detect 65% 70% 73%
UVP Delay 0.8 1 1.2 ms

VREF2 UVLO Threshold

VREG3 UVLO Threshold V

VREG5 UVLO Threshold

EN Threshold V

EN1/EN2 Threshold V

EN1/EN2 SS Start
Threshold

EN1/EN2 SS End
Threshold

Wake up 1.7 1.8 1.9 V
Hysteresis 75 100 125 mV
Wake up 3 3.1 3.2
Hysteresis 0.10 0.15 0.20
Wake up 4.1 4.2 4.3 V
Hysteresis 0.35 0.40 0.44 V

Wake up 0.8 1 1.2
Hysteresis 0.1 0.2 0.3
Wake up 0.45 0.50 0.55
Hysteresis 0.1 0.2 0.3

SS-ramp start threshold at external soft start 1 V

SS-End threshold at external soft start

(3)

EN1/EN2 Source Current VEN1/EN2 = 0V 1.5 2 2.6 μA

Continuous 1.5

SKIPSEL1/SKIPSEL2
Setting Voltage

Auto Skip 1.9 2.1
OOA Skip (min 1/8 Fsw) 3.2 3.4
OOA Skip (min 1/16 Fsw) 3.8
V

(OCL-ULV)

V

TRIP Setting Voltage V

(OCL-ULV)

V

(OCL-LV)

V

(OCL-LV)

, Discharge ON 1.5

, Discharge OFF 1.9 2.1
, Discharge OFF 3.2 3.4
, Discharge ON 3.8

Current mode, OVP enable 1.5

FUNC Setting Voltage V

D-CAP mode, OVP disable 1.9 2.1
D-CAP mode, OVP enable 3.2 3.4
Current mode, OVP disable 3.8

TRIP Input Current μA

SKIPSEL Input Current μA

Forward Voltage V

TRIP = 0 V –1 1
TRIP =5 V –1 1
SKIPSELx = 0 V –0.5 0.5
SKIPSELx = 5 V –0.5 0.5

VREG5-VBST

, IF= 10 mA, TA= 25°C 0.10 0.20 V

VBST Leakage Current VBST = 30 V, SW = 25 V 0.01 1.5 μA

Thermal SDN Threshold °C

Shutdown temperature
Hysteresis

(3)

(3)

TPS51220

2 V

V

150

10

(3) Specified by design.

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DRVH2

VIN

VREG3

EN2

DRVH1

V5SW

RF

EN1

PGOOD2
SKIPSEL2
CSP2
CSN2

PGOOD1

SKIPSEL1

CSP1

CSN1

VFB1

SW1

VBST1

DRVL1

VREG5

GND

DRVL2

VBST2

SW2

COMP1

FUNC

EN

VREF2

TRIP

COMP2

VFB2

24
23
22
21

20
19

18
17

1

2

3
4

5
6

7
8

9

10

11

12

13

14

15

16

32

31

30

29

28

27

26

25

RHBPACKAGE

(TOP VIEW)

TPS51220

SLVS785C –OCTOBER 2007–REVISED JULY 2009

PINOUT

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DEVICE INFORMATION

TERMINAL FUNCTIONS

TERMINAL

NAME NO.

DRVH1 1
DRVH2 24
SW2 25
SW1 32

VREG3 22 O
EN1 4

EN2 21
PGOOD1 5
PGOOD2 20
SKIPSEL1 6 Skip mode selection pin.

SKIPSEL2 19

CSP1 7 Current sense comparator inputs (+). An RC network with high quality X5R or X7R ceramic capacitor should
CSP2 18
CSN1 8

CSN2 17
VFB1 9
VFB2 16
COMP1 10 Loop compensation pin for current mode (error amplifier output). Connect R (and C if required) from this pin

COMP2 15

RF 3 I/O

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I/O DESCRIPTION

High-side MOSFET gate driver outputs. Source 1.7Ω, sink 1.0Ω, SW-node referenced floating driver. Drive

O

voltage corresponds to VBST to SW voltage.

I/O High-side MOSFET gate driver returns.

Always alive 3.3-V, 10-mA low dropout linear regulator output. Bypass to (signal) GND with more than 1-μF
ceramic capacitor. Runs from VIN supply or from VREG5 when it is switched over to V5SW input.

Channel 1 and channel 2 SMPS enable Pins. When turning on, apply greater than 0.55 V and less than 6 V,

I

or be floating. Connect to GND to disable. Adjustable soft-start capacitance to be attached here.
Power Good window comparator outputs for channel 1 and channel 2. The applied voltage should be less

O

than 6 V, and the recommended pull-up resistance value is from 100 kΩ to 1 MΩ.

I

I/O be used to extract voltage drop across DCR. 0.1 μF is a good value to start the design. See the current

I

I

I

GND: Continuous conduction mode
VREF2: Auto skip
VREG3: OOA auto skip, maximum 7 skips (suitable for fsw< 400 kHz)
VREG5: OOA auto skip, maximum 15 skips (suitable for equal to or greater than 400 kHz)

sensing scheme section for more details.
Current sense comparator inputs (–). See the current sensing scheme section. Used as power supply for the

current sense circuit for 5 V or higher output voltage setting. Also, used for output discharge terminal.
SMPS voltage feedback inputs. Connect the feedback resistors divider, and should be referred to (signal)

GND.

to VREF2 for proper loop compensation with current mode operation. Ramp compensation adjustable pin for
D-CAP mode, connect R from this pin to VREF2. 10 kΩ is a good value to start the design. 6 kΩ to 20 kΩ
can be chosen. See the D-CAP MODE section for more details.

Frequency setting pin. Connect a frequency setting resistor to (signal) GND. Connect to an external clock for
synchronization.

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TERMINAL FUNCTIONS (continued)

TERMINAL

NAME NO.

FUNC 11 I

VREF2 13 O 2-V Reference Output. Bypass to (signal) GND by 0.22μF ceramic capacitor.

TRIP 14 I

EN 12 I
VBST1 31 Supply inputs for high-side NFET driver (boot strap Terminal). Connect a capacitor (0.1μF or greater is

VBST2 26
DRVL1 30

DRVL2 27

V5SW 2 I voltage is higher than 4.8 V, switch-over function will be enabled. (Note) When switch-over is enabled,

VREG5 29 O

VIN 23 I Supply input for 5-V and 3.3-V linear regulator. Typically connected to VBAT.
GND 28 – Ground.

I/O DESCRIPTION

Control architecture and OVP function selection pin.

GND: Current mode, OVP enable
VREF2: D-CAP mode, OVP disable
VREG3: D-CAP mode, OVP enable
VREG5: Current mode, OVP disable

Overcurrent trip level and discharge mode selection pin.

GND: V

(OCL-ULV)

VREF2: V
VREG3: V
VREG5: V

(OCL-ULV)

(OCL-LV)
(OCL-LV)

, Discharge on

, Discharge off
, Discharge off
, Discharge on

VREF2 and VREG5 Linear Regulators Enable Pin. When turning on, apply greater than 1.2V and less than
6V. Connect to GND to Disable.

I recommended) from this pin to respective SW terminal. Additional SB diode from VREG5 to this pin is an

optional.

O Low-side MOSFET gate driver outputs. Source 1.3 Ω, sink 0.7 Ω, GND referenced driver.

VREG5 switchover power supply input pin. When EN1 is high, PGOOD1 indicates GOOD and V5SW
VREG5 output voltage will be almost the same as V5SW input voltage.

5-V, 100-mA low-dropout linear regulator output. Bypass to (power) GND using a 10-μF ceramic capacitor.
Runs from VIN supply. Internally connected to VBST and DRVL. Shuts off with EN. Switches over to V5SW
when 4.8 V or above is provided. (Note: when switch-over (above V5SW) is enabled, VREG5 output voltage
is approximately the same as V5SW input voltage.)

SLVS785C –OCTOBER 2007–REVISED JULY 2009

Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback 9

Product Folder Links :TPS51220

0

20

40

60

80

100

120

-50 0 50 100 150
T -JunctionTemperature- CJ°

I -StandbyCurrent- Am

(VINSTBY)

0

20

40

60

80

100

120

5 10 15 20 25 30

V -VINInputVoltage-V

I

I -StandbyCurrent- mA

(VINSTBY)

0

3

6

9

12

15

5 10 15 20 25 30

V -VINInputVoltage-V

I

RT

I -ShutdownCurrent- μA

(VINSDN)

0

3

6

9

12

15

-50 0 50 100 150

T -JunctionTemperature- CJ°

I -ShutdownCurrent- μA

(VINSDN)

VIN=12V

TPS51220

SLVS785C –OCTOBER 2007–REVISED JULY 2009

VIN SHUTDOWN CURRENT VIN SHUTDOWN CURRENT

vs vs

INPUT VOLTAGE JUNCTION TEMPERATURE

www.ti.com

TYPICAL CHARACTERISTICS

Figure 2. Figure 3.

VIN STANDBY CURRENT VIN STANDBY CURRENT

JUNCTION TEMPERATURE INPUT VOLTAGE

vs vs

Figure 4. Figure 5.

10 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated

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0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

5 10 15 20 25

V - VIN Input Voltage - V

I

I -BatteryCurrent-mA

(VBAT)

EN=on,EN1=on,EN2=off

1.98

1.99

2.00

2.01

2.02

-100 -50 0 50 100

I -OutputCurrent- μA

O(VREF2)

V -OutputVoltage-V

O(VREF2)

VIN=12V

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

5 10 15 20 25

V - VIN Input Voltage - V

I

I -BatteryCurrent-mA

(VBAT)

EN=on,EN1=on,EN2=on

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

5 10 15 20 25

V -VINInputVoltage-V

I

I -BatteryCurrent-mA

(VBAT)

EN=on,EN1=off,EN2=on

www.ti.com

TPS51220

SLVS785C –OCTOBER 2007–REVISED JULY 2009

NO LOAD BATTERY CURRENT NO LOAD BATTERY CURRENT

BATTERY CURRENT VREF2 OUTPUT VOLTAGE

vs vs

INPUT VOLTAGE INPUT VOLTAGE

Figure 6. Figure 7.

vs vs

INPUT VOLTAGE OUTPUT CURRENT

TYPICAL CHARACTERISTICS (continued)

Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback 11

Figure 8. Figure 9.

Product Folder Links :TPS51220

270

280

290

300

310

320

330

-50 0 50 100 150

T -JunctionTemperature- CJ°

f -SwitchingFrequency-kHz

(SW)

RF=330kΩ

0.00

0.05

0.10

0.15

0.20

0.25

-50 0 50 100 150

T -JunctionTemperature- CJ°

V -ForwardVoltage-V

(FBST)

3.20

3.25

3.30

3.35

3.40

0 2 4 6 8 10

I -OutputCurrent-mA

O(VREG3)

V -OutputVoltage-V

O(VREG3)

VIN=12V

4.90

4.95

5.00

5.05

5.10

0 20 40 60 80 100

I -OutputCurrent-mA

O(VREG5)

V -OutputVoltage-V

O(VREG5)

VIN=12V

TPS51220

SLVS785C –OCTOBER 2007–REVISED JULY 2009

www.ti.com

VREG3 OUTPUT VOLTAGE VREG5 OUTPUT VOLTAGE

OUTPUT CURRENT OUTPUT CURRENT

SWITCHING FREQUENCY FORWARD VOLTAGE OF BOOST SW

JUNCTION TEMPERATURE JUNCTION TEMPERATURE

vs vs

Figure 10. Figure 11.

vs vs

TYPICAL CHARACTERISTICS (continued)

12 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated

Figure 12. Figure 13.

Product Folder Links :TPS51220

T -JunctionTemperature- CJ°

25

27

29

31

33

35

37

V -CurrentLimitThreshold-mV

(OCL-ULV)

-50 0 50 100 150

CSN=1V

CSN=5V

CSN=12V

T -JunctionTemperature- CJ°

54

56

58

60

62

64

66

V -CurrentLimitThreshold-mV

(OCL-LV)

-50 0 50 100 150

CSN=1V

CSN=5V

CSN=12V

50

70

90

110

130

150

-50 0 50 100 150

T -JunctionTemperature- CJ°

OVP/UVP Threshold-%

OVP

UVP

0.0

0.3

0.6

0.9

1.2

1.5

-50 0 50 100 150

T -JunctionTemperature- CJ°

I -VBSTLeakageCurrent- μA

lkg

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TPS51220

SLVS785C –OCTOBER 2007–REVISED JULY 2009

OVP/UVP THRESHOLD VOLTAGE VBST LEAKAGE CURRENT

JUNCTION TEMPERATURE JUNCTION TEMPERATURE

CURRENT LIMIT THRESHOLD CURRENT LIMIT THRESHOLD

JUNCTION TEMPERATURE JUNCTION TEMPERATURE

vs vs

Figure 14. Figure 15.

vs vs

TYPICAL CHARACTERISTICS (continued)

Copyright © 2007–2009, Texas Instruments Incorporated Submit Documentation Feedback 13

Figure 16. Figure 17.

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0

20

40

60

80

100

0.001 0.01 0.1 1 10
I -5-VOutputCurrent- A

O1

h

-Efficiency-%

Auto-skip

CCM

VIN=12V

OOA

50

60

70

80

90

100

0.001 0.01 0.1 1 10

I -5-VOutputCurrent- A

O1

h

-Efficiency-%

Auto-skip

VIN=7V

VIN=12V

VIN=21V

3.20

3.25

3.30

3.35

3.40

5 10 15 20 25

V -VINInputVoltage-V

I

V -3.3-VOutputVoltage-V

O2

IO=0A

IO=6A

IO=3A

CCM

4.90

4.95

5.00

5.05

5.10

5 10 15 20 25

V -VINInputVoltage-V

I

V -5-VOutputVoltage-V

O1

IO=0A

IO=6A

IO=3A

CCM

TPS51220

SLVS785C –OCTOBER 2007–REVISED JULY 2009

www.ti.com

5-V OUTPUT VOLTAGE 3.3-V OUTPUT VOLTAGE

OUTPUT CURRENT OUTPUT CURRENT

vs vs

INPUT VOLTAGE INPUT VOLTAGE

Figure 18. Figure 19.

5-V EFFICIENCY 5-V EFFICIENCY

vs vs

TYPICAL CHARACTERISTICS (continued)

14 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated

Figure 20. Figure 21.

Product Folder Links :TPS51220