High Performance, Single-Synchronous Step-Down Controller
with Differential Voltage Feedback
1
FEATURES
23
• Differential Voltage Feedback
•DC Compensation for Accurate Regulation
•Wide Input Voltage Range: 3 V to 28 V
•Output Voltage Range: 0.5 V to 2.0 V with
Fixed Options of 1.05 V and 1.00 V
•Wide Output Load Range: 0 A to 20 A+
•Adaptive On-Time Modulation with Selectable
Control Architecture and Frequency
– D-CAP™ Mode at 300 kHz/400 kHz for Fast
Transient Response
– D-CAP2™ Mode at 500 kHz/670 kHz for
Ceramic Output Capacitor
•4700 ppm/°C, Low-Side R
•R
Accurate Current Sense Option
SENSE
•Internal, 1-ms Voltage Servo Softstart
•Built-In Output Discharge
•Power Good Output
•Integrated Boost Switch
•Built-In OVP/UVP/OCP
•Thermal Shutdown (Non-latched)
•3 mm × 3 mm, 16-Pin, QFN (RTE) Package
APPLICATIONS
•Notebook Computers
•I/O Supplies
Current Sensing
DS(on)
TPS51219
SLUSAG1B –MARCH 2011– REVISED OCTOBER 2011
DESCRIPTION
The TPS51219 is a small-sized single buck controller
with adaptive on-time control. It provides a choice of
control modes (D-CAP™ or D-CAP2™) to meet a
wide range of system requirements. It is designed for
tight DC regulation requirements such as the VCCIO
application for Intel®notebooks. The performance
and flexibility of the TPS51219 makes it suitable for
low output voltage, high current, PC system power
rails and similar point-of-load (POL) power supplies.
Differentialvoltagefeedbackandthevoltage
compensation function combine to provide high
precision power to load devices.
A small package, fixed voltage options and minimal
external component count saves cost and space,
while a dedicated EN pin and pre-set frequency
selections minimize design effort. The skip-mode at
light load condition, strong gate drivers, and low-side
FET R
operation over a broad load range. The external
resistorcurrent senseoption enablesaccurate
current sensing. The conversion input voltage (the
high-side FET drain voltage) ranges from 3 V to 28 V
and output voltage ranges from 0.5 V to 2.0 V. The
device requires an external 5-V supply.
The TPS51219 is available in a 16-pin, QFN package
and is specified for ambient temperature from -40°C
to 85°C.
current sensing provides high efficiency
DS(on)
1
2D-CAP, D-CAP2 are trademarks of Texas Instruments.
3Intel is a registered trademark of Intel.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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ORDERING INFORMATION
T
A
PACKAGEPINS
–40°C to 85°CPlastic Quad Flat Pack (QFN)16
ORDERABLE DEVICEOUTPUTMINIMUM
NUMBERSUPPLYQUANTITY
TPS51219RTERTape and reel3000
TPS51219RTETMini-reel250
(1)
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature range (unless otherwise noted)
VREF–0.33.6
Junction temperature range, T
Storage temperature range, T
J
STG
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the network ground terminal unless otherwise noted.
(3) Voltage values are with respect to the SW terminal.
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
BST13IHigh-side MOSFET gate driver bootstrap voltage input. Connect a capacitor from the BST pin to the SW pin.
COMP5I
DH11OHigh-side MOSFET gate driver output.
DL10O Low-side MOSFET gate driver output.
EN14IEnable pin. 3.3-V I/O level, 100 ns de-bounce. Short to GND to disable the device.
GND7–Device analog ground; Connect to a quiet point on the system GND plane
GSNS3IVoltage sense return tied directly to the GND sense point of the load. Short to GND if remote sense is not used.
MODE15I
PGND8–
PGOOD16O Powergood signal open drain output. PGOOD goes high when the output voltage is within the target range.
REFIN2IOutput voltage setting pin. See the VREF and REFIN, Output Voltage section.
SW12I/O High-side MOSFET gate driver return. R
TRIP6Icurrent sensing if connected to GND through an OCL setting resistor. For R
VSNS4IVoltage sense line tied directly to the load voltage sense point.
VREF1O2.0-V ±0.8% voltage reference output.
V59I5V power supply input for internal circuits and MOSFET gate drivers.
Thermal
pad
I/ODESCRIPTION
Connection for the DC compensation integrator for improved load-line performance. Connect a capacitor from
this pin to the VSNS pin (when operating in D-CAP2 mode), or to the positive terminal of the output capacitor
(when operating in D-CAP mode). Connect directly to the VSNS pin without capacitor to disable the integrator
function.
Connect a resistor to GND to configure switching frequency, control mode and current sense scheme. (See
Table 2)
Synchronous low-side MOSFET gate driver return. Also serve as the current sensing input (+). Connect to the
GND pin as close as possible to the device.
current sensing input (–) when using R
DS(on)
Current sense comparator input (-) for resistor current sensing. Or overcurrent threshold setting pin for R
μA at room temperature, TC=4700ppm/°C, is sourced to set the trip voltage.
––Thermal pad. Connect directly to system GND plane with multiple vias.
The TPS51219 is a high performance, single-synchronous step-down controller with differential voltage feedback.
The TPS51219 realizes accurate regulation at the specific load point over wide load range with the combination
of three functions.
•2-V Reference with 0.8% Tolerance. Internal voltage divider provides precise reference (See Table 1 in the
VREF and REFIN, Output Voltage section). A value of 0.1µF is recommended as the decoupling capacitance
between VREF and GSNS pins.
•Integrator. Feedback capacitance connected from the output (COMP pin) to the input (VSNS pin) of the error
amplifier comprises integrator, which increases gain at DC to low frequency region and improves load
regulation of the output voltage. 10nF is recommended as the capacitance between VSNS and COMP pins.
•Differential remote sensing. Differential feedback provides precise output voltage control at the point of
load. Connect VSNS and GSNS directly to output voltage sense point and ground return point at the load
device, respectively. Short GSNS to GND if remote sense is not used.
The TPS51219 supports two control architectures, D-CAP™ mode and D-CAP2™ mode. Both control modes do
not require complex external compensation networks and are suitable for designs with small external
components counts. The D-CAP™ mode provides fast transient response with appropriate amount of equivalent
series resistance (ESR) on the output capacitors. The D-CAP2™ mode is dedicated for a configuration with very
low ESR output capacitors such as multi-layer ceramic capacitors (MLCC). For the both modes, an adaptive
on-time control scheme is used to achieve pseudo-constant frequency. The TPS51219 adjusts the on-time (tON)
to be inversely proportional to the input voltage (VIN) and proportional to the SMPS output voltage (V
switching frequency remains nearly constant over the variation of input voltage at the steady-state condition.
Control modes and switching frequency are selected by the MODE pin described in Table 2.
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). The
OUT
VREF and REFIN, Output Voltage
The device provides a 2.0-V, ±0.8% accurate, voltage reference from VREF. This output has a 300-µA current
capability to drive the REFIN input voltage through a voltage divider circuit. A capacitor with a value of 0.1-µF or
larger should be attached close to the VREF terminal.
The SMPS output voltage is defined by REFIN voltage, within the range between 0.5 V and 2.0 V, programmed
by the resister-divider connected between VREF and GSNS. (See Figure 23 and External Components Selection
section.) A few nano-farads of capacitance from REFIN to GSNS is recommended for stable operation. A voltage
divider and a filter capacitor to this pin should be referenced to GSNS. Fixed output voltage can be set as shown
in Table 1.
Provide a voltage supply to VIN and V5 before asserting EN to high. TPS51219 provides integrated soft-start
functions to suppress in-rush current at start-up. The soft-start is achieved by controlling internal reference
voltage ramping up. Figure 24 shows the start-up waveforms. The switching regulator waits for 400μs after EN
assertion. The MODE pin voltage is read in this period. A typical V
THe TPS51219 has a powergood open-drain output that indicates the V
The target voltage window and transition delay times of the PGOOD comparator are ±8% (typ) and 1-ms delay
for assertion (low to high), and ±16% (typ) and 2-µs delay for de-assertion (high to low) during running. The
PGOOD start-up delay is 2.5 ms after EN is asserted to high. The time constant, which is composed of the
REFIN capacitor and a resistor divider, needs to be short enough to reach the target value before PGOOD
comparator enabled.
OUT
SLUSAG1B –MARCH 2011– REVISED OCTOBER 2011
ramp up duration is 700 μs.
voltage is within the target range.
OUT
Figure 24. Typical Start-up Waveforms
MODE Pin Configuration
The TPS51219 reads the MODE pin voltage when the EN signal is raised high and stores the status in a
register. A 16.7-μA current is sourced from the MODE pin during this time to read the voltage across the resistor
connected between the pin and GND. Table 2 shows resistor values, corresponding control mode, switching
frequency and current sense operation configurations.
Figure 25 shows a simplified model of D-CAP™ mode architecture in the TPS51219.
Figure 25. Simplified D-CAP™ Model
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The transconductance amplifier and the capacitance C1 configure an integrator. The VSNS voltage is compared
with REFIN voltage. Ripple voltage generated by ESR of the output capacitance is fed back through the C1 so
that C1 should be properly connected to the positive terminal of output capacitor, not at the remote point of load.
The PWM comparator creates a set signal to turn on the high-side MOSFET each cycle. The D-CAP™ mode
offers flexibility on output inductance and capacitance selections with ease-of-use without complex feedback loop
calculation and external components. However, it does require sufficient amount of ESR that represents inductor
current information for stable operation and good jitter performance. Organic semiconductor capacitor(s) or
specialty polymer capacitor(s) are recommended.
The requirement for loop stability is simple and is described in Equation 1. The 0-dB frequency, f0, is
recommended to be lower than 1/3 of the switching frequency to secure proper phase margin. The integrator
time constant should be long enough compared to f0, for example one decade low, as described in Equation 2.
where
•ESR is the effective series resistance of the output capacitor
•C
•fSWis the switching frequency(1)
where
•gMis transconductance of the error amplifier (typically 130 µS)(2)
Jitter is another attribute caused by signal-to-noise ratio of the feedback signal. One of the major factors that
determine jitter performance in D-CAP™ mode is the down-slope angle of the VSNS ripple voltage. Figure 26
shows, in the same noise condition, that jitter is improved by making the slope angle larger.
SLUSAG1B –MARCH 2011– REVISED OCTOBER 2011
Figure 26. Ripple Voltage Slope and Jitter Performance
For a good jitter performance, use the recommended down slope of approximately 20 mV per switching period as
shown in Figure 26 and Equation 3.
Figure 27 shows simplified model of D-CAP2™ architecture.
Figure 27. Simplified Modulator Using D-CAP2™ Mode
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When the TPS51219 operates in D-CAP2™ mode, connect the COMP and VSNS pins as shown in Figure 27.
The transconductance amplifier and the capacitance C1 configures the integrator. The D-CAP2™ mode in the
TPS51219 includes an internal feedback network enabling the use of very low ESR output capacitor(s) such as
multi-layer ceramic capacitors (MLCC). The role of the internal network is to sense the ripple component of the
inductor current information and then combine it with the voltage feedback signal.
Using RC1=RC2≡RCand CC1=CC2≡CC, 0-dB frequency of the D-CAP2™ mode is given by Equation 4. f0is
recommended to be lower than 1/3 of the switching frequency to secure proper phase margin. The integrator
time constant should be long enough compared to f0, for example one decade low, as described in Equation 5.
where
The typical G value is 0.25, and typical RCCCtime constant values for 500 kHz and 670 kHz operation are 32 μs
and 23 μs, respectively.
For example, when fSW= 500 kHz and LX=0.45 μH, C
capacitor, pay attention to its characteristics. For MLCC use X5R or better dielectric and take into account
derating of the capacitance by both DC bias and AC bias. When derating by DC bias and AC bias are 80% and
50%, respectively, the effective derating is 40% because 0.8 x 0.5 = 0.4. The capacitance of specialty polymer
capacitors may change depending on the operating frequency. Consult capacitor manufacturers for specific
characteristics.
•G is gain of the amplifier which amplifies the ripple current information generated by the compensation
circuit(4)
should be larger than 272 μF. At the selection of
OUT
(5)
()
-
=´´
´
INOUT
OUT
LOAD(LL)
XINSW
VV
V
1
I
2 LVf
æö
=´
ç÷
èø
TRIP
OCTRIPTRIP
I
VR
8
( )( )
æöæö
-
ç÷ç÷
=+=+´´
ç÷ç÷
´
èøèø
IND(ripple)
OCTRIPOCTRIPINOUTOUT
OCL
XSWIN
DS onDS on
I
VVVVV
1
I
R2R2LfV
TPS51219
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Light-Load Operation
In auto-skip mode, the TPS51219 SMPS control logic automatically reduces its switching frequency to improve
light-load efficiency. To achieve this intelligence, a zero cross detection comparator is used to prevent negative
inductor current by turning off the low-side MOSFET. Equation 6 shows the boundary load condition of this skip
mode and continuous conduction operation.
Current Sensing
In order to provide both cost effective solution and good accuracy, TPS51219 supports both of MOSFET R
sensing and external resistor sensing. For R
through the trip voltage setting resistor, R
. In this scheme, TRIP terminal sources 10µA of I
TRIP
the trip level is set to 1/8 of the voltage across the R
between the PGND pin and the SW pin so that the SW pin is connected to the drain terminal of the low-side
MOSFET. I
has a 4700ppm/°C temperature slope to compensate the temperature dependency of the R
TRIP
For resistor sensing scheme, an appropriate current sensing resistor should be connected between the source
terminal of the low-side MOSFET and PGND. The TRIP pin is connected to the MOSFET source terminal node.
The inductor current is monitored by the voltage between PGND pin and TRIP pin. In either scheme, PGND is
used as the positive current sensing node so that PGND should be connected to the proper current sensing
device, i.e. the sense resistor or the source terminal of the low-side MOSFET.
sensing scheme, TRIP pin should be connected to GND
DS(on)
. The inductor current is monitored by the voltage
TRIP
SLUSAG1B –MARCH 2011– REVISED OCTOBER 2011
(6)
DS(on)
current and
TRIP
DS(on)
.
Overcurrent Protection
TPS51219 has cycle-by-cycle overcurrent limiting protection. The inductor current is monitored during the
off-state and the controller maintains the off-state when the inductor current is larger than the overcurrent trip
level. The trip level and current sense operation are determined by the MODE pin setting and TRIP pin
connection (See Table 2 and Current Sensing section). For R
10 µA and the trip level is set to 1/8 of the voltage across this R
is determined by Equation 7.
For a resistor sensing scheme, the trip level, V
Because the comparison is made during the off-state, V
load current OCL level, I
Overcurrent limiting using R
, can be calculated by considering the inductor ripple current.
OCL
sensing is shown in Equation 8.
DS(on)
, is a fixed value of 25 mV.
OCTRIP
OCTRIP
where
•I
IND(ripple)
is inductor ripple current(8)
TRIP
sets the valley level of the inductor current. The
Overcurrent limiting using resistor sensing is shown in Equation 9.
where
•I
•R
IND(ripple)
is inductor ripple current
is the external current sense resistance(9)
EXT
In an overcurrent condition, the current to the load exceeds the current to the output capacitor, thus the output
voltage tends to fall down. Eventually, it crosses the undervoltage protection threshold and shuts down.
Overvoltage and Undervoltage Protection
The TPS51219 sets the overvoltage protection (OVP) when VSNS voltage reaches a level 20% (typ) higher than
the REFIN voltage. When an OV event is detected, the controller changes the output target voltage to 0 V. This
usually turns off DH and forces DL to be on. When the inductor current begins to flow through the low-side
MOSFET and reaches the negative OCL, DL is turned off and DH is turned on, for a minimum on-time.
After the minimum on-time expires, DH is turned off and DL is turned on again. This action minimizes the output
node undershoot due to LC resonance. When the VSNS reaches 0 V, the driver output is latched as DH off, DL
on.
The undervoltage protection (UVP) latch is set when the VSNS voltage remains lower than 68% (typ) of the
REFIN voltage for 1 ms or longer. In this fault condition, the controller latches DH low and DL low and discharges
the V
To release the OVP and UVP latches, toggle EN or adjust the V5 voltage down and up beyond the undervoltage
lockout threshold.
. UVP detection function is enabled after 1.2 ms of SMPS operation to ensure startup.
OUT
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V5 Undervoltage Lockout Protection
TPS51219 has a 5-V supply undervoltage lockout protection (UVLO) threshold. When the V5 voltage is lower
than UVLO threshold voltage, typically 3.9 V, V
is shut off. This is a non-latch protection.
OUT
Thermal Shutdown
TPS51219 includes an internal temperature monitor. If the temperature exceeds the threshold value, 140°C (typ),
V
is shut off. The state of V
OUT
is restarted with soft-start sequence when the device temperature is reduced by 10°C (typ).
is open at thermal shutdown. This is a non-latch protection and the operation
The external components selection is simple in D-CAP™ mode.
1. DETERMINE THE VALUE OF R1 AND R2
The output voltage is determined by the value of the voltage-divider resistor, R1 and R2 as shown in Figure 25.
R1 is connected between VREF and REFIN pins, and R2 is connected between the REFIN pin and GSNS.
Setting R1 as 10-kΩ is a good starting point. Determine R2 using Equation 10.
2. CHOOSE THE INDUCTOR
The inductance value should be determined to yield a ripple current of approximately ¼ to ½ of maximum output
current. Larger ripple current increases output ripple voltage and improves the signal-to-noise ratio and helps
stable operation.
SLUSAG1B –MARCH 2011– REVISED OCTOBER 2011
(10)
(11)
The inductor needs a low direct current resistance (DCR) to achieve good efficiency, as well as enough room
above peak inductor current before saturation. The peak inductor current can be estimated in Equation 12.
(12)
3. CHOOSE THE OCL SETTING RESISTANCE
R
for R
TRIP
Combining Equation 7 and Equation 8, R
R
for Resistor Setting
EXT
Combining Equation 7 and Equation 9, R
For more accurate current sensing with an external resistor, the following technique is recommended. Adding an
RC filter to cancel the parasitic inductance (ESL) of resistor, this filter value is calculated using Equation 15.
DS(on)
Sensing
can be obtained using Equation 13.
TRIP
can be obtained using Equation 14.
EXT
(13)
(14)
The time-constant of CXand RXshould match the one of ESL and R
100 Ω is recommended for noise suppression.
Figure 28. Resistor Sensing with CompensationFigure 29. Adjustment of Overcurrent Limitation in
Resistor Sensing
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A voltage divider can be configured to adjust for overcurrent limitation, as described in Figure 29. For RX, R
and CXcan be calculated as shown in Equation 16, and the overcurrent limitation value can be calculated as
shown in Equation 17.
Therefore, R
can be obtained using Equation 18.
EXT
4. CHOOSE THE OUTPUT CAPACITORS
D-CAP™ Mode
Organic semiconductor capacitor(s) or specialty polymer capacitor(s) are recommended. Determine the ESR
value to meet small signal stability and recommended ripple voltage. A quick reference is shown in Equation 19
and Equation 20.
where
•gMis 130 µS (typ)
•C1 is the capacitance connected between the VSNS and COMP pins(20)
Certain issues must be considered before designing a layout using the TPS51219.
Figure 30. DC/DC Converter Ground System
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•VINcapacitor(s), V
capacitor(s) and MOSFETs are the power components and should be placed on one
OUT
side of the PCB (solder side). Other small signal components should be placed on another side (component
side). At least one inner plane should be inserted, connected to ground, in order to shield and isolate the
small signal traces from noisy power lines.
•All sensitive analog traces and components such as VSNS, COMP, MODE, REFIN, VREF and TRIP should
be placed away from high-voltage switching nodes such as SW, DH, DL or BST to avoid coupling. Use
internal layer(s) as ground plane(s) and shield feedback trace from power traces and components.
•The DC/DC converter has several high-current loops. The area of these loops should be minimized in order to
suppress generating switching noise.
– Loop #1. The most important loop to minimize the area of is the path from the VINcapacitor(s) through the
high and low-side MOSFETs, and back to the capacitor(s) through ground. Connect the negative node of
the VINcapacitor(s) and the source of the low-side MOSFET at ground as close as possible. (Refer to loop
#1 of Figure 30)
– Loop #2. The second important loop is the path from the low-side MOSFET through inductor and V
capacitor(s), and back to source of the low-side MOSFET through ground. Connect source of the low-side
MOSFET and negative node of V
capacitor(s) at ground as close as possible. (Refer to loop #2 of
OUT
Figure 30)
– Loop #3. The third important loop is of gate driving system for the low-side MOSFET. To turn on the
low-side MOSFET, high current flows from V5 capacitor through gate driver and the low-side MOSFET,
and back to negative node of the capacitor through ground. To turn off the low-side MOSFET, high current
flows from gate of the low-side MOSFET through the gate driver and PGND, and back to source of the
low-side MOSFET through ground. Connect negative node of V5 capacitor, source of the low-side
MOSFET and PGND at ground as close as possible. (Refer to loop #3 of Figure 30)
•Connect the PGND and GND pins directly at the device.
•Connect VSNS directly to the output voltage sense point at the load device. Connect GSNS to ground return
points at the load device. Insert a 10-Ω, 1-nF, R-C filter between the sense point and the VSNS pin where the
COMP capacitance is connected as shown in Case 1 (Figure 31). When the COMP pin capacitance is
connected to output bulk capacitance, connect the R-C filter in series to both the VSNS pin and the COMP
capacitance as shown in Case 2 (Figure 32).
SLUSAG1B –MARCH 2011– REVISED OCTOBER 2011
Figure 31. Case 1: COMP Pin Capacitance Connected to VSNS
Figure 32. Case 2: COMP Pin Capacitance Connected to Output Bulk Capacitance
•Connect the overcurrent setting resistors from TRIP pin to ground and make the connections as close as
possible to the device. The trace from TRIP pin to resistor and from resistor to ground should avoid coupling
to a high-voltage switching node.
•Connect the frequency and mode setting resistor from MODE pin to ground, and make the connections as
close as possible to the device. The trace from the MODE pin to the resistor and from the resistor to ground
should avoid coupling to a high-voltage switching node.
Connections from gate drivers to the respective gate of the high-side or the low-side MOSFET should be as
short as possible to reduce stray inductance. Use 0.65 mm (25 mils) or wider trace and via(s) of at least 0.5
mm (20 mils) diameter along this trace.
•The PCB trace defined as SW node, which connects to the source of the switching MOSFET, the drain of the
rectifying MOSFET and the high-voltage side of the inductor, should be as short and wide as possible.
•In order to effectively remove heat from the package, prepare the thermal land and solder to the package
thermal pad. Wide trace of the component-side copper, connected to this thermal land, helps to dissipate
heat. Numerous vias with a 0.3-mm diameter connected from the thermal land to the internal/solder-side
ground plane(s) should be used to help dissipation.
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Package Type Package
(1)
Drawing
Pins Package
Qty
Eco Plan
(2)
& no Sb/Br)
& no Sb/Br)
Lead/Ball Finish
(6)
CU NIPDAULevel-2-260C-1 YEAR-40 to 8551219
CU NIPDAULevel-2-260C-1 YEAR-40 to 8551219
MSL Peak Temp
(3)
Op Temp (°C)Device Marking
(4/5)
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
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