Texas Instruments TPS51219 Schematic [ru]

1

2

3

4

12

11

10

9

SW

DH

DL

V5

VREF

REFIN

GSNS

VSNS

TPS51219RTE

5 6 7 8

PGND

GND

TRIP

COMP

16 15 14 13

BST

EN

MODE

PGOOD

PwrPd

VSNS

GSNS

PGOOD

V5IN

EN

V

OUT

V

IN

UDG-11006

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High Performance, Single-Synchronous Step-Down Controller

with Differential Voltage Feedback

1

FEATURES

23

• Differential Voltage Feedback

• DC Compensation for Accurate Regulation

• Wide Input Voltage Range: 3 V to 28 V

• Output Voltage Range: 0.5 V to 2.0 V with

Fixed Options of 1.05 V and 1.00 V

• Wide Output Load Range: 0 A to 20 A+

• Adaptive On-Time Modulation with Selectable

Control Architecture and Frequency
– D-CAP™ Mode at 300 kHz/400 kHz for Fast

Transient Response

– D-CAP2™ Mode at 500 kHz/670 kHz for

Ceramic Output Capacitor

• 4700 ppm/°C, Low-Side R

• R

Accurate Current Sense Option

SENSE

• Internal, 1-ms Voltage Servo Softstart

• Built-In Output Discharge

• Power Good Output

• Integrated Boost Switch

• Built-In OVP/UVP/OCP

• Thermal Shutdown (Non-latched)

• 3 mm × 3 mm, 16-Pin, QFN (RTE) Package

APPLICATIONS

• Notebook Computers

• I/O Supplies

Current Sensing

DS(on)

TPS51219

SLUSAG1B –MARCH 2011– REVISED OCTOBER 2011

DESCRIPTION

The TPS51219 is a small-sized single buck controller
with adaptive on-time control. It provides a choice of
control modes (D-CAP™ or D-CAP2™) to meet a
wide range of system requirements. It is designed for
tight DC regulation requirements such as the VCCIO
application for Intel®notebooks. The performance
and flexibility of the TPS51219 makes it suitable for
low output voltage, high current, PC system power
rails and similar point-of-load (POL) power supplies.
Differential voltage feedback and the voltage
compensation function combine to provide high
precision power to load devices.

A small package, fixed voltage options and minimal
external component count saves cost and space,
while a dedicated EN pin and pre-set frequency
selections minimize design effort. The skip-mode at
light load condition, strong gate drivers, and low-side
FET R
operation over a broad load range. The external
resistor current sense option enables accurate
current sensing. The conversion input voltage (the
high-side FET drain voltage) ranges from 3 V to 28 V
and output voltage ranges from 0.5 V to 2.0 V. The
device requires an external 5-V supply.

The TPS51219 is available in a 16-pin, QFN package
and is specified for ambient temperature from -40°C
to 85°C.

current sensing provides high efficiency

DS(on)

1

2D-CAP, D-CAP2 are trademarks of Texas Instruments.
3Intel is a registered trademark of Intel.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright © 2011, Texas Instruments Incorporated

TPS51219

SLUSAG1B –MARCH 2011– REVISED OCTOBER 2011

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

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ORDERING INFORMATION

T

A

PACKAGE PINS

–40°C to 85°C Plastic Quad Flat Pack (QFN) 16

ORDERABLE DEVICE OUTPUT MINIMUM

NUMBER SUPPLY QUANTITY

TPS51219RTER Tape and reel 3000
TPS51219RTET Mini-reel 250

(1)

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

ABSOLUTE MAXIMUM RATINGS

(1)

over operating free-air temperature range (unless otherwise noted)

VALUE UNIT

MIN MAX

BST –0.3 36

(3)

BST
SW –5 30

Input voltage range

(2)

EN, MODE, TRIP, V5 –0.3 6.0 V
COMP, REFIN, VSNS –0.3 3.6
GSNS –0.35 0.35
PGND –0.3 0.3
DH –5 36

(3)

DH

Output voltage range

(2)

DL –0.3 6 V
PGOOD –0.3 6

VREF –0.3 3.6
Junction temperature range, T
Storage temperature range, T

J

STG

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the network ground terminal unless otherwise noted.
(3) Voltage values are with respect to the SW terminal.

–0.3 6

–0.3 6

125 °C

–55 150 °C

2 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated

TPS51219

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RECOMMENDED OPERATING CONDITIONS

Supply voltage V5 4.5 5.5 V

BST –0.1 33.5

(1)

BST
SW -3 28

(2)

Input voltage range V

Output voltage range V

T

A

(1) Voltage values are with respect to the SW terminal.
(2) This voltage should be applied for less than 30% of the repetitive period.

SW
EN, TRIP, MODE –0.1 5.5
REFIN, VSNS, COMP –0.1 3.5
GSNS –0.3 0.3
PGND –0.1 0.1
DH –3 33.5

(1)

DH

(2)

DH
DL –0.1 5.5
PGOOD –0.1 5.5
VREF –0.1 3.5
Operating free-air temperature –40 85 °C

SLUSAG1B –MARCH 2011– REVISED OCTOBER 2011

MIN TYP MAX UNIT

–0.1 5.5

–4.5 28

–0.1 5.5
–4.5 33.5

THERMAL INFORMATION

TPS51219

THERMAL METRIC

θ

θ

θ

ψ

ψ

θ

JA
JCtop
JB

JT
JB

JCbot

Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific

JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(1)

RTE UNITS

16 PINS

(2)

(3)

(4)

(5)

(6)

(7)

48.5

49.5

22.1

0.7

22.1

7.1

°C/W

Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback 3

TPS51219

SLUSAG1B –MARCH 2011– REVISED OCTOBER 2011

ELECTRICAL CHARACTERISTICS

over operating free-air temperature range, VV5= 5 V, V

PARAMETER TEST CONDITION MIN TYP MAX UNIT

SUPPLY CURRENT

I

V5

I

V5SDN

VREF OUTPUT

V

VREF

V

VREF(tol)

I

VREF(ocl)

OUTPUT VOLTAGE

V

VSNS

V

VSNS(tol)

V

REFIN1

V

REFIN1P05

V

OFF_LPCMP

V

COMPCLP

g

M

I

VSNS

I

REFIN

I

VSNS(dis)

SWITCH MODE POWER SUPPLY (SMPS) FREQUENCY

f

SW

t

ON(min)

t

OFF(min)

MOSFET DRIVERS

R

DH

R

DL

t

DEAD

INTERNAL BOOT STRAP SWITCH

V

FBST

I

BSTLK

(1) Ensured by design. Not production tested.

V5 supply current TA= 25°C, No load, VEN= 5 V 560 μA
V5 shutdown current TA= 25°C, No load, VEN= 0 V 0.5 2.0 μA

Output voltage I

Output voltage tolerance

Current limit V

VSNS sense voltage V

VSNS regulation voltage tolerance V

= 0 μA wrt GSNS 2.000 V

VREF

0 μA ≤ I

VREF

0 μA ≤ I

VREF

VREF-GSNS

V

= 0 V 1.000 V

REFIN

= 3.3 V 1.050 V

REFIN

0.5 V ≤ V

REFIN

V

= 0 V, 0°C ≤ TA≤ 85°C –9 9

REFIN

V

= 0 V, -40°C ≤ TA≤ 85°C -14 14

REFIN

= 3.3 V, 0°C ≤ TA≤ 85°C –9 9 mV

REFIN

V

= 3.3 V, -40°C ≤ TA≤ 85°C -14 14

REFIN

V

= 0.5 V and V

REFIN

REFIN voltage for 1.00-V output 0.3 V
REFIN voltage for 1.05-V output 2.2 V
Loop comparator offset voltage V

COMP clamp voltage

Error amplifier transconductance V
VSNS input current V
REFIN input current V

= 1 V, VSNS shorted to COMP -5 5 mV

REFIN

V

= 0 V, V

REFIN

V

= 0 V, V

REFIN

= 0 V 130 μS

REFIN

= 1.05 V -1 1 μA

VSNS

= 0 V –1 1 μA

REFIN

VSNS discharge current VEN= 0 V, V

VIN= 12 V, V

Switching frequency kHz

VIN= 12 V, V
VIN= 12 V, V

VIN= 12 V, V
Minimum on time DH rising to falling
Minimum off time DH falling to rising 320

DH resistance

DL resistance

Dead time ns

Forward voltage V

Source, IDH= –50 mA 1.6 3.0

Sink, IDH= 50 mA 0.6 1.5

Source, IDL= –50 mA 0.9 2.0

Sink, IDL= 50 mA 0.5 1.2

DH-off to DL-on 10

DL-off to DH-on 20

, TA= 25°C, IF= 10 mA 0.1 0.2 V

V5-BST

BST leakage current TA= 25°C, V

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= 0 V, VEN= 5 V (unless otherwise noted)

MODE

< 30 μA, TA= 0°C to 85°C -0.8% 0.8%
< 300 μA, TA= –40°C to 85°C -1.2% 1.2%

= 1.7 V 0.4 1.0 mA

≤ 2 V V

= 2.0 V -5 5

REFIN

= 0.95 V 0.885 V

VSNS

= 1.05 V 1.115 V

VSNS

= 0.5 V 5 12 mA

VSNS

VSNS
VSNS
VSNS
VSNS

= 1.8 V, V
= 1.8 V, V
= 1.8 V, V
= 1.8 V, V

(1)

= 2.5 V 400

MODE

= 1.67 V 300

MODE

= 0.2 V 670

MODE

= 0.033 V 500

MODE

REFIN

60

V

ns

Ω

= 33 V, VSW= 28 V 0.01 1.5 μA

BST

4 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated

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ELECTRICAL CHARACTERISTICS (continued)

over operating free-air temperature range, VV5= 5 V, V

PARAMETER TEST CONDITION MIN TYP MAX UNIT

LOGIC THRESHOLD

I

MODE

V

THMODE

V

LL

V

LH

V

LHYST

I

LLK

SOFT START

t

SS

POWERGOOD COMPARATOR

V

THPG

I

PG

t

PGDLY

t

PGCMPSS

I

PG(leak)

CURRENT DETECTION

I

TRIP

(2)

TC

ITRIP

V

TRIP

V

OCL

V

OCLN

V

RTRIP

V

ZC

(2) Ensured by design. Not production tested.

MODE source current 15.6 16.7 17.8 μA

MODE 0-1 113 143 173

MODE 1-2 253 283 313

MODE 2-3 433 458 483
MODE threshold voltage MODE 3-4 644 667 690 mV

MODE 4-5 914 949 984

MODE 5-6 1329 1369 1409

MODE 6-7 1950 2000 2050
EN low-level voltage 0.5
EN high-level voltage 1.8 V
EN hysteresis voltage 0.25
EN input leakage current –1 0 1 μA

Soft-start time Internal soft-start time 1.1 ms

PGOOD in from higher 106% 108% 110%

PGOOD threshold

PGOOD in from lower 90% 92% 94%

PGOOD out to higher 114% 116% 118%

PGOOD out to lower 82% 84% 86%
PGOOD sink current V

PGOOD delay time

PGOOD

Delay for PGOOD in 0.8 1.0 1.2 ms

Delay for PGOOD out, with 100 mV over drive 0.25 µs
PGOOD start-up delay PGOOD comparator wake-up delay 2.5 ms
PGOOD leakage current -1 0 1 µA

TRIP source current TA= 25°C, V
TRIP source current temperature

coefficient
V

(2)

voltage range R

TRIP

Current limit threshold V

Negative current limit threshold V

R

V

V

V

V

DS(on)

DS(on)
TRIP
TRIP
TRIP
TRIP
TRIP
TRIP

Resistor sense trip voltage Resistor sensing 25 mV
Zero cross detection offset 0 mV

MODE

= 0.5 V 3 6 mA

TRIP

sensing 4700 ppm/°C

sensing 0.2 3 V
= 3.0 V, R
= 1.6 V, R
= 0.2 V, R
= 3.0 V, R
= 1.6 V, R
= 0.2 V, R

DS(on)
DS(on)
DS(on)
DS(on)
DS(on)
DS(on)

TPS51219

SLUSAG1B –MARCH 2011– REVISED OCTOBER 2011

= 0 V, VEN= 5 V (unless otherwise noted)

= 0.4 V, R

sensing 360 375 390
sensing 190 200 210 mV
sensing 20 25 30
sensing –390 –375 –360
sensing –212 –200 –188 mV
sensing –30 –25 –20

sensing 9 10 11 μA

DS(on)

Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback 5

TPS51219

SLUSAG1B –MARCH 2011– REVISED OCTOBER 2011

ELECTRICAL CHARACTERISTICS (continued)

over operating free-air temperature range, VV5= 5 V, V

PARAMETER TEST CONDITION MIN TYP MAX UNIT

PROTECTIONS

V

UVLO

V

OVP

t

OVPDLY

V

UVP

t

UVPDLY

t

UVPENDLY

V5 UVLO threshold voltage V

OVP threshold voltage OVP detect voltage 118% 120% 122%
OVP propagation delay With 100 mV over drive 370 ns
UVP threshold voltage UVP detect voltage 66% 68% 70%
UVP delay 1 ms
UVP enable delay 1.4 ms

THERMAL SHUTDOWN

T

SDN

Thermal shutdown threshold °C

(3) Ensured by design. Not production tested.

Wake-up 4.2 4.4 4.5
Shutdown 3.7 3.9 4.1

Shutdown temperature
Hysteresis

MODE

(3)

= 0 V, VEN= 5 V (unless otherwise noted)

(3)

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140

10

6 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated

4

2

3

8

12

11

10

9

VREF

REFIN

GSNS

VSNS

PGOOD

DH

DL

V5

16 15 14 13

1

5 6 7

MODE

EN

BST

SW

PGND

GND

COMP

TRIP

TPS51219

PowerPAD

TM

www.ti.com

TPS51219

SLUSAG1B –MARCH 2011– REVISED OCTOBER 2011

DEVICE INFORMATION

RTE PACKAGE (TOP VIEW)

PIN FUNCTIONS

PIN

NAME NO.

BST 13 I High-side MOSFET gate driver bootstrap voltage input. Connect a capacitor from the BST pin to the SW pin.

COMP 5 I

DH 11 O High-side MOSFET gate driver output.
DL 10 O Low-side MOSFET gate driver output.
EN 14 I Enable pin. 3.3-V I/O level, 100 ns de-bounce. Short to GND to disable the device.
GND 7 – Device analog ground; Connect to a quiet point on the system GND plane
GSNS 3 I Voltage sense return tied directly to the GND sense point of the load. Short to GND if remote sense is not used.

MODE 15 I

PGND 8 –
PGOOD 16 O Powergood signal open drain output. PGOOD goes high when the output voltage is within the target range.

REFIN 2 I Output voltage setting pin. See the VREF and REFIN, Output Voltage section.
SW 12 I/O High-side MOSFET gate driver return. R

TRIP 6 I current sensing if connected to GND through an OCL setting resistor. For R

VSNS 4 I Voltage sense line tied directly to the load voltage sense point.
VREF 1 O 2.0-V ±0.8% voltage reference output.
V5 9 I 5V power supply input for internal circuits and MOSFET gate drivers.
Thermal

pad

I/O DESCRIPTION

Connection for the DC compensation integrator for improved load-line performance. Connect a capacitor from
this pin to the VSNS pin (when operating in D-CAP2 mode), or to the positive terminal of the output capacitor
(when operating in D-CAP mode). Connect directly to the VSNS pin without capacitor to disable the integrator
function.

Connect a resistor to GND to configure switching frequency, control mode and current sense scheme. (See

Table 2)

Synchronous low-side MOSFET gate driver return. Also serve as the current sensing input (+). Connect to the
GND pin as close as possible to the device.

current sensing input (–) when using R

DS(on)

Current sense comparator input (-) for resistor current sensing. Or overcurrent threshold setting pin for R

μA at room temperature, TC=4700ppm/°C, is sourced to set the trip voltage.

– – Thermal pad. Connect directly to system GND plane with multiple vias.

current sensing.

DS(on)

current sensing operation, 10

DS(on)

DS(on)

Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback 7

8

12

PGND

SW

OC

ZC

XCON

13

BST

9 V5

PWM

4

REFIN

TRIP

Delay

16 PGOOD

Control Logic

10 mA

+

+

V

REFIN

+ 20%

+

+

2

VSNS

6

11 DH

10 DL

t

ON

One­Shot

UV

OV

V

REFIN

– 32%

14EN

Soft-Start

+

NOC

+

1VREF Reference

7 R

R

Control Mode

On-Time

Current Sense

Selection

16.7 mA

15 MODE

V

REFIN

+8/16%

V

REFIN

– 8/16%

+

+

Discharge

V5OK

+

4.3 V/3.9 V

UVPOVP

COMP 5

+

VBG

5-V UVLO

TPS51219

UDG-11007

EN

3GSNS

7GND

EN

Set_1p05v

Set_adj

Discharge

R

8 R

+

V

REFIN

2.2 V

0.3 V

Set_adj

Set_1p05v

EN

+

+

25 mV

Set_resistor _sensing

Set_resistor _sensing

TPS51219

SLUSAG1B –MARCH 2011– REVISED OCTOBER 2011

FUNCTIONAL BLOCK DIAGRAM

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8 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated

0

200

400

600

800

1000

−50 −25 0 25 50 75 100 125
Junction Temperature (°C)

V5 Supply Current (µA)

VV5 = 5 V
VEN = 5 V
No Load

0

2

4

6

8

10

−50 −25 0 25 50 75 100 125
Junction Temperature (°C)

V5 Shutdown Current (µA)

VV5 = 5 V
VEN = 0 V
No Load

0

2

4

6

8

10

12

14

16

−50 −25 0 25 50 75 100 125
Junction Temperature (°C)

Trip Source Current (µA)

VV5 = 5 V
V

TRIP

= 0.5 V

50

60

70

80

90

100

110

120

130

140

150

−50 −25 0 25 50 75 100 125
Junction Temperature (°C)

UVP/OVP Threshold (%)

UVP
OVP

VV5 = 5 V
V

REFIN

= 0 V

1.980

1.985

1.990

1.995

2.000

2.005

2.010

2.015

2.020

0 50 100 150 200 250 300 350 400

VREF Current (µA)

VREF Voltage (V)

VV5 = 5 V
TA = 27°C

200

300

400

500

600

700

800

900

6 8 10 12 14 16 18 20 22

Input Voltage (V)

Switching Frequency (kHz)

R

MODE

= 1 kΩ

R

MODE

= 12 kΩ

R

MODE

= 100 kΩ

R

MODE

= 200 kΩ

I

OUT

= 10 A

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TPS51219

SLUSAG1B –MARCH 2011– REVISED OCTOBER 2011

TYPICAL CHARACTERISTICS

Figure 1. V5 Supply Current vs Junction Temperature Figure 2. V5 Shutdown Current vs Junction Temperature

Figure 3. Current Sense Current vs Junction Temperature Figure 4. OVP/UVP Threshold vs Junction Temperature

Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback 9

Figure 5. VREF Load Regulation Figure 6. Switching Frequency vs Input Voltage

0

100

200

300

400

500

600

700

800

0 2 4 6 8 10 12 14 16 18 20

Output Current (A)

Switching Frequency (kHz)

R

MODE

= 100 kΩ
VIN = 12 V
V

OUT

= 1.05 V

L = 0.56 µH

0

100

200

300

400

500

600

700

800

0 2 4 6 8 10 12 14 16 18 20

Output Current (A)

Switching Frequency (kHz)

R

MODE

= 200 kΩ
VIN = 12 V
V

OUT

= 1.05 V

L = 0.56 µH

0

100

200

300

400

500

600

700

800

0 2 4 6 8 10 12 14 16 18 20

Output Current (A)

Switching Frequency (kHz)

R

MODE

= 1 kΩ
VIN = 12 V
V

OUT

= 1.05 V

L = 0.45 µH

0

100

200

300

400

500

600

700

800

0 2 4 6 8 10 12 14 16 18 20

Output Current (A)

Switching Frequency (kHz)

R

MODE

= 12 kΩ
VIN = 12 V
V

OUT

= 1.05 V

L = 0.36 µH

1.030

1.035

1.040

1.045

1.050

1.055

1.060

1.065

1.070

0 2 4 6 8 10 12 14 16 18 20

1.05−V Output Current (A)

VSNS−GSNS − 1.05−V Output Voltage (V)

R

MODE

= 1 kΩ
VIN = 12 V

G001

1.030

1.035

1.040

1.045

1.050

1.055

1.060

1.065

1.070

6 8 10 12 14 16 18 20 22

Input Voltage (V)

VSNS−GSNS − 1.05−V Output Voltage (V)

I

OUT

= 0 A

I

OUT

= 10 A

R

MODE

= 1 kΩ

G001

TPS51219

SLUSAG1B –MARCH 2011– REVISED OCTOBER 2011

Figure 11 and Figure 12 refer to the application schematic in Figure 33.

Figure 7. Switching Frequency vs Load Current Figure 8. Switching Frequency vs Load Current

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TYPICAL CHARACTERISTICS

Figure 9. Switching Frequency vs Load Current Figure 10. Switching Frequency vs Load Current

10 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated

Figure 11. 1.05-V Output Load Regulation Figure 12. 1.05-V Output Line Regulation

0.980

0.985

0.990

0.995

1.000

1.005

1.010

1.015

1.020

0 2 4 6 8 10

1.00−V Output Current (A)

VSNS−GSNS − 1.00−V Output Voltage (V)

R

MODE

= 1 kΩ
VIN = 12 V

G001

0

10

20

30

40

50

60

70

80

90

100

0.001 0.01 0.1 1 10 100

1.05−V Output Current (A)

Efficiency (%)

VIN = 8 V
VIN = 12 V
VIN = 20 V

R

MODE

= 1 kΩ

0.980

0.985

0.990

0.995

1.000

1.005

1.010

1.015

1.020

6 8 10 12 14 16 18 20 22

Input Voltage (V)

VSNS−GSNS − 1.00−V Output Voltage (V)

I

OUT

= 0 A

I

OUT

= 10 A

R

MODE

= 1 kΩ

G001

0

10

20

30

40

50

60

70

80

90

100

0.001 0.01 0.1 1 10 100

1.00−V Output Current (A)

Efficiency (%)

VIN = 8 V
VIN = 12 V
VIN = 20 V

R

MODE

= 1 kΩ

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TPS51219

SLUSAG1B –MARCH 2011– REVISED OCTOBER 2011

TYPICAL CHARACTERISTICS

Figure 11, Figure 12, and Figure 13 refer to the application schematic in Figure 33.

Figure 14, Figure 15 and Figure 16, refer to the application schematic in Figure 33 except the parameters

of L1 (0.56 µH), C7 (2 × 330 µF) and Q3 (not used).

Figure 13. 1.05-V Output Efficiency Figure 14. 1.00-V Output Load Regulation

Figure 15. 1.00-V Output Line Regulation Figure 16. 1.00-V Output Efficiency

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VIN=20 V

VSNS-GSNS (20 mV/div)
offset: 1.05 V

I

OUT

(8 A/div)

offset: 6 A

C

OUT

= 5 x 330 µF(Bulk) + 12 x 22 µF(MLCC)

VIN=20 V

VSNS-GSNS (20 mV/div)
offset: 1.00 V

I

OUT

(8 A/div)

C

OUT

= 2 x 330 µF(Bulk) + 12 x 22 µF(MLCC)

EN (5 V/div)

VSNS-GSNS

(500mV/div)

PGOOD (5V/div)

Time (400 µs/div)

I

OUT

= 15A

Time (400 µs/div)

EN (5 V/div)

VSNS-GSNS

(500mV/div)

PGOOD (5V/div)

I

OUT

= 0 A

0.5-V Pre-biased

TPS51219

SLUSAG1B –MARCH 2011– REVISED OCTOBER 2011

Figure 17. 1.05-V Load Transient Response Figure 18. 1.00-V Load Transient Response

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TYPICAL CHARACTERISTICS

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Figure 19. 1.05-V Startup Waveforms Figure 20. 1.05-V Startup Waveforms (0.5-V Pre-Biased)