1
2
3
4
10
9
8
7
VBST
DRVH
SW
V5IN
PGOOD
TRIP
EN
VFB
TPS51218
5 6DRVLRF
GND
V
IN
V
OUT
V
OUT
_GND
EN
V5IN
UDG-09064
TPS51218
www.ti.com
SLUS935B –MAY 2009– REVISED FEBRUARY 2012
HIGH PERFORMANCE, SINGLE SYNCHRONOUS STEP-DOWN
CONTROLLER FOR NOTEBOOK POWER SUPPLY
Check for Samples: TPS51218
1
FEATURES
2
• Wide Input Voltage Range: 3 V to 28 V
• Output Voltage Range: 0.7 V to 2.6 V • I/O Supplies
• Wide Output Load Range: 0 to 20A+ • System Power Supplies
• Built-in 0.5% 0.7 V Reference
• D-CAP™ Mode with 100-ns Load Step
Response
• Adaptive On Time Control Architecture With 4
Selectable Frequency Setting
• 4700 ppm/°C R
• Internal 1-ms Voltage Servo Softstart
• Pre-Charged Start-up Capability
• Built in Output Discharge
• Power Good Output
• Integrated Boost Switch
• Built-in OVP/UVP/OCP
• Thermal Shutdown (Non-latch)
• SON-10 (DSC) Package
Current Sensing
DS(on)
APPLICATIONS
• Notebook Computers
DESCRIPTION
The TPS51218 is a small-sized single buck controller
with adaptive on-time D-CAP™ mode. The device is
suitable for low output voltage, high current, PC
system power rail and similar point-of-load (POL)
power supply in digital consumer products. A small
package with minimal pin-count saves space on the
PCB, while a dedicated EN pin and pre-set frequency
selections minimize design effort required for new
designs. The skip-mode at light load condition, strong
gate drivers and low-side FET R
supports low-loss and high efficiency, over a broad
load range. The conversion input voltage which is the
high-side FET drain voltage ranges from 3 V to 28 V
and the output voltage ranges from 0.7 V to 2.6 V.
The device requires an external 5-V supply. The
TPS51218 is available in a 10-pin SON package
specified from –40°C to 85°C.
current sensing
DS(on)
TYPICAL APPLICATION CIRCUIT
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2D-CAP is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2012, Texas Instruments Incorporated
TPS51218
SLUS935B –MAY 2009– REVISED FEBRUARY 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
T
A
PACKAGE PINS
–40°C to 85°C Plastic SON PowerPAD
ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature range (unless otherwise noted)
VBST –0.3 to 37
(3)
Input voltage range
Output voltage range
T
J
T
STG
(2)
(2)
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the network ground terminal unless otherwise noted.
(3) Voltage values are with respect to the SW terminal.
VBST
SW –5 to 30
V5IN, EN, TRIP, VFB, RF –0.3 to 7
DRVH –5 to 37
(3)
DRVH
(3)
DRVH
, pulse width < 20 ns –2.5 to 7
DRVL –0.5 to 7
DRVL, pulse width < 20 ns –2.5 to 7
PGOOD –0.3 to 7
Junction temperature range 150 °C
Storage temperature range –55 to 150 °C
ORDERING DEVICE OUTPUT MINIMUM
NUMBER SUPPLY QUANTITY
TPS51218DSCR 10 Tape and reel 3000
TPS51218DSCT 10 Mini reel 250
VALUE UNIT
–0.3 to 7
–0.3 to 7
V
V
DISSIPATION RATINGS
2-oz. trace and copper pad with solder.
PACKAGE TA< 25°C DERATING FACTOR TA= 85°C
10-pin DSC
(1)
(1) Enhanced thermal conductance by thermal vias is used beneath thermal pad as shown in Land Pattern information.
2 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated
POWER RATING ABOVE TA= 25°C POWER RATING
1.54 W 15 mW/°C 0.62 W
Product Folder Link(s): TPS51218
TPS51218
www.ti.com
SLUS935B –MAY 2009– REVISED FEBRUARY 2012
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN TYP MAX UNIT
Supply voltage V5IN 4.5 6.5 V
VBST –0.1 34.5
SW –1 28
VBST
(1)
(2)
–4 28 V
–0.1 6.5
EN, TRIP, VFB, RF –0.1 6.5
DRVH –1 34.5
(1)
DRVH
(2)
–4 34.5
–0.1 6.5 V
DRVL –0.3 6.5
PGOOD –0.1 6.5
Operating free-air temperature –40 85 °C
Input voltage range SW
Output voltage range DRVH
T
A
(1) This voltage should be applied for less than 30% of the repetitive period.
(2) Voltage values are with respect to the SW terminal.
Copyright © 2009–2012, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): TPS51218
TPS51218
SLUS935B –MAY 2009– REVISED FEBRUARY 2012
ELECTRICAL CHARACTERISTICS
over recommended free-air temperature range, V5IN=5V. (Unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
I
V5IN
I
V5INSDN
V5IN supply current 320 500 μA
V5IN shutdown current V5IN current, TA= 25°C, No Load, VEN= 0 V 1 μA
INTERNAL REFERENCE VOLTAGE
V
I
VFB
VFB
VFB regulation voltage
VFB input current V
OUTPUT DISCHARGE
I
Dischg
Output discharge current from
SW pin
OUTPUT DRIVERS
R
R
t
D
DRVH
DRVL
DRVH resistance
DRVL resistance
Dead time ns
BOOT STRAP SWITCH
V
FBST
I
VBSTLK
Forward voltage V
VBST leakage current V
DUTY AND FREQUENCY CONTROL
t
OFF(min)
t
ON(min)
Minimum off-time TA= 25°C 150 260 400
Minimum on-time 79
SOFTSTART
t
ss
Internal SS time From VEN= high to V
POWERGOOD
V
THPG
I
PGMAX
t
PGDEL
PG threshold PG in from higher 107.5% 110% 112.5%
PG sink current V
PG delay Delay for PG in 0.8 1 1.2 ms
LOGIC THRESHOLD AND SETTING CONDITIONS
V
EN
I
EN
f
SW
V
RF
EN voltage threshold V
EN input current VEN= 5V 1.0 μA
Switching frequency kHz
CCM setting voltage V
(1) Ensured by design. Not production tested.
(2) Not production tested. Test condition is VIN= 8 V, V
V5IN current, TA= 25°C, No Load,
VEN= 5 V, V
VFB voltage, CCM condition
VFB
= 0.735 V
(1)
TA= 25°C, skip mode 0.7005 0.7040 0.7075
TA= 0°C to 85°C, skip mode 0.6984 0.7040 0.7096 V
TA= –40°C to 85°C, skip mode 0.6970 0.7040 0.7110
= 0.735 V, TA= 25°C, skip mode 0.01 0.2 μA
VFB
VEN= 0 V, VSW= 0.5 V 5 13 mA
Source, I
Sink, I
Source, I
Sink, I
= –50 mA 1.5 3
DRVH
= 50 mA 0.7 1.8
DRVH
= –50 mA 1.0 2.2
DRVL
= 50 mA 0.5 1.2
DRVL
DRVH-off to DRVL-on 7 17 30
DRVL-off to DRVH-on 10 22 35
V5IN-VBST
VBST
VIN= 28 V, V
TA= 25°C
, IF= 10 mA, TA= 25°C 0.1 0.2 V
= 34.5 V, VSW= 28 V, TA= 25°C 0.01 1.5 μA
= 0.7 V, RRF= 39kΩ,
OUT
(1)
= 95% 1 ms
OUT
PG in from lower 92.5% 95% 97.5%
PG hysteresis 2.5% 5% 7.5%
= 0.5 V 3 6 mA
PGOOD
Enable 1.8
Disable 0.5
RRF= 470 kΩ, TA= 25°C
RRF= 200 kΩ, TA= 25°C
RRF= 100 kΩ, TA= 25°C
RRF= 39 kΩ, TA= 25°C
(2)
(2)
(2)
(2)
CCM 1.8
Auto-skip 0.5
OUT
= 1.1 V, I
= 10 A using application circuit shown in Figure 21.
OUT
www.ti.com
0.7000 V
Ω
ns
266 290 314
312 340 368
349 380 411
395 430 465
4 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS51218
TPS51218
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
over recommended free-air temperature range, V5IN=5V. (Unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PROTECTION: CURRENT SENSE
I
TRIP
TC
ITRIP
V
TRIP
V
OCL
V
OCLN
V
AZCADJ
PROTECTION: UVP AND OVP
V
OVP
t
OVPDEL
V
UVP
t
UVPDEL
t
UVPEN
UVLO
V
UVV5IN
THERMAL SHUTDOWN
T
SDN
(3) Ensured by design. Not production tested.
TRIP source current V
TRIP current temperature
coeffficient
Current limit threshold setting
range
Current limit threshold V
Negative current limit threshold V
Adaptive zero cross adjustable
range
= 1V, TA= 25°C 9 10 11 μA
TRIP
On the basis of 25°C 4700 ppm/°C
V
TRIP-GND
V
TRIP
TRIP
V
TRIP
V
TRIP
TRIP
V
TRIP
Voltage 0.2 3 V
= 3.0 V 355 375 395
= 1.6 V 185 200 215 mV
= 0.2 V 17 25 33
= 3.0 V –395 –375 –355
= 1.6 V –215 –200 –185 mV
= 0.2 V –33 –25 –17
Positive 3 15
Negative –15 –3
OVP trip threshold OVP detect 115% 120% 125%
OVP propagation delay time 50-mV overdrive 1 μs
Output UVP trip threshold UVP detect 65% 70% 75%
Output UVP propagation delay
time
Output UVP enable delay time From Enable to UVP workable 1.0 1.2 1.4 ms
V5IN UVLO threshold V
Thermal shutdown threshold °C
Wake up 4.20 4.38 4.50
Shutdown 3.7 3.93 4.1
Shutdown temperature
Hysteresis
(3)
(3)
SLUS935B –MAY 2009– REVISED FEBRUARY 2012
mV
0.8 1 1.2 ms
145
10
Copyright © 2009–2012, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): TPS51218
1
2
3
4
5
10
9
8
7
6
PGOOD
TRIP
EN
VFB
RF
VBST
DRVH
SW
V5IN
DRVL
TPS51218DSC
GND
DSC PACKAGE
(TOP VIEW)
TRIP
OCL
V
V8=
TPS51218
SLUS935B –MAY 2009– REVISED FEBRUARY 2012
DEVICE INFORMATION
Thermal pad is used as an active terminal of GND.
PIN FUNCTIONS
PIN
NAME NO.
DRVH 9 O
DRVL 6 O
EN 3 I SMPS enable pin. Short to GND to disable the device.
GND I Ground
PGOOD 1 O voltage. Continuous current capability is 1 mA. PGOOD goes high 1 ms after VFB becomes within
Thermal
Pad
I/O DESCRIPTION
High-side MOSFET driver output. The SW node referenced floating driver. The gate drive voltage is
defined by the voltage across VBST to SW node bootstrap flying capacitor
Synchronous MOSFET driver output. The GND referenced driver. The gate drive voltage is defined by
V5IN voltage.
Power Good window comparator open drain output. Pull up with resistor to 5 V or appropriate signal
specified limits. Power bad, or the terminal goes low, after a 2- μs delay.
Switching frequency selection. Connect a resistance to select switching frequency as shown in Table 1.
www.ti.com
RF 5 I Auto-skip or forced CCM selection.
SW 8 I
TRIP 2 I
V5IN 7 I 5 V +30%/–10% power supply input.
VBST 10 I
VFB 4 I SMPS feedback input. Connect the feedback resistor divider.
6 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated
The switching frequency is detected and stored into internal registers during startup. This pin also controls
Pull down to GND with resistor : Auto-Skip
Connect to PGOOD with resistor: forced CCM after PGOOD becomes high.
Switch node. A high-side MOSFET gate drive return. Also used for on time generation and output
discharge.
OCL detection threshold setting pin. 10 μA at room temperature, 4700 ppm/°C current is sourced and set
the OCL trip voltage as follows.
(0.2 V ≤ V
Supply input for high-side MOSFET driver (bootstrap terminal). Connect a flying capacitor from this pin to
the SW pin. Internally connected to V5IN via bootstrap MOSFET switch.
Product Folder Link(s): TPS51218
TRIP
≤ 3 V)
GND
SW
TPS51218
OCP
ZC
XCON
RF
FCCM
VBST
V5IN
PWM
VFB
TRIP
Auto-skip/FCCM
+
+
Delay
0.7 V +10/15%
0.7 V –5/10%
PGOOD
Control Logic
UDG-09065
10 mA
+
+
0.7 V –30%
0.7 V +20%
+
+
EN
Ramp Comp
Enable/SS Control
+
+
+
+
0.7 V
x(-1/8)
x(1/8)
Frequency
Setting
Detector
DRVH
DRVL
t
ON
One-
Shot
Auto-skip
UV
OV
TPS51218
www.ti.com
SLUS935B –MAY 2009– REVISED FEBRUARY 2012
FUNCTIONAL BLOCK DIAGRAM
Copyright © 2009–2012, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): TPS51218
–50
200
0
0
50 100 150
600
400
1000
800
V
V5IN
= 5 V
VEN= 5 V
V
VFB
= 0.735 V
No Load
TJ– Junction Temperature – °C
I
V5IN
– V5IN Supply Current – mA
–50
0
0 50 100 150
TJ– Junction Temperature – °C
4
12
8
20
16
I
V5INSDN
– V5IN Shutdown Current – mA
10
6
18
14
2
V
V5IN
= 5 V
VEN= 0 V
No Load
–50
0
0 50 100 150
TJ– Junction Temperature – °C
150
V
OVP
/V
UVP
– OVP/UVP Trip Threshold – %
50
100
OVP
V
V5IN
= 5 V
UVP
–50 0 50 100 150
TJ– Junction Temperature – °C
V
V5IN
= 5 V
V
TRIP
= 1 V
0
4
12
8
20
16
I
TRIP
– Current Sense Current – mA
10
6
18
14
2
TPS51218
SLUS935B –MAY 2009– REVISED FEBRUARY 2012
V5IN SUPPLY CURRENT V5IN SHUTDOWN CURRENT
vs vs
JUNCTION TEMPERATURE JUNCTION TEMPERATURE
www.ti.com
TYPICAL CHARACTERISTICS
Figure 1. Figure 2.
OVP/UVP THRESHOLD CURRENT SENSE CURRENT (I
vs vs
JUNCTION TEMPERATURE JUNCTION TEMPERATURE
TRIP
)
Figure 3. Figure 4.
8 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS51218
6
200
10 14 18 22
VIN– Input Voltage – V
250
500
f
SW
– Switching Frequency – kHz
350
300
450
400
IO= 10 A
Auto-Skip
8 12 16 20
RRF= 100 kW
RRF= 39 kW
RRF= 200 kW
RRF= 470 kW
0.001
0.1
0.01 100
I
OUT
– Output Current – A
1
1000
f
SW
– Switching Frequency – kHz
10
100
VIN= 12 V
RRF= 470 kW
0.1 1 10
FCCM
Auto-Skip
0.001
0.1
0.01 100
1
1000
f
SW
– Switching Frequency – kHz
10
100
VIN= 12 V
RRF= 200 kW
0.1 1 10
FCCM
Auto-Skip
I
OUT
– Output Current – A
0.001
0.1
0.01 100
1
1000
f
SW
– Switching Frequency – kHz
10
100
VIN= 12 V
RRF= 100 kW
0.1 1 10
FCCM
Auto-Skip
I
OUT
– Output Current – A
TPS51218
www.ti.com
SLUS935B –MAY 2009– REVISED FEBRUARY 2012
TYPICAL CHARACTERISTICS (continued)
SWITCHING FREQUENCY SWITCHING FREQUENCY
vs vs
INPUT VOLTAGE OUTPUT CURRENT
Figure 5. Figure 6.
SWITCHING FREQUENCY SWITCHING FREQUENCY
vs vs
OUTPUT CURRENT OUTPUT CURRENT
Copyright © 2009–2012, Texas Instruments Incorporated Submit Documentation Feedback 9
Figure 7. Figure 8.
Product Folder Link(s): TPS51218
0.001
0.1
0.01 100
1
1000
f
SW
– Switching Frequency – kHz
10
100
VIN= 12 V
RRF= 39 kW
0.1 1 10
FCCM
Auto-Skip
I
OUT
– Output Current – A
0.001 0.01 100
VIN= 12 V
RRF= 470 kW
0.1 1 10
I
OUT
– Output Current – A
MODE
Auto-Skip
FCCM
1.08
1.09
1.12
V
OUT
– Output Voltage – V
1.10
1.11
h – Efficiency – %
0.001 0.01 1000.1 1 10
I
OUT
– Output Current – A
0
100
50
80
70
60
RRF= 470 kW
V
OUT
= 1.1 V
90
Auto-Skip
FCCM
20
30
10
40
VIN(V)
8
12
20
1.08
1.09
1.12
V
OUT
– Output Voltage – V
1.10
1.11
Auto-Skip
RRF= 470 kW
6 8 16 18 22
VIN– Input Voltage – V
201410 12
I
OUT
= 20 A
I
OUT
= 0 A
TPS51218
SLUS935B –MAY 2009– REVISED FEBRUARY 2012
TYPICAL CHARACTERISTICS (continued)
SWITCHING FREQUENCY OUTPUT VOLTAGE
vs vs
OUTPUT CURRENT OUTPUT CURRENT
www.ti.com
Figure 9. Figure 10.
OUTPUT VOLTAGE 1.1-V EFFICIENCY
vs vs
INPUT VOLTAGE OUTPUT CURRENT
10 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated
Figure 11. Figure 12.
Product Folder Link(s): TPS51218
TPS51218
www.ti.com
SLUS935B –MAY 2009– REVISED FEBRUARY 2012
TYPICAL CHARACTERISTICS (continued)
Figure 13. 1.1-V Start-Up Waveform Figure 14. Pre-Biased Start-Up Waveform
X X
X X
X X
Figure 15. 1.1-V Soft-Stop Waveform Figure 16. 1.1-V Load Transient Response
Copyright © 2009–2012, Texas Instruments Incorporated Submit Documentation Feedback 11
X X
X X
X X
Product Folder Link(s): TPS51218
TPS51218
SLUS935B –MAY 2009– REVISED FEBRUARY 2012
www.ti.com
APPLICATION INFORMATION
GENERAL DESCRIPTION
The TPS51218 is a high-efficiency, single channel, synchronous buck regulator controller suitable for low output
voltage point-of-load applications in notebook computers and similar digital consumer applications. The device
features proprietary D-CAP™ mode control combined with adaptive on-time architecture. This combination is
ideal for building modern low duty ratio, ultra-fast load step response DC-DC converters. The output voltage
ranges from 0.7 V to 2.6 V. The conversion input voltage range is from 3 V to 28 V. The D-CAP™ mode uses the
ESR of the output capacitor(s) to sense current information. An advantage of this control scheme is that it does
not require an external phase compensation network, helping the designer with ease-of-use and realizing low
external component count configuration. The switching frequency is selectable from four preset values using a
resistor connected from the RF pin to ground. Adaptive on-time control tracks the preset switching frequency
over a wide range of input and output voltages, while it increases the switching frequency at step-up of load.
The RF pin also serves in selecting between auto-skip mode and forced continuous conduction mode for light
load conditions. The strong gate drivers of the TPS51218 allow low R
FETs for high current applications.
DS(on)
ENABLE AND SOFT START
When the EN pin voltage rises above the enable threshold, (typically 1.2 V) the controller enters its start-up
sequence. The first 250 μs calibrates the switching frequency setting resistance attached at RF to GND and
stores the switching frequency code in internal registers. A voltage of 0.1 V is applied to RF for measurement.
Switching is inhibited during this phase. In the second phase, internal DAC starts ramping up the reference
voltage from 0 V to 0.7 V. This ramping time is 750 μs. Smooth and constant ramp up of the output voltage is
maintained during start up regardless of load current. Connect a 1-kΩ resistor in series with the EN pin to provide
protection.
ADAPTIVE ON-TIME D-CAP™ CONTROL
TPS51218 does not have a dedicated oscillator that determines switching frequency. However, the device runs
with pseudo-constant frequency by feed-forwarding the input and output voltages into its on-time one-shot timer.
The adaptive on-time control adjusts the on-time to be inversely proportional to the input voltage and proportional
to the output voltage (tON∝ V
conditions over wide input voltage range. The switching frequency is selectable from four preset values by a
resistor connected to RF as shown in Table 1. (Leaving the resistance open sets the switching frequency to the
lowest value, 290 kHz. However, it is recommended to apply one of the resistances on the table in any
application designs.)
The off-time is modulated by a PWM comparator. The VFB node voltage (the mid point of resistor divider) is
compared to the internal 0.7-V reference voltage added with a ramp signal. When both signals match, the PWM
comparator asserts the set signal to terminate the off-time (turn off the low-side MOSFET and turn on high-side
MOSFET). The set signal becomes valid if the inductor current level is below OCP threshold, otherwise the
off-time is extended until the current level to become below the threshold.
/ VIN). This makes the switching frequency fairly constant in steady state
OUT
Table 1. Resistor and Switching Frequency
RESISTANCE (RRF)
(kΩ)
470 290
200 340
100 380
39 430
SWITCHING
FREQUENCY (fSW)
(kHz)
12 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS51218
R1
R2
Voltage Divider
+
V
FB
+
0.7 V
PWM
Control
Logic
and
Driver
V
IN
L
ESR
C
O
V
C
R
L
I
IND
I
OUT
UDG-09063
I
C
Switching Modulator
Output
Capacitor
DRVH
DRVL
V
OUT
O
1
H(s)
s ESR C
=
´ ´
f
SW
0
O
1
f
2 ESR C 4
= £
p´ ´
TPS51218
www.ti.com
SLUS935B –MAY 2009– REVISED FEBRUARY 2012
SMALL SIGNAL MODEL
From small-signal loop analysis, a buck converter using D-CAP™ mode can be simplified as shown in Figure 17.
Figure 17. Simplified Modulator Model
The output voltage is compared with internal reference voltage (ramp signal is ignored here for simplicity). The
PWM comparator determines the timing to turn on the high-side MOSFET. The gain and speed of the
comparator can be assumed high enough to keep the voltage at the beginning of each on cycle substantially
constant.
(1)
For loop stability, the 0-dB frequency, ƒ0, defined in Equation 2 need to be lower than 1/4 of the switching
frequency.
(2)
According to Equation 2, the loop stability of D-CAP™ mode modulator is mainly determined by the capacitor's
chemistry. For example, specialty polymer capacitors (SP-CAP) have COon the order of several 100 μF and
ESR in range of 10 mΩ. These makes f0on the order of 100 kHz or less and the loop is stable. However,
ceramic capacitors have an ƒ0of more than 700 kHz, which is not suitable for this modulator.
RAMP SIGNAL
The TPS51218 adds a ramp signal to the 0.7-V reference in order to improve its jitter performance. As described
in the previous section, the feedback voltage is compared with the reference information to keep the output
voltage in regulation. By adding a small ramp signal to the reference, the S/N ratio at the onset of a new
switching cycle is improved. Therefore the operation becomes less jittery and more stable. The ramp signal is
controlled to start with –7 mV at the beginning of ON-cycle and becomes 0 mV at the end of OFF-cycle in
continuous conduction steady state.
Copyright © 2009–2012, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): TPS51218
( )
f
IN OUT OUT
O LL
SW IN
(V V ) V
1
I
2 L V
- ´
= ´
´ ´
TPS51218
SLUS935B –MAY 2009– REVISED FEBRUARY 2012
www.ti.com
LIGHT LOAD CONDITION IN AUTO-SKIP OPERATION
With RF pin pulled down to low via RRF, the TPS51218 automatically reduces switching frequency at light load
conditions to maintain high efficiency. As the output current decreases from heavy load condition, the inductor
current is also reduced and eventually comes to the point that its rippled valley touches zero level, which is the
boundary between continuous conduction and discontinuous conduction modes. The rectifying MOSFET is
turned off when this zero inductor current is detected. As the load current further decreases, the converter runs in
to discontinuous conduction mode. The on-time is kept almost the same as it was in the continuous conduction
mode so that it takes longer time to discharge the output capacitor with smaller load current to the level of the
reference voltage. The transition point to the light load operation I
(i.e., the threshold between continuous and
O(LL)
discontinuous conduction mode) can be calculated in Equation 3.
where
• fSWis the PWM switching frequency (3)
Switching frequency versus output current in the light load condition is a function of L, VINand V
decreases almost proportional to the output current from the I
at I
/5 if the frequency setting is 290 kHz.
O(LL)
given in Equation 3. For example, it is 58 kHz
O(LL)
OUT
, but it
ADAPTIVE ZERO CROSSING
The TPS51218 has an adaptive zero crossing circuit which performs optimization of the zero inductor current
detection at skip mode operation. This function pursues ideal low-side MOSFET turning off timing and
compensates inherent offset voltage of the ZC comparator and delay time of the ZC detection circuit. It prevents
SW-node swing-up caused by too late detection and minimizes diode conduction period caused by too early
detection. As a result, better light load efficiency is delivered.
FORCED CONTINUOUS CONDUCTION MODE
When the RF pin is tied high, the controller keeps continuous conduction mode (CCM) in light load condition. In
this mode, switching frequency is kept almost constant over the entire load range which is suitable for
applications need tight control of the switching frequency at a cost of lower efficiency. To set the switching
frequency to be the same as Auto-skip mode, it is recommended to connect RRFto PGOOD. In this way, RF is
tied low prior to soft-start operation to set frequency and tied high after powergood indicates high.
OUTPUT DISCHARGE CONTROL
When EN is low, the TPS51218 discharges the output capacitor using internal MOSFET connected between SW
and GND while high-side and low-side MOSFETs are kept off. The current capability of this MOSFET is limited to
discharge slowly.
LOW-SIDE DRIVER
The low-side driver is designed to drive high current low R
represented by its internal resistance, which are 1.0Ω for V5IN to DRVL and 0.5Ω for DRVL to GND. A dead time
to prevent shoot through is internally generated between high-side MOSFET off to low-side MOSFET on, and
low-side MOSFET off to high-side MOSFET on. 5-V bias voltage is delivered from V5IN supply. The
instantaneous drive current is supplied by an input capacitor connected between V5IN and GND. The average
drive current is equal to the gate charge at Vgs=5V times switching frequency. This gate drive current as well as
the high-side gate drive current times 5V makes the driving power which need to be dissipated from TPS51218
package.
N-channel MOSFET(s). The drive capability is
DS(on)
HIGH-SIDE DRIVER
The high-side driver is designed to drive high current, low R
floating driver, 5 V of bias voltage is delivered from V5IN supply. The average drive current is also equal to the
gate charge at VGS=5V times switching frequency. The instantaneous drive current is supplied by the flying
capacitor between VBST and SW pins. The drive capability is represented by its internal resistance, which are
1.5 Ω for VBST to DRVH and 0.7 Ω for DRVH to SW.
N-channel MOSFET(s). When configured as a
DS(on)
14 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS51218
TRIP TRIP TRIP
V (mV) R (k ) I ( A)= W ´ m
( )
f
IND ripple
IN OUT OUT
TRIP TRIP
OCP
DS(on) DS(on) SW IN
I
(V V ) V
V V
1
I
8 R 2 8 R 2 L V
æ ö
- ´
ç ÷
= + = + ´
ç ÷
´ ´ ´ ´
è ø
TPS51218
www.ti.com
SLUS935B –MAY 2009– REVISED FEBRUARY 2012
POWER-GOOD
The TPS51218 has powergood output that indicates high when switcher output is within the target. The
powergood function is activated after soft-start has finished. If the output voltage becomes within +10%/–5% of
the target value, internal comparators detect power-good state and the power-good signal becomes high after a
1-ms internal delay. If the output voltage goes outside of +15%/–10% of the target value, the powergood signal
becomes low after a 2-μs internal delay. The powergood output is an open-drain output and must be pulled up
externally.
CURRENT SENSE AND OVER CURRENT PROTECTION
TPS51218 has cycle-by-cycle overcurrent limiting control. The inductor current is monitored during the OFF state
and the controller keeps the OFF state during the inductor current is larger than the overcurrent trip level. To
provide both good accuracy and cost effective solution, the TPS51218 supports temperature compensated
MOSFET R
R
. The TRIP terminal sources I
TRIP
set to the OCL trip voltage V
internally.
The inductor current is monitored by the voltage between GND pad and SW pin so that the SW pin should be
connected to the drain terminal of the low-side MOSFET properly. I
compensate the temperature dependency of the R
that GND should be connected to the proper current sensing device, i.e. the source terminal of the low-side
MOSFET.
As the comparison is done during the OFF state, V
current at overcurrent threshold, I
sensing. The TRIP pin should be connected to GND through the trip voltage setting resistor,
DS(on)
TRIP
current, which is 10μA typically at room temperature, and the trip level is
TRIP
as shown in Equation 4. Note that V
. GND is used as the positive current sensing node so
DS(on)
sets valley level of the inductor current. Thus, the load
, can be calculated in Equation 5
OCP
TRIP
TRIP
is limited up to approximately 3 V
TRIP
has 4700ppm/°C temperature slope to
(4)
(5)
In an overcurrent condition, the current to the load exceeds the current to the output capacitor thus the output
voltage tends to fall down. Eventually, it crosses the undervoltage protection threshold and shuts down the
controller.
When the device is operating in the forced continuous conduction mode, the negative current limit (NCL) protects
the external FET from carrying too much current. The NCL detect threshold is set as the same absolute value as
positive OCL but negative polarity. Please be noted the threshold still represents the valley value of the inductor
current.
OVER/UNDER VOLTAGE PROTECTION
TPS51218 monitors a resistor divided feedback voltage to detect over and undervoltage. When the feedback
voltage becomes higher than 120% of the target voltage, the OVP comparator output goes high and the circuit
latches as the high-side MOSFET driver OFF and the low-side MOSFET driver ON.
When the feedback voltage becomes lower than 70% of the target voltage, the UVP comparator output goes
high and an internal UVP delay counter begins counting. After a 1-ms delay, TPS51218 latches OFF both
high-side and low-side MOSFETs drivers. This function is enabled after 1.2 ms following EN has become high.
UVLO PROTECTION
TPS51218 has V5IN undervoltage lockout protection (UVLO). When the V5IN voltage is lower than UVLO
threshold voltage, the switch mode power supply shuts off. This is non-latch protection.
THERMAL SHUTDOWN
TPS51218 monitors the die temperature. If the temperature exceeds the threshold value (typically 145°C), the
TPS51218 is shut off. This is non-latch protection.
Copyright © 2009–2012, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): TPS51218
( )
(
)
( )
( )
( )
(
)
( )
f f
OUT OUT OUT OUT
IN max IN max
IND(ripple) SW SW
IN max OUT max IN max
V V V V V V
1 3
L
I V I V
- ´ - ´
= ´ = ´
´ ´
( )
(
)
( )
f
OUT OUT
IN m ax
TRIP
IND(peak)
DS(on) SW
IN m ax
V V V
V
1
I
8 R L V
- ´
= + ´
´ ´
( )
f
f
OUT SW
SW
IND(ripple)
V 10 mV 1 D 10 mV L
L
ESR
0.7 V I 0.7 V 70
´ ´ - ´ ´
é ù é ù
´
ë û ë û
= = = W
é ù
ë û
´
é ù é ù
ë û ë û
t
SW
t – Time
0
V
VFB
– Feedback Voltage – mV
10
tSWx (1-D)
V
RIPPLE(FB)
TPS51218
SLUS935B –MAY 2009– REVISED FEBRUARY 2012
www.ti.com
EXTERNAL COMPONENTS SELECTION
Selecting external components is simple in D-CAP™ mode.
1. Choose the inductor.
The inductance value should be determined to give the ripple current of approximately 1/4 to 1/2 of maximum
output current. Larger ripple current increases output ripple voltage and improves S/N ratio and helps stable
operation.
(6)
The inductor also needs to have low DCR to achieve good efficiency, as well as enough room above peak
inductor current before saturation. The peak inductor current can be estimated in Equation 7.
(7)
2. Choose the output capacitor(s).
Organic semiconductor capacitor(s) or specialty polymer capacitor(s) are recommended. For loop stability,
capacitance and ESR should satisfy Equation 2. For jitter performance, Equation 8 is a good starting point to
determine ESR.
where
• D is the duty ratio
• the output ripple down slope rate is 10 mV/tSWin terms of VFB terminal voltage as shown in Figure 18
• tSWis the switching period (8)
16 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated
Figure 18. Ripple Voltage Down Slope
Product Folder Link(s): TPS51218
IND(ripple)
OUT
I ESR
V 0.7
2
R1 R2
0.7
´
æ ö
- -
ç ÷
ç ÷
è ø
= ´
UDG-09066
TPS51218
DRVL
4
VIN
1 mF
VFB
V5IN
V
OUT
2
TRIP
5
RF
# 2
# 1
# 3
5
6
Thermal Pad
GND
TPS51218
www.ti.com
SLUS935B –MAY 2009– REVISED FEBRUARY 2012
3. Determine the value of R1 and R2.
The output voltage is programmed by the voltage-divider resistor, R1 and R2, shown in Figure 17. R1 is
connected between the VFB pin and the output, and R2 is connected between the VFB pin and GND. Typical
designs begin with the selection of an R2 value between 10 kΩ and 20 kΩ. Determine R1 using Equation 9.
(9)
LAYOUT CONSIDERATIONS
Figure 19. Ground System of DC/DC Converter Using the TPS51218
Certain points must be considered before starting a layout work using the TPS51218.
• Inductor, VINcapacitor(s), V
on one side of the PCB (solder side). Other small signal components should be placed on another side
(component side). At least one inner plane should be inserted, connected to ground, in order to shield and
isolate the small signal traces from noisy power lines.
• All sensitive analog traces and components such as VFB, PGOOD, TRIP and RF should be placed away
from high-voltage switching nodes such as SW, DRVL, DRVH or VBST to avoid coupling. Use internal
layer(s) as ground plane(s) and shield feedback trace from power traces and components.
• The DC/DC converter has several high-current loops. The area of these loops should be minimized in order to
suppress generating switching noise.
– The most important loop to minimize the area of is the path from the VINcapacitor(s) through the high and
low-side MOSFETs, and back to the capacitor(s) through ground. Connect the negative node of the V
capacitor(s) and the source of the low-side MOSFET at ground as close as possible. (Refer to loop #1 of
Figure 19)
– The second important loop is the path from the low-side MOSFET through inductor and V
and back to source of the low-side MOSFET through ground. Connect source of the low-side MOSFET
and negative node of V
– The third important loop is of gate driving system for the low-side MOSFET. To turn on the low-side
MOSFET, high current flows from V5IN capacitor through gate driver and the low-side MOSFET, and back
to negative node of the capacitor through ground. To turn off the low-side MOSFET, high current flows
Copyright © 2009–2012, Texas Instruments Incorporated Submit Documentation Feedback 17
capacitor(s) and MOSFETs are the power components and should be placed
OUT
capacitor(s) at ground as close as possible. (Refer to loop #2 of Figure 19)
OUT
Product Folder Link(s): TPS51218
OUT
IN
capacitor(s),
UDG-09067
TPS51218
Thermal Pad
DRVL
4 5
VIN
1 mF
VFB
V5IN
6
V
OUT
2
TRIP
5
RF
0.1 mF
100 W
VTT_SENSE
VSS_SENSE
GND
TPS51218
SLUS935B –MAY 2009– REVISED FEBRUARY 2012
www.ti.com
from gate of the low-side MOSFET through the gate driver and GND pad of the device, and back to
source of the low-side MOSFET through ground. Connect negative node of V5IN capacitor, source of the
low-side MOSFET and GND pad of the device at ground as close as possible. (Refer to loop #3 of
Figure 19)
• Since the TPS51218 controls output voltage referring to voltage across V
the voltage divider should be connected to the positive node of V
OUT
bottom side resistor and GND pad of the device should be connected to the negative node of V
capacitor, the top-side resistor of
OUT
capacitor. In a same manner both
capacitor.
OUT
The trace from these resistors to the VFB pin should be short and thin. Place on the component side and
avoid via(s) between these resistors and the device.
• Connect the overcurrent setting resistors from TRIP pin to ground and make the connections as close as
possible to the device. The trace from TRIP pin to resistor and from resistor to ground should avoid coupling
to a high-voltage switching node.
• Connect the frequency setting resistor from RF pin to ground, or to the PGOOD pin, and make the
connections as close as possible to the device. The trace from the RF pin to the resistor and from the resistor
to ground should avoid coupling to a high-voltage switching node.
• Connections from gate drivers to the respective gate of the high-side or the low-side MOSFET should be as
short as possible to reduce stray inductance. Use 0.65 mm (25 mils) or wider trace and via(s) of at least
0.5 mm (20 mils) diameter along this trace.
• The PCB trace defined as switch node, which connects to source of high-side MOSFET, drain of low-side
MOSFET and high-voltage side of the inductor, should be as short and wide as possible.
LAYOUT CONSIDERATIONS TO REMOTE SENSING
Figure 20. Remote Sensing of Output Voltage Using the TPS51218
• Make a Kelvin connection to the load device.
• Run the feedback signals as a differential pair to the device. The distance of these parallel pair should be as
short as possible.
• Run the lines in a quiet layer. Isolate them from noisy signals by a voltage or ground plane.
18 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS51218
1
2
3
4
10
9
8
7
VBST
DRVH
SW
V5IN
PGOOD
TRIP
EN
VFB
U1
TPS51218
5 6DRVLRF
GND
C2
1 mF
C1
0.1 mF
C4
330 mF x 4
C3
10 mF x 4
L1
0.45 mH
R6
100 kW
R3
1 kW
R1
5.6 kW
V
IN
8 V
to
20 V
V
OUT
1.1 V
18 A
V
OUT
_GND
EN
V5IN
4.5 V
to
6.5 V
R5
30 kW
R2
10 kW
UDG-09068
R4
(A)
470 kW
Q2
FDMS8670AS
Q1
FDMS8680
Q3
FDMS8670AS
R7
3.3 W
1
2
3
4
10
9
8
7
VBST
DRVH
SW
V5IN
PGOOD
TRIP
EN
VFB
U1
TPS51218
5 6DRVLRF
GND
C2
1 mF
C1
0.1 mF
C4
330 mF x 4
C3
10 mF x 4
L1
0.45 mH
R6
100 kW
R3
1 kW
R1
5.6 kW
V
IN
8 V
to
20 V
V
OUT
1.1 V
18 A
V
OUT
_GND
EN
V5IN
4.5 V
to
6.5 V
R5
30 kW
R2
10 kW
UDG-09069
Q2
FDMS8670AS
Q1
FDMS8680
Q3
FDMS8670AS
R4
(A)
470 kW
R7
3.3 W
TPS51218
www.ti.com
TPS51218 APPLICATION CIRCUITS
Figure 21. 1.1-V/18-A Auto-Skip Mode
SLUS935B –MAY 2009– REVISED FEBRUARY 2012
A. See Table 1 for resistor/frequency values.
Figure 22. 1.1-V/18-A Forced Continuous Conduction Mode
Product Folder Link(s): TPS51218
Copyright © 2009–2012, Texas Instruments Incorporated Submit Documentation Feedback 19
TPS51218
SLUS935B –MAY 2009– REVISED FEBRUARY 2012
Table 2. 1.1-V, 18-A, 290-kHz Application List of Materials
REFERENCE
DESIGNATOR
C3 1 4 × 10 μF, 25 V Taiyo Yuden TMK325BJ106MM
C4 1 4 × 330 μF, 2 V, 12 mΩ Panasonic EEFCX0D331XR
L1 1 0.45 μH, 25 A, 1.1 mΩ Panasonic ETQP4LR45XFC
Q1 1 30 V, 35 A, 8.5 mΩ Fairchild FDMS8680
Q2, Q3 2 30 V, 42 A, 3.5 mΩ Fairchild FDMS8670AS
QTY SPECIFICATION MANUFACTURER PART NUMBER
www.ti.com
20 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS51218
TPS51218
www.ti.com
SLUS935B –MAY 2009– REVISED FEBRUARY 2012
Changes from Revision A (June 2009) to Revision B Page
• Added DRVH, pulse width < 20 ns rating in ABSOLUTE MAXIMUM RATINGS table ........................................................ 2
• Added DRVL, pulse width < 20 ns rating in ABSOLUTE MAXIMUM RATINGS table ......................................................... 2
Copyright © 2009–2012, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Link(s): TPS51218
PACKAGE MATERIALS INFORMATION
www.ti.com 14-May-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type
TPS51218DSCR WSON DSC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS51218DSCR WSON DSC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS51218DSCT WSON DSC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
Package
Drawing
Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm)B0(mm)K0(mm)P1(mm)W(mm)
Pin1
Quadrant
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-May-2014
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS51218DSCR WSON DSC 10 3000 367.0 367.0 35.0
TPS51218DSCR WSON DSC 10 3000 367.0 367.0 35.0
TPS51218DSCT WSON DSC 10 250 210.0 185.0 35.0
Pack Materials-Page 2
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