•Output Voltage Range: 0.7 V to 2.6 V•I/O Supplies
•Wide Output Load Range: 0 to 20A+•System Power Supplies
•Built-in 0.5% 0.7 V Reference
•D-CAP™ Mode with 100-ns Load Step
Response
•Adaptive On Time Control Architecture With 4
Selectable Frequency Setting
•4700 ppm/°C R
•Internal 1-ms Voltage Servo Softstart
•Pre-Charged Start-up Capability
•Built in Output Discharge
•Power Good Output
•Integrated Boost Switch
•Built-in OVP/UVP/OCP
•Thermal Shutdown (Non-latch)
•SON-10 (DSC) Package
Current Sensing
DS(on)
APPLICATIONS
•Notebook Computers
DESCRIPTION
The TPS51218 is a small-sized single buck controller
with adaptive on-time D-CAP™ mode. The device is
suitable for low output voltage, high current, PC
system power rail and similar point-of-load (POL)
power supply in digital consumer products. A small
package with minimal pin-count saves space on the
PCB, while a dedicated EN pin and pre-set frequency
selections minimize design effort required for new
designs. The skip-mode at light load condition, strong
gate drivers and low-side FET R
supports low-loss and high efficiency, over a broad
load range. The conversion input voltage which is the
high-side FET drain voltage ranges from 3 V to 28 V
and the output voltage ranges from 0.7 V to 2.6 V.
The device requires an external 5-V supply. The
TPS51218 is available in a 10-pin SON package
specified from –40°C to 85°C.
current sensing
DS(on)
TYPICAL APPLICATION CIRCUIT
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2D-CAP is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
T
A
PACKAGEPINS
–40°C to 85°CPlastic SON PowerPAD
ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature range (unless otherwise noted)
VBST–0.3 to 37
(3)
Input voltage range
Output voltage range
T
J
T
STG
(2)
(2)
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the network ground terminal unless otherwise noted.
(3) Voltage values are with respect to the SW terminal.
VBST
SW–5 to 30
V5IN, EN, TRIP, VFB, RF–0.3 to 7
DRVH–5 to 37
(3)
DRVH
(3)
DRVH
, pulse width < 20 ns–2.5 to 7
DRVL–0.5 to 7
DRVL, pulse width < 20 ns–2.5 to 7
PGOOD–0.3 to 7
Junction temperature range150°C
Storage temperature range–55 to 150°C
ORDERING DEVICEOUTPUTMINIMUM
NUMBERSUPPLYQUANTITY
TPS51218DSCR10Tape and reel3000
TPS51218DSCT10Mini reel250
VALUEUNIT
–0.3 to 7
–0.3 to 7
V
V
DISSIPATION RATINGS
2-oz. trace and copper pad with solder.
PACKAGETA< 25°CDERATING FACTORTA= 85°C
10-pin DSC
(1)
(1) Enhanced thermal conductance by thermal vias is used beneath thermal pad as shown in Land Pattern information.
DRVL6O
EN3ISMPS enable pin. Short to GND to disable the device.
GNDIGround
PGOOD1Ovoltage. Continuous current capability is 1 mA. PGOOD goes high 1 ms after VFB becomes within
Thermal
Pad
I/ODESCRIPTION
High-side MOSFET driver output. The SW node referenced floating driver. The gate drive voltage is
defined by the voltage across VBST to SW node bootstrap flying capacitor
Synchronous MOSFET driver output. The GND referenced driver. The gate drive voltage is defined by
V5IN voltage.
Power Good window comparator open drain output. Pull up with resistor to 5 V or appropriate signal
specified limits. Power bad, or the terminal goes low, after a 2- μs delay.
Switching frequency selection. Connect a resistance to select switching frequency as shown in Table 1.
www.ti.com
RF5IAuto-skip or forced CCM selection.
SW8I
TRIP2I
V5IN7I5 V +30%/–10% power supply input.
VBST10I
VFB4ISMPS feedback input. Connect the feedback resistor divider.
The switching frequency is detected and stored into internal registers during startup. This pin also controls
Pull down to GND with resistor : Auto-Skip
Connect to PGOOD with resistor: forced CCM after PGOOD becomes high.
Switch node. A high-side MOSFET gate drive return. Also used for on time generation and output
discharge.
OCL detection threshold setting pin. 10 μA at room temperature, 4700 ppm/°C current is sourced and set
the OCL trip voltage as follows.
(0.2 V ≤ V
Supply input for high-side MOSFET driver (bootstrap terminal). Connect a flying capacitor from this pin to
the SW pin. Internally connected to V5IN via bootstrap MOSFET switch.