Texas Instruments TPS51124RGER Schematic [ru]

75 kΩ

9

10

11

12

PGOOD1

EN1

PGOOD2

EN2

TPS51124RGE

(QFN24)

13 14 15 16

VBST1

DRVL1

LL1

DRVH1

VBST2

DRVH2

LL2

DRVL2

17

8

7

6 5 4 3 2 1

18

19

20

21

22

23

24

VO1

1.05 V/10 A

Q2

IRF8113

L1

Q1

IRF7821

VO2

1.5 V/10 A

Q4

IRF8113

L2

Q3

IRF7821

Input Voltage

3 V to 28 V

C7

R6

C3

C1

C6

C4

R3

6.8

C8

R7

R1

R2
75

R5

R4

V5IN

4.5 V to 5.5 V

VO2

VO1

VFB2

TONSEL

GND

VFB1

PGND2

TRIP2

V5FILT

V5IN

TRIP1

PGND1

Power
Good2

EN2

C5

C2

Power
Good1

EN1

SGND

PGNDPGND

SGND

C9

SGND PGND

PGND

73.2 kΩ

kΩ

28.7 kΩ

22 µF

2 x 330 µF

1 µH

10 µF

0.1 µF

4.7 Fμ

6.8 kΩ

1 Fμ

3.3Ω
kΩ

0.1 µF

10 µF

1 µH

2 x 330 µF

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SLVS616C –NOVEMBER 2005–REVISED DECEMBER 2014

TPS51124 Dual Synchronous Step-Down Controller for Low-Voltage Power Rails

1 Features 3 Description

1

• High Efficiency, Low-Power Consumption,
Shutdowns to <1 μA

• Fixed Frequency Emulated On-Time Control,
Frequency Selectable From Three Options

• D-CAP™ Mode Enables Fast Transient Response

• Auto-Skip Mode

• Less Than 1% Initial Reference Accuracy

• Low Output Ripple

• Wide Input Voltage Range: 3 V to 28 V

• Output Voltage Range: 0.76 V to 5.5 V

• Low-Side R

Loss-less Current Sensing

DS(ON)

• Adaptive Gate Drivers With Integrated Boost
Diode

• Internal 1.2-ms Voltage-Servo Soft-Start

• Powergood Signals for Each Channel With Delay
Timer

• Output Discharge During Disable, Fault

2 Applications

Notebook I/O and Low-Voltage System Bus

The TPS51124 is a dual, adaptive on-time D-CAP™
mode synchronous buck controller. The part enables
system designers to cost effectively complete the
suite of notebook power bus regulators with the
absolute lowest external component count and lowest
standby consumption. The fixed frequency emulated
adaptive on-time control supports seamless operation
between PWM mode at heavy load condition and
reduced frequency operation at light load for high
efficiency down to milliampere range. The main
control loop for the TPS51124 uses the D-CAP mode
that optimized for low ESR output capacitors such as
POSCAP or SP-CAP promises fast transient
response with no external compensation. Simple and
separate power good signals for each channel allow
flexibility of power sequencing. The part provides a
convenient and efficient operation with supply input
voltages (V5IN, V5FILT) ranging from 4.5 V to 5.5 V,
conversion voltages (drain voltage for the
synchronous high-side MOSFET) from 3 V to 28 V
and output voltages from 0.76 V to 5.5 V.

The TPS51124 is available in 24-pin VQFN package
specified from –40°C to 85°C ambient temperature
range.

TPS51124

Device Information

(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

TPS51124 VQFN (24) 4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at

the end of the datasheet.

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

TPS51124

SLVS616C –NOVEMBER 2005–REVISED DECEMBER 2014

www.ti.com

Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description............................................................. 1

4 Revision History..................................................... 2

5 Pin Configuration and Functions......................... 3

6 Specifications......................................................... 4

6.1 Absolute Maximum Ratings .................................... 4

6.2 Recommended Operating Conditions...................... 4

6.3 Thermal Information.................................................. 4

6.4 Electrical Characteristics.......................................... 5

6.5 Typical Characteristics.............................................. 7

7 Detailed Description............................................ 10

7.1 Overview ................................................................. 10

7.2 Functional Block Diagram....................................... 10

7.3 Feature Description................................................. 11

7.4 Device Functional Modes........................................ 13

8 Application and Implementation........................ 14

8.1 Application Information............................................ 14

8.2 Typical Application.................................................. 14

9 Power Supply Recommendations...................... 18

10 Layout................................................................... 18

10.1 Layout Guidelines................................................. 18

10.2 Layout Example.................................................... 19

11 Device and Documentation Support................. 20

11.1 Third-Party Products Disclaimer ........................... 20

11.2 Trademarks........................................................... 20

11.3 Electrostatic Discharge Caution............................ 20

11.4 Glossary................................................................ 20

12 Mechanical, Packaging, and Orderable

Information........................................................... 20

4 Revision History

Changes from Revision B (September 2010) to Revision C Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and

Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1

Changes from Revision A (November 2005) to Revision B Page

• Changed From: pin 48 = PGND1 To: pin 18 = PGND1 in the Pin Out illustration................................................................. 3

• Updated the Function Block Diagram................................................................................................................................... 10

• Figure 19 - Removed the hysteretic symbol from the PWM component.............................................................................. 15

• Updated equation 9. Changed From: V

x 0.01 To: V

OUT

x 0.0132.................................................................................. 16

OUT

Changes from Original (November 2005) to Revision A Page

• Updated the the circut illustration, Pin 21 changed From DRVL1 To: DRVH1 and Pin 19 changed From: DRVH1 to

DRVL1.................................................................................................................................................................................... 1

• PG low hysteresis (PGOODx goes low) - deleted the Min -4% and Max -6% values ........................................................... 6

• PG high hysteresis (PGOODx goes low) - deleted the Min 4% and Max 6% values ............................................................ 6

• Hysteresis (recovery < 20 μs) - deleted the Min 8% and Max 12% values ........................................................................... 6

• Updated Figure 18, Pin 21 changed From DRVL1 To: DRVH1 and Pin 19 changed From: DRVH1 to DRVL1................. 14

2 Submit Documentation Feedback Copyright © 2005–2014, Texas Instruments Incorporated

Product Folder Links: TPS51124

PGOOD124

EN123

LL120DRVL1

19

DRVH121VBST1

22

PGND118
TRIP1

17

TRIP214
PGND213

V5FILT15

V5IN

16

VO1

1

VFB1

2

VFB2 5

VO2

6

TONSEL 4

GND

3

2

7

EN

2

8

LL

2

11

DRVL

2

12

DRVH

2

10

VBST

2

9

Thermal Pad

www.ti.com

5 Pin Configuration and Functions

TPS51124

SLVS616C –NOVEMBER 2005–REVISED DECEMBER 2014

24-Pin VQFN With Exposed Thermal Pad

RGE Package

Top View

Pin Functions

PIN

NAME NO.

DRVH1 21
DRVH2 10
DRVL1 19
DRVL2 12
EN1 23
EN2 8
GND 3 I Signal ground pin
LL1 20
LL2 11
PGND1 18
PGND2 13
PGOOD1 24 Power Good window comparator open drain output for channel 1 and 2. Pull up with a resistor to 5 V, or

PGOOD2 7
TONSEL 4 I On-time selection pin. See Table 1.

TRIP1 17 Overcurrent trip point set input. Connect resistor from this pin to GND to set threshold for synchronous low­TRIP2 14
VBST1 22 Supply input for synchronous high-side MOSFET driver (Boost Terminal). Connect capacitor from this pin
VBST2 9
VFB1 2

VFB2 5
VO1 1
VO2 6

V5FILT 15 I
V5IN 16 I 5-V power supply input for FET gate drivers. Internally connected to VBSTx by PN diodes.

Copyright © 2005–2014, Texas Instruments Incorporated Submit Documentation Feedback 3

I/O DESCRIPTION

Synchronous high-side MOSFET driver outputs. LL node referenced floating drivers. The gate drive voltage

O

is defined by the voltage across VBST to LL node flying capacitor.
Synchronous low-side MOSFET driver outputs. PGND referenced drivers. The gate-drive voltage is defined

O

by V5IN voltage.

I Channel 1 and channel 2 enable pins. Connect to 5 V or 3.3 V to turn on SMPS

Switch node connections for high-side drivers return. Also serve as input to current comparators and input

I/O

voltage monitor for on-time control circuitry.
Ground returns for DRVL1 and DRVL2. Also serve as input of current comparators. Connect PGND1,

I/O

PGND2, and GND strongly together near the IC. Output discharge current flows through this pin, also.

O appropriate signal voltage. Current capability is 5 mA. PGOOD goes high 0.5 ms after VFB comes within

specified limits. Power bad, or the terminal goes low, is within 10 μs.

I side R

current comparator.

I to respective LL terminals. An internal PN diode is connected between V5IN to each of these pins. User

can add external Schottky diode if forward drop is critical to drive the MOSFET.

I SMPS voltage feedback inputs. Connect with feedback resistor divider.

Output connections to SMPS. These terminals serve two functions: On-time adjustment and output

I

discharge.
5-V power supply input for the entire control circuit except the MOSFET drivers. Connect RC low-pass filter

from V5IN to V5FILT.

sense. Voltage across this pin and GND is compared to voltage across PGND and LL at over-

DS(on)

Product Folder Links: TPS51124

TPS51124

SLVS616C –NOVEMBER 2005–REVISED DECEMBER 2014

6 Specifications

www.ti.com

6.1 Absolute Maximum Ratings

(1)

over operating free-air temperature range (unless otherwise noted)

MIN MAX UNIT

VBST1, VBST2 –0.3 36

Input voltage V

Output
voltage

T

Operating ambient temperature –40 85 °C

A

T

Junction temperature –40 125 °C

J

T

Storage temperature –55 150 °C

stg

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to the network ground terminal unless otherwise noted

VBST1, VBST2 (wrt LLx) –0.3 6
V5IN, V5FILT, EN1, EN2, VFB1, VFB2, TRIP1, TRIP2, VO1,

VO2, TONSEL
DRVH1, DRVH2 –1 36
DRVH1, DRVH2 (wrt LLx) –0.3 6
LL1, LL2 –2 30 V
PGOOD1, PGOOD2, DRVL1, DRVL2 –0.3 6
PGND1, PGND2 –0.3 0.3

–0.3 6

6.2 Recommended Operating Conditions

over operating free-air temperature (unless otherwise noted)

MIN MAX UNIT

Supply input voltage V5IN, V5FILT 4.5 5.5 V

VBST1, VBST2 –0.1 34

Input voltage VBST1, VBST2 (wrt LLx) –0.1 5.5 V

EN1, EN2, VFB1, VFB2, TRIP1, TRIP2, VO1, VO2, TONSEL –0.1 5.5
DRVH1, DRVH2 –0.8 34
DRVH1, DRVH2 (wrt LLx) –0.1 5.5

Output voltage LL1, LL2 –1.8 28 V

PGOOD1, PGOOD2, DRVL1, DRVL2 –0.1 5.5
PGND1, PGND2 –0.1 0.1

TAOperating ambient temperature –40 85 °C

6.3 Thermal Information

TPS51124

THERMAL METRIC

R

θJA

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

4 Submit Documentation Feedback Copyright © 2005–2014, Texas Instruments Incorporated

Junction-to-ambient thermal resistance 42.9 °C/W

(1)

Product Folder Links: TPS51124

VQFN UNIT

24 PINS

www.ti.com

SLVS616C –NOVEMBER 2005–REVISED DECEMBER 2014

6.4 Electrical Characteristics

over operating free-air temperature range, V5IN = V5FILT = 5 V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SUPPLY CURRENT

I

V5FILT

I

V5INSDN

I

V5FILTSD

N

V5FILT supply current EN1 = EN2 = 5 V, VFB1 = VFB2 = 0.77 V, 350 700 μA

V5IN shutdown current V5IN current, no load, EN1 = EN2 = 0 V 1 μA
V5FILT shutdown current V5FILT current, no load, EN1 = EN2 = 0 V 1 μA

VFB VOLTAGE and DISCHARGE RESISTANCE

V

VFB

V

VFB

V

VFBSKIP

I

VFB

R

Dischg

VFB regulation voltage FB voltage, skip mode (f

VFB regulation voltage
tolerance

VFB regulation shift in 0.758-V target for resistor divider. See PWM Operation of
continuous conduction Detailed Description

VFB input current VFBx = 0.758 V, absolute value 0.02 0.1 μA
VO discharge resistance ENx = 0 V, VOx = 0.5 V, TA= 25°C 10 20 Ω

OUTPUT: N-CHANEEL MOSFET GATE DRIVERS

R

R

T

DRVH

DRVL

D

DRVH resistance

DRVL resistance

Dead time

INTERNAL BST DIODE

V

FBST

I

VBSTLK

Forward voltage V
VBST leakage current 0.1 1 μA

ON-TIME TIMER CONTROL AND INTERNAL SOFT START,

T

ON11

T

ON12

T

ON13

T

ON21

T

ON22

T

ON23

T

ON(MIN)

T

OFF(MIN)

T

ss

CH1, 240-kHz setting VO1 = 1.5 V,TONSEL = GND, LL1 = 12 V 440 500 560 ns
CH1, 300-kHz setting VO1 = 1.5 V, TONSEL = FLOAT, LL1 = 12 V 340 390 440 ns
CH1, 360-kHz setting VO1 = 1.5 V,TONSEL = V5FILT, LL1 = 12 V 265 305 345 ns
CH2, 300-kHz setting VO2 = 1.05 V, TONSEL = GND, LL2 = 12 V 235 270 305 ns
CH2, 360-kHz setting VO2 = 1.05 V, TONSEL = FLOAT, LL2 = 12 V 180 210 240 ns
CH2, 420-kHz setting VO2 = 1.05 V, TONSEL = V5FILT, LL2 = 12 V 120 150 180 ns
CH2 On time VO2 = 0.76 V, TONSEL = V5FILT, LL2 = 28 V 80 110 140 ns
CH1/CH2 Min. off time LL = –0.1 V, TA= 25°C, VFB = 0.7 V 435 ns

Internal SS time 0.85 1.2 1.40 ms

UVLO/LOGIC THRESHOLD

V

UV5VFILT

V

EN

I

EN

V5FILT UVLO threshold V

ENx threshold V

ENx input current Absolute value

V5FILT current, no load,
LL1=LL2=0.5V

/10) 764 mV

PWM

TA= 25°C, bandgap initial accuracy –0.9% 0.9%
TA= 0°C to 85°C
TA= –40°C to 85°C

Source, V
Sink, V

DRVHx-LLx

Source, V
Sink, V

DRVLx–PGNDx

(1)

(1)

(1)

VBSTx–DRVHx

= 0.5 V 5 7 Ω

= 0.5 V 1.5 2.5 Ω

V5IN–DRVLx

= 0.5 V 4 6 Ω

= 0.5 V 1 2.0 Ω

DRVHx-low (DRVHx = 1 V) to DRVLx-on
(DRVLx = 4 V), LL = –0.05 V,

DRVLx-low (DRVLx = 1 V) to DRVHx-on
(DRVHx = 4 V), LL = –0.05 V,

V5IN–VBSTx

, IF= 10 mA, TA= 25°C 0.7 0.8 0.9 V

VBST = 34 V, LL = 28 V, VOx = 5.5 V,
TA= 25°C

Internal soft start, time from ENx > 3 V to VFBx regulation value =
735 mV

Wake up 3.7 4.0 4.3
Hysteresis 0.2 0.3 0.4
Wake up 1.0 1.3 1.5
Hysteresis 0.2

(2)

TPS51124

–1.3% 1.3%
–1.6% 1.6%

758 mV

10 20 50 ns

30 40 60 ns

0.02 0.1 μA

(1) Specified by design. Not production tested.
(2) Ensured by design. Not production tested.

Copyright © 2005–2014, Texas Instruments Incorporated Submit Documentation Feedback 5

Product Folder Links: TPS51124

TPS51124

SLVS616C –NOVEMBER 2005–REVISED DECEMBER 2014

Electrical Characteristics (continued)

over operating free-air temperature range, V5IN = V5FILT = 5 V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(2)

Fast

V

TONSEL

I

TONSEL

TONSEL threshold Medium

TONSEL input current μA

CURRENT SENSE

I

TRIP

TC

V

OCLoff

V

ZC

V

Rtrip

TRIP source current VTRIPx < 0.3 V, TA= 25°C 9 10 11 μA
I

temperature On the basis of 25°C

ITRIP

TRIP

coeffficent C
OCP compensation offset –10 0 10 mV
Zero cross detection VPGNDx-LLx voltage, PGOODx = Hi

comparator offset
Current limit threshold V

setting range

POWERGOOD COMPARATOR

V

THPG

I

PGMAX

T

PGDEL

PG threshold

PG sink current PGOODx = 0.5 V 2.5 5.0 mA
PG delay Delay for PG in 400 510 620 μs

OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION

V

OVP

t

OVPDEL

V

UVP

t

UVPDEL

t

UVPEN

Output OVP trip threshold OVP detect 110% 115% 120%
Output OVP prop delay 1.5 μs
Output UVP trip threshold Hysteresis (recovery < 20 μs) 10%
Output UVP delay 20 32 40 μs
Output UVP enable delay After 1.7 × Tss, UVP protection engaged 1.4 2 2.4 ms

THERMAL SHUTDOWN

T

SDN

Thermal shutdown
threshold

(2)

(2)

Slow
TONSEL=0V, current out of the pin
TONSEL=5V, current in to the pin

(2)

(V

TRIPx-GND

V

TRIPx-GND

TRIPx-GND

– V

PGNDx-LLx

= 60 mV

) voltage,

voltage, all temperatures

(2)

(2)

(2)

(2)

PG in from lower (PGOODx goes hi) 92.5% 95% 97.5%
PG low hysteresis (PGOODx goes low) –5%
PG in from higher (PGOODx goes hi) 102.5

PG high hysteresis (PGOODx goes low) 5%

Shutdown temperature
Hysteresis

(2)

(2)

V5FIL

T –0.3

2

V5FILT V

–1.0

1
1

4200

0.5 mV

30 200 mV

105% 107.5%

%

160

10

www.ti.com

0.5

ppm/°

°C

6 Submit Documentation Feedback Copyright © 2005–2014, Texas Instruments Incorporated

Product Folder Links: TPS51124

0

100

200

300

400

500

0 5 10 15 20 25

f

SW

− SwitchingFrequency − kHz

CH1

CH2

VI− InputVoltage V−

TONSEL=GND

40

60

80

100

120

140

−50 0 50 100 150

V

OVP

V

UVP

− OVP/UVP Threshold − %

OVP

UVP

TJ − Junction Temperature − 5C

0

0.2

0.4

0.6

0.8

1

−50 0 50 100 150

I

V5INSDN

− Shutdown Current − Aµ

TJ − Junction Temperature − 5C

0

2

4

6

8

10

12

14

16

−50 0 50 100 150

I

TRIP

− Trip Source Current − Aµ

TJ − Junction Temperature − 5C

0

0.2

0.4

0.6

0.8

1

−50 0 50 100 150

I

V5FLTSDN

− Shutdown Current − Aµ

TJ − Junction Temperature − 5C

0

100

200

300

400

500

−50 0 50 100 150

I

V5FILT

− Supply Current − Aµ

TJ − Junction Temperature − 5C

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6.5 Typical Characteristics

TPS51124

SLVS616C –NOVEMBER 2005–REVISED DECEMBER 2014

Figure 1. V5FILT Supply Current vs Junction Temperature

Figure 3. V5IN Shutdown Current vs Junction Temperature

Figure 2. V5FILT Shutdown Current vs Junction

Temperature

Figure 4. Trip Source Current vs Junction Temperature

(1) The data of Figure 6–Figure 8 are measured from the Typical Application Circuit of Figure 18 and Table 2.

Copyright © 2005–2014, Texas Instruments Incorporated Submit Documentation Feedback 7

Figure 5. OVP/UVP Threshold vs Junction Temperature

Figure 6. Switching Frequency (Slow) vs Input Voltage

Product Folder Links: TPS51124

(1)

0

100

200

300

400

500

0.001 0.01 0.1 1 10

CH2

CH1

TONSEL = V5FILT

IO − Output Current − A

f

SW

− Switching Frequency − kHz

1

1.025

1.050

1.075

1.1

0.001 0.01 0.1 1 10

VI = 21 V

VI = 12 V

VI = 7 V

1.05 V
TONSEL = FLOAT

V

OUT1

− Output Voltage − V

I

OUT1

− Output Current − A

0

100

200

300

400

500

0.001 0.01 0.1 1 10

CH2

CH1

TONSEL = GND

IO − Output Current − A

f

SW

− Switching Frequency − kHz

0

100

200

300

400

500

0.001 0.01 0.1 1 10

CH2

CH1

TONSEL = FLOAT

IO − Output Current − A

f

SW

− Switching Frequency − kHz

0

100

200

300

400

500

0 5 10 15 20 25

CH1

CH2

TONSEL=FLOAT

f

SW

− SwitchingFrequency − kHz

VI− InputVoltage − V

0

100

200

300

400

500

0 5 10 15 20 25

CH1

CH2

TONSEL=V5FILT

f

SW

− SwitchingFrequency − kHz

VI− InputVoltage − V

TPS51124

SLVS616C –NOVEMBER 2005–REVISED DECEMBER 2014

Typical Characteristics (continued)

Figure 7. Switching Frequency (MED) vs Input Voltage Figure 8. Switching Frequency (Fast) vs Input Voltage

www.ti.com

Figure 9. Switching Frequency (Slow) vs Output Voltage

Figure 11. Switching Frequency (Fast) vs Output Voltage

(1) The data of Figure 9–Figure 12 are measured from the Typical Application Circuit of Figure 18 and Table 2.
8 Submit Documentation Feedback Copyright © 2005–2014, Texas Instruments Incorporated

(1)

Figure 10. Switching Frequency (MED) vs Output Voltage

Figure 12. 1.05-V Output Voltage vs Output Current

Product Folder Links: TPS51124

0

20

40

60

80

100

0.001 0.01 0.1 1 10

VI=21V

VI=7V

1.5V
TONSEL=FLOAT

I

OUT2

− OutputCurrent − A

VI=12V

− Efficiency − %

1.425

1.450

1.475

1.500

1.525

1.550

1.575

0 5 10 15 20 25

1.5 V
TONSEL = FLOAT

V

OUT2

− Output Voltage − V

VI − Input Voltage − V

IO = 0 A

IO = 5 A

0

20

40

60

80

100

0.001 0.01 0.1 1 10

VI=21V

VI=7V

1.05V
TONSEL=FLOAT

I

OUT1

− OutputCurrent − A

VI=12V

− Efficiency − %

1.425

1.450

1.475

1.500

1.525

1.550

1.575

0.001 0.01 0.1 1 10

VI = 21 V

VI = 12 V

VI = 7 V

1.5 V
TONSEL = FLOAT

V

OUT2

− Output Voltage − V

I

OUT2

− Output Current − A

1

1.025

1.050

1.075

1.1

0 5 10 15 20 25

1.05 V
TONSEL = FLOAT

V

OUT1

− Output Voltage − V

VI − Input Voltage − V

IO = 0 A

IO = 5 A

www.ti.com

Typical Characteristics (continued)

TPS51124

SLVS616C –NOVEMBER 2005–REVISED DECEMBER 2014

Figure 13. 1.5-V Output Voltage vs Output Current

(1)

Figure 14. 1.05-V Output Voltage vs Input Voltage

Figure 15. 1.5-V Output Voltage vs Input Voltage Figure 16. 1.05-V Efficiency vs Output Current

(1) The data of Figure 13–Figure 16 are measured from the Typical Application Circuit of Figure 18 and Table 2
(1) The data of Figure 17–Figure 22 are measured from the Typical Application Circuit of Figure 18 and Table 2

Copyright © 2005–2014, Texas Instruments Incorporated Submit Documentation Feedback 9

Figure 17. 1.5-V Efficiency vs Output Current

Product Folder Links: TPS51124

(1)