Texas Instruments TPS51116 Schematic [ru]

PGOOD

VREF

0.9 V

10 mA

VTT

0.9 V 2 A

TPS51116RGE

20 19

VBST DRVH LL DRVL

V5FILT

VLDOIN

VTTGND

VTTSNS

7 8

VTT

CS_GND

9 10

VDDQSET

VDDQSNS

13PGOOD

1211

S5S3

GND

MODE

VTTREF

COMP

NC NC

V5IN

PGND

22 2124 23

5V_IN

VDDQ

1.8 V 10 A

VIN

IRF7832

IRF7821

Ceramic

2y10 µF

Ceramic

0.033 µF

Ceramic

0.1 µF

1 µH

C6 SP−CAP 2y150 µF

C5 Ceramic 2y10 µF

C2 Ceramic 1 µF

C7 Ceramic 1 µF

R2 100 kΩ

5.1 kΩ

5.1 Ω

UDG−04153

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TPS51116

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Complete DDR, DDR2, DDR3, and LPDDR3 Memory Power Solution

Synchronous Buck Controller, 3-A LDO, Buffered Reference

Check for Samples: TPS51116

FEATURES

• Synchronous Buck Controller (VDDQ) – Wide-Input Voltage Range: 3.0-V to 28-V – D−CAP™ Mode with 100-ns Load Step

Response

– Current Mode Option Supports Ceramic

Output Capacitors – Supports Soft-Off in S4/S5 States – Current Sensing from R – 2.5-V (DDR), 1.8-V (DDR2), Adjustable to

1.5-V (DDR3) or 1.2-V (LPDDR3) or

Output Range 0.75-V to 3.0-V – Equipped with Powergood, Overvoltage

Protection and Undervoltage Protection

• 3-A LDO (VTT), Buffered Reference (VREF) – Capable to Sink and Source 3 A – LDO Input Available to Optimize Power

Losses

– Requires only 20-μF Ceramic Output

Capacitor – Buffered Low Noise 10-mA VREF Output – Accuracy ±20 mV for both VREF and VTT – Supports High-Z in S3 and Soft-Off in S4/S5 – Thermal Shutdown

DS(on)

or Resistor

SLUS609I –MAY 2004–REVISED JANUARY 2014

DESCRIPTION

The TPS51116 provides a complete power supply for DDR/SSTL-2, DDR2/SSTL-18, DDR3/SSTL-15, and LPDDR3 memory systems. It integrates a synchronous buck controller with a 3-A sink/source tracking linear regulator and buffered low noise reference. The TPS51116 offers the lowest total solution cost in systems where space is at a premium. The TPS51116 synchronous controller runs fixed 400-kHz, pseudo-constant frequency PWM with an adaptive on-time control that can be configured in D-CAP™ Mode for ease of use and fastest transient response or in current mode to support ceramic output capacitors. The 3-A sink/source LDO maintains fast transient response only requiring 20-μF (2 × 10 μF) of ceramic output capacitance. In addition, the LDO supply input is available externally to significantly reduce the total power losses. The TPS51116 supports all of the sleep state controls placing VTT at high-Z in S3 (suspend to RAM) and discharging VDDQ, VTT and VTTREF (soft-off) in S4/S5 (suspend to disk). TPS51116 has all of the protection features including thermal shutdown and is offered in both a 20-pin HTSSOP PowerPAD™ package and 24-pin 4×4 QFN.

APPLICATIONS

• DDR/DDR2/DDR3/LPDDR3 Memory Power Supplies

• SSTL-2, SSTL-18, SSTL-15 and HSTL Termination

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2D-CAP, PowerPAD are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

TPS51116

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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION

-40°C to 85°C

(1) All packaging options have Cu NIPDAU lead/ball finish.

ABSOLUTE MAXIMUM RATINGS

PACKAGE PINS ORDER

Plastic HTSSOP

PowerPAD (PWP)

Plastic QUAD Flat Pack TPS51116RGER 3000

(QFN)

(1)

ORDERABLE PART OUTPUT

TPS51116PWPRG4 Tape-and-reel 2000

(1)

NUMBER SUPPLY

TPS51116PWP Tube 70

TPS51116PWPR 20 Tape-and-reel 2000

TPS51116RGE Tube 90

24 tape-and-reel

TPS51116RGET 250

Large

Small

tape-and-reel

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MINIMUM

QUANTITY

over operating free-air temperature range unless otherwise noted

MIN MAX UNIT

VBST –0.3 36 VBST wrt LL –0.3 6

T T

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

Input voltage range V

Output voltage range LL –1.0 30 V

OUT

Operating ambient temperature range –40 85

Storage temperature –55 150

stg

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the network ground terminal unless otherwise noted.

CS, MODE, S3, S5, VTTSNS, VDDQSNS, V5IN, VLDOIN, VDDQSET, V5FILT

PGND, VTTGND, CS_GND –0.3 0.3 DRVH –1.0 36

COMP, DRVL, PGOOD, VTT, VTTREF –0.3 6

–0.3 6

°C

DISSIPATION RATINGS

PACKAGE TA= 25°C

20-pin PWP 2.53 25.3 1.01 24-pin RGE 2.20 22.0 0.88

TA< 25°C POWER RATING TA= 85°C POWER RATING

(W) (W)

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DERATING FACTOR ABOVE

(mW/°C)

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RECOMMENDED OPERATING CONDITIONS

MIN MAX UNIT

Supply voltage, V5IN, V5FILT 4.75 5.25 V

VBST, DRVH –0.1 34 LL –0.6 28 VLDOIN, VTT, VTTSNS, VDDQSNS –0.1 3.6

Voltage range V

Operating free-air temperature, T

VTTREF –0.1 1.8 PGND, VTTGND, CS_GND –0.1 0.1 S3, S5, MODE, VDDQSET, CS, COMP, PGOOD,

DRVL

–0.1 5.25

–40 85 °C

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TPS51116

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ELECTRICAL CHARACTERISTICS

over operating free-air temperature range, V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SUPPLY CURRENT

TA= 25°C, No load, VS3= VS5= 5 V,

V5IN1

V5IN2

V5IN3

V5INSDN

VLDOIN1

VLDOIN2

VLDOINSDN

Supply current 1, V5IN

Supply current 2, V5IN

Supply current 3, V5IN Shutdown current, V5IN

Supply current 1, VLDOIN TA= 25°C, No load, VS3= VS5= 5 V 1 10 Supply current 2, VLDOIN TA= 25°C, No load, VS3= 5 V, VS5= 0 V, 0.1 10 Standby current, VLDOIN TA= 25°C, No load, VS3= VS5= 0 V 0.1 1.0

VTTREF OUTPUT

VTTREF

VTTREFTOL

VTTREFSRC

VTTREFSNK

Output voltage, VTTREF V

Output voltage tolerance mV

Source current V Sink current V

VDDQ OUTPUT

VDDQ

VDDQSET

VDDQSNS

VDDQSET

VDDQDisch

VLDOINDisch

Output voltage, VDDQ V

VDDQSET regulation voltage 0°C ≤ TA≤ 85°C, Adjustable mode 740.2 750.0 759.8

Input impedance, VDDQSNS V

Input current, VDDQSET μA

Discharge current, VDDQ 10 40 mA

Discharge current, VLDOIN 700 mA

VTT OUTPUT

VTTSNS

Output voltage, VTT VS3= VS5= 5 V, V

(1)

COMP connected to capacitor TA= 25°C, No load, VS3= 0 V, VS5= 5 V,

(1)

COMP connected to capacitor TA= 25°C, No load, VS3= 0 V, VS5= 5 V,

(1)

TA= 25°C, No load, VS3= VS5= 0 V 0.1 1.0

-10 mA < I Tolerance to V

TA= 25°C, V 0°C ≤ TA≤ 85°C, V

-40°C ≤ TA≤ 85°C, V TA= 25°C, V 0°C ≤ TA≤ 85°C, V

-40°C ≤ TA≤ 85°C, V

-40°C ≤ TA≤ 85°C, Adjustable mode, No load

TA= 25°C, Adjustable mode 742.5 750.0 757.5 mV

-40°C ≤ TA≤ 85°C, Adjustable mode 738.0 750.0 762.0 V

Adjustable mode 460 V V VS3= VS5= 0 V, V

V VS3= VS5= 0 V, V

VS3= VS5= 5 V, V

= 5 V, VLDOIN is connected to VDDQ output (unless otherwise noted)

V5IN

0.8 2 mA

300 600

= 5 V

COMP

VDDQSNS VDDQSNS

(2)

VDDQSET VDDQSET

= 0 V

MODE

= 0.5 V

MODE

< 10 mA, V

VTTREF

VDDQSNS

< 10 mA, V

VTTREF

VDDQSNS

< 10 mA, V

VTTREF

VDDQSNS

< 10 mA, V

VTTREF

VDDQSNS

= 2.5 V, V = 2.5 V, V

VDDQSET

VDDQSNS

= 0 V -20 -40 -80

VTTREF

= 2.5 V 20 40 80

VTTREF

= 0 V, No load 2.465 2.500 2.535

VDDQSET

= 0 V, No load

VDDQSET

= 5 V, No load

VDDQSET

= 5V, No load

VDDQSET

= 2.5 V,

= 1.8 V,

= 1.5 V,

= 1.2 V,

= 0 V, No load

(2)

= 5V, No load

-20 20

-18 18

-15 15

–12 12

(2)

2.457 2.500 2.543

(2)

2.440 2.500 2.550

1.776 1.800 1.824

1.769 1.800 1.831

(2)

1.764 1.800 1.836

0.75 3.0

= 0 V 215 kΩ = 5 V 180

= 0.78 V, COMP = Open -0.04 = 0.78 V, COMP = 5 V -0.06

VDDQSNS

VLDOIN VLDOIN VLDOIN

= 0.5 V,

= V = V = V

VDDQSNS VDDQSNS VDDQSNS

= 2.5 V 1.25 = 1.8 V 0.9 V = 1.5 V 0.75

240 500

/2 V

VDDQSNS

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μA

(1) V5IN references to PWP packaged devices should be interpreted as V5FILT references to RGE packaged devices. (2) Specified by design. Not production tested.

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ELECTRICAL CHARACTERISTICS (continued)

over operating free-air temperature range, V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VTTTOL25

VTTTOL18

VTTTOL15

VTTTOL12

VTTOCLSRC

VTTOCLSNK

VTTLK

VTTBIAS

VTTSNSLK

VTTDisch

TRANSCONDUCTANCE AMPLIFIER

gm Gain TA= 25°C 240 300 360 μS I

COMPSNK

COMPSRC

COMPHI

COMPLO

VTT output voltage tolerance V to VTTREF |I

Source current limit, VTT

Sink current limit, VTT

Leakage current, VTT VS3= 0 V, VS5= 5 V, V Input bias current, VTTSNS VS3= 5 V, V Leakage current, VTTSNS VS3= 0 V, VS5= 5 V, V

Discharge current, VTT 10 17 mA

COMP maximum sink VS3= 0 V, VS5= 5 V, V current V

COMP maximum source VS3= 0 V, VS5= 5 V, V current V

COMP high clamp voltage 1.31 1.34 1.37

COMP low clamp voltage 1.18 1.21 1.24

= 5 V, VLDOIN is connected to VDDQ output (unless otherwise noted)

V5IN

VDDQSNS

VTT

VDDQSNS

VTT

VDDQSNS

VTT

VDDQSNS

VTT

VDDQSNS

VTT

VDDQSNS

VTT

VDDQSNS

VTT

VDDQSNS

VTT

VDDQSNS

VTT

VDDQSNS

VTT

VDDQSNS

VTT

VDDQSNS

VTT

VLDOIN

1.19 V, PGOOD = HI V

VLDOIN

1.31 V, PGOOD = HI V

VLDOIN

TA= 25°C, VS3= VS5= V V

VTT

VDDQSNS

VS3= 0 V, VS5= 5 V, V V

VDDQSNS

VS3= 0 V, VS5= 5 V, V V

VDDQSNS

= V

= V = V

= V

VLDOIN

VDDQSNS

VDDQSNS VDDQSNS

VDDQSNS

VTTSNS

= 0 A

| < 1.5 A

| < 3 A

= 0 A

| < 1 A

| < 2 A

= 0 A

| < 1 A

| < 2 A

= 0 A

| < 1 A

| < 1.5 A

= 0.5 V

= 2.7 V, V

= 2.3 V, V

= 2.3 V, VCS= 0 V

= 2.7 V, VCS= 0 V

= 2.5 V, VS3= VS5= 5 V,

= 1.8 V, VS3= VS5= 5 V,

= 1.5 V, VS3= VS5= 5 V,

= 1.2 V, VS3= VS5= 5 V,

= 2.5 V, V

= 2.5 V, V = 2.5 V, V

= 2.5 V, V

VTT

= V

VDDQSNS

VTT

VDDQSNS

VDDQSET

= 1.28 V

COMP

VDDQSET

= 1.28 V

COMP

VDDQSET

= V

VTT

VTTSNS

= 0 V 1.5 2.2 3.0

VTT

= V

VTT

VTTSNS

= V

VTT

VDDQ

= V

VDDQSNS

/2 -10 10

/2 -1 -0.1 1 μA

= V

VDDQSNS

/2 -1 1

= 0 V,

-20 20

-30 30 mV

-40 40

-20 20

-30 30 mV

-40 40

-20 20

-30 30 mV

-40 40

-20 20

-30 30 mV

-40 40

3.0 3.8 6.0

3.0 3.6 6.0

1.5 2.2 3.0

-13

μA

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ELECTRICAL CHARACTERISTICS (continued)

over operating free-air temperature range, V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DUTY CONTROL

ON0

ON(min)

OFF(min)

ZERO CURRENT COMPARATOR

OUTPUT DRIVERS

DRVH

DRVL

INTERNAL BST DIODE

FBST

VBSTLK

PROTECTIONS

OCL

TRIP

ITRIP

OCL(off)

R(trip)

POWERGOOD COMPARATOR

TVDDQPG

PG(max)

PG(del)

(3) Specified by design. Not production tested. (4) V5IN references to PWP packaged devices should be interpreted as V5FILT references to RGE packaged devices.

Operating on-time VIN= 12 V, V Startup on-time VIN= 12 V, V Minimum on-time TA= 25°C Minimum off-time TA= 25°C

Zero current comparator offset

DRVH resistance

DRVL resistance

Dead time ns

Forward voltage V VBST leakage current 0.1 1.0 μA

Current limit threshold mV

Current sense sink current μA

TRIP current temperature R coefficient of TA= 25°C

Overcurrent protection (V COMP offset VCS> 4.5 V

Current limit threshold setting range

VDDQ powergood threshold PG in from higher 102.5% 105.0% 107.5%

PGOOD sink current V PGOOD delay time Delay for PG in 80 130 200 μs

= 5 V, VLDOIN is connected to VDDQ output (unless otherwise noted)

V5IN

VDDQSET VDDQSNS

(3)

= 0 V 520

= 0 V 125

100 350

-6 0 6 mV

Source, I Sink, I Source, I Sink, I LL-low to DRVL-on DRVL-off to DRVH-on

V5IN-VBST

VBST

TA= 25°C

PGND-CS

= –100 mA 3 6

DRVH

= 100 mA 0.9 3

DRVH

= –100 mA 3 6

DRVL

= 100 mA 0.9 3

DRVL

(3)

10 20

, IF= 10 mA, TA= 25°C 0.7 0.8 0.9 V

= 34 V, VLL= 28 V, V

VDDQ

= 2.6 V,

, PGOOD = HI, VCS< 0.5 V 50 60 70

, PGOOD = LO, VCS< 0.5 V 20 30 40 TA= 25°C, VCS> 4.5 V, PGOOD = HI 9 10 11 TA= 25°C, VCS> 4.5 V, PGOOD = LO 4 5 6

sense scheme, On the basis

DS(on)

V5IN-CS

- V

(3) (4)

(3)

PGND-LL

(3)

), V

V5IN-CS

= 60 mV,

-5 0 5

30 150

4500 ppm/°C

PG in from lower 92.5% 95.0% 97.5%

PG hysteresis 5%

VTT

= 0 V, V

= 0.5 V 2.5 7.5 mA

PGOOD

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Ω

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ELECTRICAL CHARACTERISTICS (continued)

over operating free-air temperature range, V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

UNDERVOLTAGE LOCKOUT/LOGIC THRESHOLD

UVV5IN

THMODE

THVDDQSET

IHYST

INLEAK

INVDDQSET

UNDERVOLTAGE AND OVERVOLTAGE PROTECTION

OVP

OVPDEL

UVP

UVPDEL

UVPEN

THERMAL SHUTDOWN

SDN

V5IN UVLO threshold voltage

MODE threshold

VDDQSET threshold voltage

High-level input voltage S3, S5 2.2 Low-level input voltage S3, S5 0.3 Hysteresis voltage S3, S5 0.2 Logic input leakage current S3, S5, MODE -1 1 Input leakage/ bias current VDDQSET -1 1

VDDQ OVP trip threshold voltage

VDDQ OVP propagation

(5)

delay

Output UVP trip threshold

Output UVP propagation

(5)

delay Output UVP enable delay

Thermal SDN threshold

(5)

= 5 V, VLDOIN is connected to VDDQ output (unless otherwise noted)

V5IN

Wake up 3.7 4.0 4.3 Hysteresis 0.2 0.3 0.4 No discharge 4.7 Non-tracking discharge 0.1

2.5 V output 0.08 0.15 0.25 V

1.8 V output 3.5 4.0 4.5

OVP detect 110% 115% 120% Hysteresis 5%

UVP detect 70% Hysteresis 10%

Shutdown temperature 160 Hysteresis 10

SLUS609I –MAY 2004–REVISED JANUARY 2014

μA

1.5 μs

cycle

1007

°C

(5) Specified by design. Not production tested.

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DEVICE INFORMATION

TERMINAL FUNCTIONS

TERMINAL

NAME

COMP 8 6 I/O

CS 15 16 I/O voltage setting input for R

DRVH 19 21 O Switching (top) MOSFET gate drive output. DRVL 17 19 O Rectifying (bottom) MOSFET gate drive output. GND 5 3 - Signal ground. Connect to minus terminal of the VTT LDO output capacitor. CS_GND - 17 – Current sense comparator input (+) and ground for powergood circuit.

LL 18 20 I/O MODE 6 4 I Discharge mode setting pin. See VDDQ and VTT Discharge Control section.

NC No connect.

PGND 16 18 –

PGOOD 13 13 O S3 11 10 I S3 signal input.

S5 12 11 I S5 signal input. V5IN 14 15 I 5-V power supply input for internal circuits (PWP) and MOSFET gate drivers (PWP, RGE).

V5FILT - 14 I VBST 20 22 I/O Switching (top) MOSFET driver bootstrap voltage input.

VDDQSET 10 9 I VDDQ output voltage setting pin. See VDDQ Output Voltage Selection section.

VDDQSNS 9 8 I/O current sinking terminal for VDDQ Non-tracking discharge. Output voltage feedback input for

VLDOIN 1 23 I Power supply for the VTT LDO. VTT 2 24 O Power output for the VTT LDO. VTTGND 3 1 - Power ground output for the VTT LDO. VTTREF 7 5 O VTTREF buffered reference output.

VTTSNS 4 2 I

NO. I/O DESCRIPTION

PWP RGE

Output of the transconductance amplifier for phase compensation. Connect to V5IN to disable gm amplifier and use D-CAP™ mode.

Current sense comparator input (-) for resistor current sense scheme. Or overcurrent trip (RGE) through the voltage setting resistor.

Switching (top) MOSFET gate driver return. Current sense comparator input (-) for R current sense.

– 7 – – 12 –

Ground for rectifying (bottom) MOSFET gate driver (PWP, RGE). Also current sense comparator input(+) and ground for powergood circuit (PWP).

Powergood signal open drain output, In HIGH state when VDDQ output voltage is within the target range.

Filtered 5-V power supply input for internal circuits. Connect R-C network from V5IN to V5FILT.

VDDQ reference input for VTT and VTTREF. Power supply for the VTTREF. Discharge VDDQ output if VDDQSET pin is connected to V5IN or GND.

Voltage sense input for the VTT LDO. Connect to plus terminal of the VTT LDO output capacitor.

current sense scheme if connected to V5IN (PWP), V5FILT

DS(on)

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1 2 3 4 5 6 7 8 9 10

20 19 18 17 16 15 14 13 12 11

VLDOIN

VTT

VTTGND

VTTSNS

GND

MODE

VTTREF

COMP

VDDQSNS

VDDQSET

VBST DRVH LL DRVL PGND CS V5IN PGOOD S5 S3

PWP PACKAGE

(TOP VIEW)

NC VDDQSNS VDDQSET S3 S5 NC

7 8

9 10 11 12

RGE PACKAGE

(BOTTOM VIEW)

24 23 22 21 20 19

VTT

VLDOIN

VBST

DRVH

DRVL

1 2 3 4 5 6

18 17 16 15 14 13

VTTGND

VTTSNS

GND

MODE

VTTREF

COMP

PGND

CS_GND

V5IN

V5FILT

PGOOD

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FUNCTIONAL BLOCK DIAGRAM (PWP)

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FUNCTIONAL BLOCK DIAGRAM (RGE)

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TPS51116

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DETAILED DESCRIPTION

The TPS51116 is an integrated power management solution which combines a synchronous buck controller, a 10-mA buffered reference and a high-current sink/source low-dropout linear regulator (LDO) in a small 20-pin HTSSOP package or a 24-pin QFN package. Each of these rails generates VDDQ, VTTREF and VTT that required with DDR/DDR2/DDR3/LPDDR3 memory systems. The switch mode power supply (SMPS) portion employs external N-channel MOSFETs to support high current for DDR/DDR2/DDR3/LPDDR3 memory VDD/VDDQ. The preset output voltage is selectable from 2.5 V or 1.8 V. User-defined output voltage is also possible and can be adjustable from 0.75 V to 3 V. Input voltage range of the SMPS is 3 V to 28 V. The SMPS runs an adaptive on-time PWM operation at high-load condition and automatically reduces frequency to keep excellent efficiency down to several mA. Current sensing scheme uses either R MOSFET for a low-cost, loss-less solution, or an optional sense resistor placed in series to the rectifying MOSFET for more accurate current limit. The output of the switcher is sensed by VDDQSNS pin to generate one-half VDDQ for the 10-mA buffered reference (VTTREF) and the VTT active termination supply. The VTT LDO can source and sink up to 3-A peak current with only 20-μF (two 10-μF in parallel) ceramic output capacitors. VTTREF tracks VDDQ/2 within ±1% of VDDQ. VTT output tracks VTTREF within ±20 mV at no load condition while ±40 mV at full load. The LDO input can be separated from VDDQ and optionally connected to a lower voltage by using VLDOIN pin. This helps reducing power dissipation in sourcing phase. TheTPS51116 is fully compatible to JEDEC DDR/DDR2 specifications at S3/S5 sleep state (see Table 2). The part has two options of output discharge function when both VTT and VDDQ are disabled. The tracking discharge mode discharges VDDQ and VTT outputs through the internal LDO transistors and then VTT output tracks half of VDDQ voltage during discharge. The non-tracking discharge mode discharges outputs using internal discharge MOSFETs which are connected to VDDQSNS and VTT. The current capability of these discharge FETs are limited and discharge occurs more slowly than the tracking discharge. These discharge functions can be disabled by selecting non-discharge mode.

of the external rectifying

DS(on)

VDDQ SMPS, Dual PWM Operation Modes

The main control loop of the SMPS is designed as an adaptive on-time pulse width modulation (PWM) controller. It supports two control schemes which are a current mode and a proprietary D-CAP™ mode. D-CAP™ mode uses internal compensation circuit and is suitable for low external component count configuration with an appropriate amount of ESR at the output capacitor(s). Current mode control has more flexibility, using external compensation network, and can be used to achieve stable operation with very low ESR capacitor(s) such as ceramic or specialty polymer capacitors.

These control modes are selected by the COMP terminal connection. If the COMP pin is connected to V5IN, TPS51116 works in the D-CAP™ mode, otherwise it works in the current mode. VDDQ output voltage is monitored at a feedback point voltage. If VDDQSET is connected to V5IN or GND, this feedback point is the output of the internal resistor divider inside VDDQSNS pin. If an external resistor divider is connected to VDDQSET pin, VDDQSET pin itself becomes the feedback point (see VDDQ Output Voltage Selection section).

At the beginning of each cycle, the synchronous high-side MOSFET is turned on, or becomes ON state. This MOSFET is turned off, or becomes OFF state, after internal one shot timer expires. This one shot is determined by VINand V control (see PWM Frequency and Adaptive On-Time Control section). The MOSFET is turned on again when feedback information indicates insufficient output voltage and inductor current information indicates below the overcurrent limit. Repeating operation in this manner, the controller regulates the output voltage. The synchronous bottom or the rectifying MOSFET is turned on each OFF state to keep the conduction loss minimum. The rectifying MOSFET is turned off when inductor current information detects zero level. This enables seamless transition to the reduced frequency operation at light load condition so that high efficiency is kept over broad range of load current.

In the current mode control scheme, the transconductance amplifier generates a target current level corresponding to the voltage difference between the feedback point and the internal 750 mV reference. During the OFF state, the PWM comparator monitors the inductor current signal as well as this target current level, and when the inductor current signal comes lower than the target current level, the comparator provides SET signal to initiate the next ON state. The voltage feedback gain is adjustable outside the controller device to support various types of output MOSFETs and capacitors. In the D-CAP™ mode, the transconductance amplifier is disabled and the PWM comparator compares the feedback point voltage and the internal 750 mV reference during the OFF state. When the feedback point comes lower than the reference voltage, the comparator provides SET signal to initiate the next ON state.

to keep frequency fairly constant over input voltage range, hence it is called adaptive on-time

OUT

Product Folder Links: TPS51116

OUT(LL)

2 L f

(VIN* V

OUT

) V

OUT

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TPS51116

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SLUS609I –MAY 2004–REVISED JANUARY 2014

VDDQ SMPS, Light Load Condition

TPS51116 automatically reduces switching frequency at light load condition to maintain high efficiency. This reduction of frequency is achieved smoothly and without increase of V

ripple or load regulation. Detail

OUT

operation is described as follows. As the output current decreases from heavy load condition, the inductor current is also reduced and eventually comes to the point that its valley touches zero current, which is the boundary between continuous conduction and discontinuous conduction modes. The rectifying MOSFET is turned off when this zero inductor current is detected. As the load current further decreased, the converter runs in discontinuous conduction mode and it takes longer and longer to discharge the output capacitor to the level that requires next ON cycle. The ON-time is kept the same as that in the heavy load condition. In reverse, when the output current increase from light load to heavy load, switching frequency increases to the constant 400 kHz as the inductor current reaches to the continuous conduction. The transition load point to the light load operation I

OUT(LL)

(i.e. the

threshold between continuous and discontinuous conduction mode) can be calculated in Equation 1:

where

• f is the PWM switching frequency (400 kHz) (1)

Switching frequency versus output current in the light load condition is a function of L, f, VINand V decreases almost proportional to the output current from the I I

/10 and 4 kHz at I

OUT(LL)

/100.

OUT(LL)

given above. For example, it is 40 kHz at

OUT

, but it

Low-Side Driver

The low-side driver is designed to drive high-current, low-R represented by the internal resistance, which is 3 Ω for V5IN to DRVL and 0.9 Ω for DRVL to PGND. A deadtime to prevent shoot through is internally generated between high-side MOSFET off to low-side MOSFET on, and low-side MOSFET off to high-side MOSFET on. 5-V bias voltage is delivered from V5IN supply. The instantaneous drive current is supplied by an input capacitor connected between V5IN and GND. The average drive current is equal to the gate charge at VGS= 5 V times switching frequency. This gate drive current as well as the high-side gate drive current times 5 V makes the driving power which needs to be dissipated from TPS51116 package.

, N-channel MOSFET(s). The drive capability is

DS(on)

High-Side Driver

The high-side driver is designed to drive high-current, low on-resistance, N-channel MOSFET(s). When configured as a floating driver, 5-V bias voltage is delivered from V5IN supply. The average drive current is also calculated by the gate charge at VGS= 5V times switching frequency. The instantaneous drive current is supplied by the flying capacitor between VBST and LL pins. The drive capability is represented by the internal resistance, which is 3 Ω for VBST to DRVH and 0.9 Ω for DRVH to LL.

Current Sensing Scheme

In order to provide both good accuracy and cost effective solution, TPS51116 supports both of external resistor sensing and MOSFET R should be connected between the source terminal of the low-side MOSFET and PGND. CS pin is connected to the MOSFET source terminal node. The inductor current is monitored by the voltage between PGND pin and CS pin. For R

sensing scheme, CS pin should be connected to V5IN (PWP), or V5FILT (RGE) through the trip

DS(on)

voltage setting resistor, R voltage across the R

. The inductor current is monitored by the voltage between PGND pin and LL pin so that

TRIP

LL pin should be connected to the drain terminal of the low-side MOSFET. I slope to compensate the temperature dependency of the R current sensing node so that PGND should be connected to the proper current sensing device, i.e. the sense resistor or the source terminal of the low-side MOSFET.

sensing. For resistor sensing scheme, an appropriate current sensing resistor

DS(on)

. In this scheme, CS terminal sinks 10-μA I

TRIP

DS(on)

. In either scheme, PGND is used as the positive

current and the trip level is set to the

TRIP

has 4500ppm/°C temperature

TRIP

Product Folder Links: TPS51116

TPS51116

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PWM Frequency and Adaptive On-Time Control

TPS51116 includes an adaptive on-time control scheme and does not have a dedicated oscillator on board. However, the device runs with fixed 400-kHz pseudo-constant frequency by feed-forwarding the input and output voltage into the on-time one-shot timer. The on-time is controlled inverse proportional to the input voltage and proportional to the output voltage so that the duty ratio is kept as V

OUT/VIN

technically with the same cycle time. Although the TPS51116 does not have a pin connected to VIN, the input voltage is monitored at LL pin during the ON state. This helps pin count reduction to make the part compact without sacrificing its performance. In order to secure minimum ON-time during startup, feed-forward from the output voltage is enabled after the output becomes 750 mV or larger.

VDDQ Output Voltage Selection

TPS51116 can be used for both of DDR (V output voltage (0.75 V < V output voltage scheme for a DDR3 (V

< 3 V) by connecting VDDQSET pin as shown in Table 1. Use the adjustable

VDDQ

Table 1. VDDQSET and Output Voltages

VDDQSET VDDQ (V) VTTREF and VTT NOTE

GND 2.5 V V5IN 1.8 V

FB Resistors Adjustable V

= 2.5 V) and DDR2 (V

VDDQ

= 1.5 V) or LPDDR3 (V

= 1.8 V) power supply and adjustable

VDDQ

= 1.2 V) application.

VDDQ

/2 DDR

VDDQSNS

/2 DDR2

VDDQSNS

/2 0.75 V < V

VDDQSNS

VDDQ

< 3 V

(1)(2)

VTT Linear Regulator and VTTREF

TPS51116 integrates high performance low-dropout linear regulator that is capable of sourcing and sinking current up to 3 A. This VTT linear regulator employs ultimate fast response feedback loop so that small ceramic capacitors are enough to keep tracking the VTTREF within ±40 mV at all conditions including fast load transient. To achieve tight regulation with minimum effect of wiring resistance, a remote sensing terminal, VTTSNS, should be connected to the positive node of VTT output capacitor(s) as a separate trace from VTT pin. For stable operation, total capacitance of the VTT output terminal can be equal to or greater than 20 μF. It is recommended to attach two 10-μF ceramic capacitors in parallel to minimize the effect of ESR and ESL. If ESR of the output capacitor is greater than 2 mΩ, insert an RC filter between the output and the VTTSNS input to achieve loop stability. The RC filter time constant should be almost the same or slightly lower than the time constant made by the output capacitor and its ESR. VTTREF block consists of on-chip 1/2 divider, LPF and buffer. This regulator also has sink and source capability up to 10 mA. Bypass VTTREF to GND by a 0.033-μF ceramic capacitor for stable operation.

When VTT is not required in the design, following treatment is strongly recommended.

• Connect VLDOIN to VDDQSNS.

• Tie VTTSNS to VTT, and remove capacitors from VTT to float.

• Connect VTTGND and MODE to GND (Non-tracking discharge mode as shown in Table 3)

• Maintain a 0.033-µF capacitor connected at VTTREF.

• Pull down S3 to GND with 1 kΩ of resistance. A typical circuit for this application is shown in Figure 1

(1) V (2) Including DDR3 and LPDDR3

≥ 1.2 V when used as VLDOIN.

VDDQ

Product Folder Links: TPS51116

+ 32 hidden pages

Texas Instruments TPS51116 Schematic [ru]

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

DESCRIPTION

APPLICATIONS

ABSOLUTE MAXIMUM RATINGS

DISSIPATION RATINGS

RECOMMENDED OPERATING CONDITIONS

ELECTRICAL CHARACTERISTICS

DEVICE INFORMATION

DETAILED DESCRIPTION

VDDQ SMPS, Dual PWM Operation Modes

VDDQ SMPS, Light Load Condition

Low-Side Driver

High-Side Driver

Current Sensing Scheme

PWM Frequency and Adaptive On-Time Control

VDDQ Output Voltage Selection

VTT Linear Regulator and VTTREF