TEXAS INSTRUMENTS TPS40192, TPS40193 Technical data

1

2

3

4

10

9

8

7

HDRV

SW

BOOT

LDRV

ENABLE

FB

COMP

VDD

TPS40192/3

5 6BP5PGD

11

GND

UDG−06063

V

OUT

ON/OFF

External Logic

Supply

5V or Less,

or BP5

V

IN

V

OUT

TPS40192 , TPS40193

www.ti.com

SLUS719B – MARCH 2007 – REVISED SEPTEMBER 2007

4.5-V TO 18-V INPUT 10-PIN SYNCHRONOUS BUCK CONTROLLER WITH POWER GOOD

1

FEATURES CONTENTS

• Input Operating Voltage Range: 4.5 V to 18 V

• Up to 20-A Output Currents

• Supports Pre-Biased Outputs

• 0.5% 0.591-V Reference

• 600 kHz (TPS40192) and 300 kHz (TPS40193)

Switching Frequencies

• Three Selectable Thermally Compensated

Short Circuit Protection Levels

• Hiccup Restart from Faults

• Internal 5-V Regulator

• High and Low side FET RDS

Current

ON

Sensing

• 10-Pin 3 mm × 3 mm SON Package

• Internal 4-ms Soft-Start Time

• Thermal Shutdown Protection at 145 ° C

APPLICATIONS

• Cable Modem CPE

• Digital Set Top Box

• Graphics/Audio Cards

• Entry Level and Mid-Range Servers

Device Ratings 3
Electrical Characteristics 4
Typical Characteristics 6
Terminal Information 9
Application Information 11
Design Example 17
Additional References 27

DESCRIPTION

TPS40192 and TPS40193 are cost-optimized
synchronous buck controllers that operate from 4.5 V
to 18 V input. These controllers implement a
voltage-mode control architecture with the switching
frequency fixed at either 600 kHz (TPS40192) or 300
kHz (TPS40193). The higher switching frequency
facilitates the use of smaller inductor and output
capacitors, thereby providing a compact
power-supply solution. An adaptive anti-cross
conduction scheme is used to prevent shoot through
current in the power FETs.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SIMPLIFIED APPLICATION DIAGRAM

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

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TPS40192 , TPS40193

SLUS719B – MARCH 2007 – REVISED SEPTEMBER 2007

DESCRIPTION (continued)

Short circuit detection is done by sensing the voltage drop across the low-side MOSFET when it is on and
comparing it with a user selected threshold of 100 mV, 200 mV or 280 mV. The threshold is set with a single
external resistor connected from COMP to GND. This resistor is sensed at startup and the selected threshold is
latched. Pulse by pulse limiting (to prevent current runaway) is provided by sensing the voltage across the
high-side MOSFET when it is on and terminating the cycle when the voltage drop rises above a fixed threshold of
550 mV. When the controller senses an output short circuit, both MOSFETs are turned off and a timeout period
is observed before attempting to restart. This provides limited power dissipation in the event of a sustained fault.

ORDERING INFORMATION

T

J

-40 ° C to 85 ° C Plastic 10-Pin SON (DRC)

PACKAGE FREQUENCY (kHz) PART NUMBER

300

600

TAPE AND REEL

QUANTITY

250 TPS40193DRCT

3000 TPS40193DRCR

250 TPS40192DRCT

3000 TPS40192DRCR

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TPS40192 , TPS40193

SLUS719B – MARCH 2007 – REVISED SEPTEMBER 2007

DEVICE RATINGS
ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted

VDD, ENABLE – 0.3 to 20
SW – 5 to 25

Input voltage range BOOT, HDRV – 0.3 to 30 V

BOOT-SW, HDRV-SW (differential from BOOT or HDRV to SW) -0.3 to 6
COMP, FB, BP5, LDRV, PGD – 0.3 to 6

T

Operating junction temperature range – 40 to 150

J

T

Storage temperature – 55 to 150

stg

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(1)

TPS40192/TPS40193 UNIT

RECOMMENDED OPERATING CONDITIONS

MIN NOM MAX UNIT

V

Input voltage 4.5 18 V

VDD

T

Operating Junction temperature -40 125 ° C

J

PACKAGE DISSIPATION RATINGS

R

High-K Board

PACKAGE AIRFLOW (LFM)

0 (Natural Convection) 47.9 2.08 0.835

DRC 200 40.5 2.46 0.987

400 38.2 2.61 1.04

(1) Ratings based on JEDEC High Thermal Conductivity (High K) Board. For more information on the test method, see TI Technical Brief

SZZA017.

θ JA

( ° C/W) TA= 25 ° C TA= 85 ° C

(1)

Power Rating (W) Power Rating (W)

° C

ELECTROSTATIC DISCHARGE (ESD) PROTECTION

MIN TYP MAX UNIT

Human Body Model (HBM) 2500
Charged Device Model (CDM) 1500

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TPS40192 , TPS40193

SLUS719B – MARCH 2007 – REVISED SEPTEMBER 2007

ELECTRICAL CHARACTERISTICS

TJ= – 40 ° C to 85 ° C, V

REFERENCE

V

FB

INPUT SUPPLY

V

VDD

I

VDD

ON BOARD REGULATOR

V

5VBP

V

DO

I

SC

I

BP5

OSCILLATOR

f

SW

V

RMP

PWM

D

MAX

t

ON(min)

t

DEAD

SOFT-START

t

SS

t

SSDLY

t

REG

ERROR AMPLIFIER

GBWP Gain bandwidth product
A

OL

I

IB

I

EAOP

I

EAOM

SHORT CIRCUIT PROTECTION

t

PSS(min)

t

BLNK

t

OFF

V

ILIM

V

ILIMH

(1) Ensured by design. Not production tested.

Feedback voltage range mV

Input voltage range 4.5 18.0 V

Operating current

Output voltage V
Regulator dropout voltage V
Regulator current limit threshold 50
Average current 50

Switching frequency kHz

Ramp amplitude

Maximum duty cycle
Minimum controlled pulse

Output driver dead time

Soft-start time 3 4 6
Soft-start delay time 2 ms
Time to regulation 6

DC gain
Input bias current (current out of FB

pin)
Output source current V
Output sink current V

Minimum pulse during short circuit
Blanking time
Off-time between restart attempts 30 50 ms

Short circuit comparator threshold
voltage

Short circuit threshold voltage on
high-side MOSFET

= 12 Vdc, all parameters at zero power dissipation (unless otherwise noted)

VDD

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(1)

(1)

(1)

(1)

(1)

0 ° C ≤ TJ≤ 85 ° C 588 591 594

-40 ° C ≤ TJ≤ 85 ° C 585 591 594

V
V

= 3 V 2.5 4.0 mA

ENABLE

= 0.6 V 45 70 μ A

ENABLE

> 6 V, I

VDD

- V

VDD

BP5

≤ 10 mA 5.1 5.3 5.5 V

5VBP

, V

= 5 V, I

VDD

≤ 25 mA 350 550 mV

BP5

TPS40193 240 300 360
TPS40192 500 600 700

85%

(1)

HDRV off to LDRV on 50 ns
LDRV off to HDRV on 25

7 10 MHz

60 dB

= 0 V 1

FB

= 2 V 1

FB

(1)

60 90 120

R

COMP(GND)

R

COMP(GND)

R

COMP(GND)

= OPEN, TJ= 25 ° C 160 200 240
= 4 k Ω , TJ= 25 ° C 80 100 120
= 12 k Ω , TJ= 25 ° C 228 280 342

TJ= 25 ° C 400 550 650

1 V

250

mA

110

100 nA

mA

ns

mV

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ELECTRICAL CHARACTERISTICS (continued)

TJ= – 40 ° C to 85 ° C, V

OUTPUT DRIVERS

R

HDHI

R

HDLO

R

LDHI

R

LDLO

t

HRISE

t

HFALL

t

LRISE

t

LFALL

UVLO

V

UVLO

UVLO

SHUTDOWN

V

IH

V

IL

POWER GOOD

V

OV

V

UV

V

PG_HYST

R

PGD

I

PDGLK

BOOT DIODE

V

DFWD

THERMAL SHUTDOWN

T

JSD

T

JSDH

(2) Ensured by design. Not production tested.

High-side driver pull-up resistance V
High-side driver pull-down resistance V
Low-side driver pull-up resistance I
Low-side driver pull-down resistance I
High-side driver rise time
High-side driver fall time
Low-side driver rise time
Low-side driver fall time

Turn-on voltage 3.9 4.2 4.4 V
Hysteresis 700 800 900 mV

HYST

High-level input voltage, ENABLE 1.9 3.0
Low-level input votlage, ENABLE 0.6

Feedback voltage limit for powergood 650
Feedback voltage limit for powergood 525 mV
Powergood hysteresis voltage at FB pin 30
Pulldown resistance of PGD pin V
Leakage current V

Bootstrap diode forward voltage I

Junction shutdown temperature
Hysteresis

= 12 Vdc, all parameters at zero power dissipation (unless otherwise noted)

VDD

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(2)

TPS40192 , TPS40193

SLUS719B – MARCH 2007 – REVISED SEPTEMBER 2007

- V

BOOT
BOOT

LDRV

(2)

(2)

(2)

(2)

(2)

LDRV

C

LOAD

= 0 V 7 50 Ω

FB

= 0 V 7 12 μ A

FB

BOOT

= 4.5 V, I

SW

- V

= 4.5 V, I

SW

= -100 mA 2.5 5.0
= 100 mA 0.8 1.5

= 1 nF ns

= 5 mA 0.5 0.8 1.2 V

= -100 mA 3 6

HDRV

= 100 mA 1.5 3.0

HDRV

15 35
10 25
15 35
10 25

145

20

Ω

V

° C

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TJ − Junction Temperature − °C

V

FB

− Relative Reverefnce Voltage Change − %

−40 −25 −10 5 20 35 95 12550 65 80 110

−0.50

−0.45

−0.40

−0.20

−0.15

−0.05

−0.35

−0.30

−0.25

0.00

0.50

−0.10

−40 −25 −10 5 20 35 95 125

−4.5

−4.0

−3.5

−1.5

−1.0

−0.5

0.5

−3.0

−2.5

−2.0

0.0

50 65 80 110

f

SW

− Relative Oscillator Frequency Change − %

TJ − Junction Temperature − °C

I

VDD

− Shutdown Current − µA

TJ − Junction Temperature − °C

0

10

20

30

40

50

60

−40 −25 −10 5 20 35 9550 65 80 110 125

V

ENABLE

< 0.6 V

V

ENABLE

− Enable Threshold Voltage − V

TJ − Junction Temperature − °C

0

0.5

1.0

1.5

2.0

2.5

−40 −25 −10 5 20 35 95 12550 65 80 110

Turn On

Turn Off

TPS40192 , TPS40193

SLUS719B – MARCH 2007 – REVISED SEPTEMBER 2007

TYPICAL CHARACTERISTICS

RELATIVE REFERENCE FEEDBACK VOLTAGE RELATIVE OSCILLATOR FREQUENCY CHANGE

vs vs

JUNCTION TEMPERATURE JUNCTION TEMPERATURE

Figure 1. Figure 2.

SHUTDOWN INPUT CURRENT ENABLE THRESHOLD VOLTAGE

vs vs

JUNCTION TEMPERATURE JUNCTION TEMPERATURE

Figure 3. Figure 4.

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t

SS

− Soft start Time − ms

TJ − Junction Temperature − °C

3.75

3.80

3.85

3.90

3.95

4.00

4.05

−40 −25 −10 5 20 35 95 12550 65 80 110

−40 −25 −10 5 20 35 95 12550 65 80 110

0

50

150

200

250

350

400

100

300

V

ILIM

− Current Limit Threshold − mV

TJ − Junction Temperature − °C

R

COMP

= 4 kΩ

R

COMP

= OPEN

R

COMP

= 12 kΩ

0

100

300

400

600

700

800

500

200

−40 −25 −10 5 20 35 95 12550 65 80 110

V

ILIMH

− Current Limit Threshold − mV

TJ − Junction Temperature − °C

t

REG

− Regulation Time − ms

TJ − Junction Temperature − °C

4.4

5.3

5.7

6.1

6.3

5.5

4.7

−40 −25 −10 5 20 35 95 12550 65 80 110

4.9

5.1

5.5

5.9

TYPICAL CHARACTERISTICS (continued)

TPS40192 , TPS40193

SLUS719B – MARCH 2007 – REVISED SEPTEMBER 2007

SOFT START TIME LOW-SIDE MOSFET CURRENT LIMIT THRESHOLD

vs vs

JUNCTION TEMPERATURE JUNCTION TEMPERATURE

Figure 5. Figure 6.

HIGH-SIDE MOSFET CURRENT LIMIT THRESHOLD TOTAL TIME TO REGULATION

vs vs

JUNCTION TEMPERATURE JUNCTION TEMPERATURE

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Figure 7. Figure 8.

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4 6 8 10 12 14 16 18

0

10

40

70

80

100

60

30

20

90

50

I

VDD

− Supply Current − µA

V

VDD

− Input Voltage − V

V

ENABLE

< 0.6 V

V

OV

, V

UV

− Powergood Threshold Voltage − mV

TJ − Junction Temperature − °C

560

580

540

520

500

660

680

640

620

600

−40 −25 −10 5 20 35 95 12550 65 80 110

Overvoltage

Undervoltage

0.4 0.6 0.8 1.0 1.2 1.4 1.6

0

0.5

3.0

3.5

4.5

1.5

1.0

5.0

2.0

2.5

4.0

1-D - Freewheel Time - ms

I

OC

- Relative Overcurrent Trip Point - A

TPS40192 , TPS40193

SLUS719B – MARCH 2007 – REVISED SEPTEMBER 2007

TYPICAL CHARACTERISTICS (continued)

POWERGOOD THRESHOLD VOLTAGE SHUTDOWN CURRENT

vs vs

JUNCTION TEMPERATURE INPUT VOLTAGE

Figure 9. Figure 10.

RELATIVE OVERCURRENT TRIP POINT

vs

FREEWHEEL TIME

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Figure 11.

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DRC PACKAGE

(TOP VIEW)

PGD5VDD4COMP3FB2ENABLE

1

6 7 8 9 10

BP5 LDRV BOOT SW HDRV

TPS40192
TPS40193

TPS40192 , TPS40193

SLUS719B – MARCH 2007 – REVISED SEPTEMBER 2007

DEVICE INFORMATION

Table 1. TERMINAL FUNCTIONS

TERMINAL

NAME NO.

BOOT 8 I

BP5 6 O 25nC or greater. Low power, low noise loads may be connected here if desired. The sum of the external

COMP 3 O Output of the error amplifier.

ENABLE 1 I controller on. A weak internal pull-up holds this pin high so that the pin may be left floating if this function is

FB 2 I
GND (11) - Thermal pad ground connection. Common reference for the device. Connect to the system GND.

HDRV 10 O Bootstrapped output for driving the gate of the high side N channel FET.
LDRV 7 O Output to the rectifier MOSFET gate
PGD 5 O Open drain power good output

SW 9 I
VDD 4 I Power input to the controller

I/O DESCRIPTION

Gate drive voltage for the high-side N-channel MOSFET. A capacitor 100 nF typical must be connected
between this pin and SW.

Output bypass for the internal regulator. Connect at least 1 μ F capacitor from this pin to GND. Larger
capacitors, up to 4.7 μ F will improve noise performance when using a low side FET with a gate charge of

load and the gate drive requirements must not exceed 50 mA. This regulator is turned off when ENABLE is
pulled low.

Logic level input which starts or stops the controller from an external user command. A high-level turns the
not used.

Inverting input to the error amplifier. In normal operation the voltage on this pin is equal to the internal
reference voltage (591 mV typical)

Sense line for the adaptive anti-cross conduction circuitry. Serves as common connection for the flying high
side MOSFET driver

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ENABLE 1

VDD

4

BP5

6

COMP 3

FB

2

GND

PP

5 V

Regulator

4.2 V

+

5 V

UVLO

+

Error

Amplifier

591 mV

SS

+

Fault

Controller

Soft Start

Ramp

Generator

PWM Logic

and

Anti-Cross

Conduction

+

VDD - 0.5 V

Oscillator

Short Circuit

Threshold

Selector

SD

UVLO

UVLO

SS

SD

FAULT

UVLO

+

CLK

10CLK

8

7

9

5

ENABLE

HDRV

SW

LDRV

PGD

5 V

Powergood

Control

FB

SD

FAULT

5 V

SC Threshold Latch

SC: -110 mV, -200 mV, or -280 mV

750 kW

VDD

SC

SD

+

FAULT

OCL

OCH

UDG-06064

TPS40192 , TPS40193

SLUS719B – MARCH 2007 – REVISED SEPTEMBER 2007

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TPS40192 , TPS40193

SLUS719B – MARCH 2007 – REVISED SEPTEMBER 2007

APPLICATION INFORMATION

Introduction

The TPS40192 and TPS40193 are cost optimized controllers providing all the necessary features to construct a
high performance DC/DC converter while keeping costs to a minimum. Support for pre-biased outputs eliminates
concerns about damaging sensitive loads during startup. Strong gate drivers for the high side and rectifier
N-channel MOSFETs decrease switching losses for increased efficiency. Adaptive gate drive timing prevents
shoot through and minimizes body diode conduction in the rectifier MOSFET, also increasing efficiency.
Selectable short circuit protection thresholds and hiccup recovery from a short circuit increase design flexibility
and minimize power dissipation in the event of a prolonged output fault. A dedicated enable pin (ENABLE) allows
the converter to be placed in a very low quiescent current shutdown mode. Internally fixed switching frequency
and soft-start time reduce external component count, simplifying design and layout, as well as reducing footprint
and cost. The 3 mm × 3 mm package size also contributes to a reduced overall converter footprint.

Voltage Reference

The band gap cell is designed with a trimmed 591 mV output. The 0.5% tolerance on the reference voltage
allows the user to design a very accurate power-supply.

Oscillator

The TPS40192 has a fixed internal switching frequency of 600 kHz while the TPS40193 operates at 300 kHz.

UVLO

When the input voltage is below the UVLO threshold, the device holds all gate drive outputs in the low (OFF)
state. When the input rises above the UVLO threshold, and the ENABLE pin is above the turn ON threshold, the
oscillator begins to operate and the start-up sequence is allowed to begin. The UVLO level is internally fixed at

4.2 V.

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4

1

5

To
Enable
Chip

VDD

ENABLE

GND

1.5 MΩ

200 kΩ

1 kΩ

1 kΩ

300 kΩ

200 Ω

UDG−05061

TPS40192 , TPS40193

SLUS719B – MARCH 2007 – REVISED SEPTEMBER 2007

Enable Functionality

The TPS40192 and TPS40193 have a dedicated ENABLE pin. This simplifies user level interface design since
no multiplexed functions exist. Another benefit is a true low power shutdown mode of operation. When the
ENABLE pin is pulled to GND, all unnecessary functions, including the BP5 regulator, are turned off, reducing the
device IDD current to 45-uA. A functionally equivalent circuit of the enable circuitry shown in Figure 12 .

Figure 12. TPS40192 ENABLE Pin Internal Circuitry

If the ENABLE pin is left floating, the chip starts automatically. The pin must be pulled to less than 600 mV to
guarantee that the TPS40192/3 is in shutdown mode. Note that the ENABLE pin is relatively high impedance. In
some situations, there could be enough noise nearby to cause the ENABLE pin to swing below the 600 mV
threshold and give erroneous shutdown commands to the rest of the device. There are two solutions to this
problem should it arise.

1. Place a capacitor from ENABLE to GND. A side effect of this is to delay the start of the converter while the
capacitor charges past the enable threshold

2. Place a resistor from VDD to ENABLE. This causes more current to flow in the shutdown mode, but does not
delay converter startup. If a resistor is used, the total current into the ENABLE pin should be limited to no
more than 500 μ A.

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