TEXAS INSTRUMENTS TPS40100 Technical data

TPS40100

www.ti.com

MIDRANGE INPUT SYNCHRONOUS BUCK CONTROLLER

WITH ADVANCED SEQUENCING AND OUTPUT MARGINING

FEATURES APPLICATIONS

• Operation over 4.5 V to 18 V Input Range

• Adjustable Frequency (Between 100 kHz and

600 kHz) Current Feedback Control

• Output Voltage Range From 0.7 V to 5.5 V

• Simultaneous, Ratiometric and Sequential

Startup Sequencing

• Adaptive Gate Drive

• Remote Sensing (Via Separate GND/PGND)

• Internal Gate Drivers for N-channel MOSFETs

• Internal 5-V Regulator

• 24-Pin QFN Package

• Thermal Shutdown

• Programmable Overcurrent Protection

• Power Good Indicator

• 1%, 690-mV Reference

• Output Margining, 3% and 5%

• Programmable UVLO (with Programmable

Hysteresis)

• Frequency Synchronization

• Servers

• Networking Equipment

• Cable Modems and Routers

• XDSL Modems and Routers

• Set-Top Boxes

• Telecommunications Equipment

• Power Supply Modules

DESCRIPTION

The TPS40100 is a mid voltage, wide-input (between

4.5 V and 18 V), synchronous, step-down controller.
The TPS40100 offers programmable closed loop
soft-start, programmable UVLO (with programmable
hysteresis), programmable inductor sensed current
limit and can be synchronized to other timebases.
The TPS40100 incorporates MOSFET gate drivers
for external N-channel high-side and synchronous
rectifier (SR) MOSFET. Gate drive logic incorporates
adaptive anti-cross conduction circuitry for improved
efficiency, reducing both cross conduction and diode
conduction in the rectifier MOSFET. The externally
programmable current limit provides a hiccup
overcurrent recovery characteristic.

SLUS601–MAY 2005

TYPICAL APPLICATION

V

24 2223 21 20 19

PG

SS

VO

GM

VDD

ISNS

HDRV

5VBP

LDRV

PGND

SW

BST

18

17

16

15

14

13

COMP

1

2

3

V

V

IN

TRKIN

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

4

5

6

MGU

MGD

FB

TRKOUT

TRKIN

UVLO

ILIM

7 98 10 11 12

RT

TPS40100

BIAS

SYNC

GND

IN

UDG−04137

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Copyright © 2005, Texas Instruments Incorporated

www.ti.com

TPS40100

SLUS601–MAY 2005

ORDERING INFORMATION

T

A

-40°C to 85°C QFN

PACKAGE PART NUMBER

TPS40100RGER

TPS40100RGET

(1) The QFN package (RGE) is available taped and reeled only. Use

large reel device type R (TPS40100RGER) to order quantities of
3,000 per reel. Use small reel device type T (TPS40100RGET) to
order quantities of 250 per reel.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted

VDD -0.3to20

5VBP, BIAS, FB, ILIM, ISNS, LDRV, MGU, MGD, PG, SS,
SYNC, UVLO, VO

BST to SW, HDRV to SW

V

Input voltage range V

IN

SW -1.5 to V

SW (transient) < 100 ns -6 to 30

TRKIN -0.3to20

GNDtoPGND -0.3to0.3

TRKOUT -0.3 to 8.0

HDRV, LDRV (RMS) 0.5

HDRV, LDRV (peak) 2.0

FB, COMP, TRKOUT 10 to -10 mA

SS 20 to -20

I

Input current range PG 20

IN

GM 1mA

RT 10

V5BP 50

RT source 100 µA

T

T

Operating junction temperature range –40 to 125

J

Storage temperature –55 to 150

stg

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) BST to SW and HDRV to SW are relative measurements. BST and HDRV can be this amount of voltage above or below the voltage at

SW.

(3) V5BP current includes gate drive current requirements. Observe maximum TJrating for the device.

(2)

(1)

(1)

TPS40100 UNIT

-0.3 to 6

-0.3 to 6.0

VIN

A

(3)

°C

2

TPS40100

www.ti.com

SLUS601–MAY 2005

ELECTRICAL CHARACTERISTICS

-40°C ≤ TA=TJ≤ 85°C, V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

INPUT VOLTAGE

V

VDD

OPERATING CURRENT

I

DD

I

SD

5VPB

OSCILLATOR/RAMP GENERATOR

f

SW

V

RAMP

t

OFF

D

MIN

t

MIN

V

VLY

FREQUENCY SYNCHRONIZATION

V

IH

V

IL

I

SYNC

t

SYNC

t

SYNC_SH

SOFT-START AND FAULT IDLE

I

SS

I

SS_SINK

V

SSC

V

SSD

V

SSOS

ERROR AMPLIFIER

GBWP Gain bandwidth product

AVOL Open loop 60 80 dB

I

BIAS

I

OH

I

OL

FEEDBACK REFERENCE

V

FB

(1) Ensured by design. Not production tested.
(2) To meet set up time requirements for the synchronization circuit, a negative logic pulse must be greater than 100 ns wide.

Operating range 4.5 18.0 V

Quiescent current VFB> 0.8 V, 0% duty cycle 1.3 1.8 2.5 mA

Shutdown current V

Internal regulator V

Programmable oscillator frequency 100 600

Oscillator frequency accuracy 250 275 300

Ramp amplitude

Fixed off-time 100 150 ns

Minimum duty cycle 0%

Minimum controllable pulse width

Valley voltage

High-level input voltage 2

Low-level input voltage 0.8

Input current, SYNC V

Mimimum pulse width, SYNC 50

Minimum set-up/hold time, SYNC

Soft-start source (charge) current 13 20 25

Soft-start sink (discharge) current 3.4 5.0 6.6

Soft-start completed voltage 3.25 3.40 3.75

Soft-start discharged voltage 0.15 0.20 0.25

Retry interval time to SS time ratio

Offset from SS to error amplifier 300 500 800 mV

Input bias current, FB 50 200 nA

High-level output current 23

Low-level output current 23

Slew rate

Feedback voltage reference mV

=12V,RRT= 182 kΩ,RGM= 232 kΩ,R

VDD

(1)

(1)

(1)

(2)

(1)

(1)

(1)

= 121 kΩ (unless otherwise noted)

ILIM

< 1 V 500 µA

UVLO

7V≤ V

4.5 V ≤ V

4.5 V ≤ V

-40°C ≤ TA=TJ≤ 125°C

≤ 18 V, 0 mA ≤ I

VDD

< 7 V, 0 mA ≤ I

VDD

<18V,

VDD

≤ 30 mA 4.7 5.0 5.3

LOAD

≤ 30 mA 4.3 5.0 5.3

LOAD

0.5 V

C

= 4.7 nF, -40°C ≤ TA=TJ≤ 125°C 175 ns

LOAD

1.0 1.6 2.0 V

= 2.5 V 4.0 5.5 10.0 µA

SYNC

100

16

3.5 5.0 MHz

2.1 V/µs

TA=25°C 686 690 694

-40°C < TA=TJ≤ 125°C 683 697

kHz

P-P

V

ns

µA

V

mA

3

www.ti.com

TPS40100

SLUS601–MAY 2005

ELECTRICAL CHARACTERISTICS (continued)

-40°C ≤ TA=TJ≤ 85°C, V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VOLTAGE MARGINING

V

FBMGU

I

MGUP

V

FBMGD

I

MGDN

t

MGDLY

t

MGTRAN

CURRENT SENSE AMPLIFIER

gm

CSA

TC

GM

V

GMLIN

I

ISNS

V

GMCM

CURRENT LIMIT

V

ILIM

t

ILIMDLY

DRIVER SPECIFICATIONS

t

RHDRV

t

FHDRV

I

HDRVSRPKS

I

HDRVSRMIL

I

HSDVSNPK

I

HDRVSNMIL

R

HDRVUP

R

HDRVDN

t

RLDRV

t

FLDRV

I

LDRVSRPK

I

LDRVSNMIL

I

LSDVSNPK

R

LDRVUP

R

LDRVDN

I

SWLEAK

POWERGOOD

V

LPGD

t

PGD

V

LPGDNP

V

OV

V

UV

(3) Margining delay time is the time delay from an assertion of a margining command until the output voltage begins to transition to the

margined voltage.

(4) Ensured by design. Not production tested.

Feedback voltage margin 5% up V

Feedback voltage margin 3% up 2 V ≤ V

Margin-up bias current 60 80 100 µA

Feedback voltage margin 5% down V

Feedback voltage margin 3% down 2 V ≤ V

Margin-down bias current 60 80 100 µA

Margining delay time

Margining transition time 1.5 7.0

Current sense amplifier gain TJ=25°C 300 333 365 µS

Amplifier gain temperature coefficient -2000 ppm/°C

Gm linear range voltage TJ=25°C -50 50 mV

Bias current at ISNS pin VVO=V

Input voltage common mode V

ILIM pin voltage to trip overcurrent 1.44 1.48 1.52 V

Current limit comparator propagation delay HDRV transition from on to off 70 140 ns

HIgh-side driver rise time

HIgh-side driver fall time

HIgh-side driver peak source current

HIgh-side driver source current at 2.5 V

HIgh-side driver peak sink current

High-side driver sink current at 2.5 V

HIgh-side driver pullup resistance I

HIgh-side driver pulldown resistance I

Low-side driver rise time

Low-side driver fall time

Low-side driver peak source current

Low-side driver source current at 2.5 V

Low-side driver peak sink current

Low-side driver sink current at 2.5 V

Low-side driver pullup resistance I

Low-side driver pulldown resistance I

Leakage current from SW pin -1 1 µA

Powergood low voltage I

Powergood delay time 15 25 35 µs

Powergood low voltage , no device power 1.00 1.25 V

Power good overvoltage threshold, V

Power good undervoltage threshold, V

=12V,RRT= 182 kΩ,RGM= 232 kΩ,R

VDD

MGU

MGD

(3)

4.5 V ≤ VIN≤ 5.5 V 0 3.6

(4)

(4)

(4)

(4)

(4)

(4)

(4)

(4)

(4)

(4)

(4)

FB

FB

C

LOAD

C

LOAD

(4)

V

HDRV-VSW

V

HDRV-VSW

HDRV

HDRV

C

LOAD

C

LOAD

V

LDRV

V

LDRV

LDRV

LDRV

PGD

V

VDD

5-V supply

= 121 kΩ (unless otherwise noted)

ILIM

≤ 500 mV 715 725 735

≤ 3 V 700 711 720

MGU

≤ 500 mV 645 655 665

≤ 3 V 660 669 680

MGD

12 30

= 3.3 V 250 nA

ISNS

06

= 4.7 nF 57

= 4.7 nF 47

800

= 2.5 V 700

1.3

= 2.5 V 1.2

= 300 mA 2.4 4.0

= 300 mA 1.0 1.8

= 4.7 nF 57

= 4.7 nF 47

800

= 2.5 V 700

1.3

= 2.5 V 1.2

= 300 mA 2.0 4.0

= 300 mA 0.8 1.5

= 2 mA 30 100 mV

= OPEN, 10-kΩ pullup to external

765

615

mV

mA

ms

ns

mA

A

Ω

ns

mA

A

Ω

mV

4

TPS40100

www.ti.com

ELECTRICAL CHARACTERISTICS (continued)

-40°C ≤ TA=TJ≤ 85°C, V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

TRACKING AMPLIFIER

V

TRKOS

V

TRKCM

V

TRK

V

HTKROUT

V

LTKROUT

I

SRCTRKOUT

I

SNKTRKOUT

V

TRKDIF

GBWP

AVOL

PROGRAMMABLE UVLO

V

UVLO

I

UVLO

INTERNALLY FIXED UVLO

V

UVLOFON

V

UVLOFOFF

V

UVLOHYST

THERMAL SHUTDOWN

T

SD

T

SDHYST

Tracking amplifier input offset voltage mV

Input common mode, active range 0 6

Tracking amplifier voltage range

High-level output voltage, TRKOUT

Low-level output voltage, TRKOUT 0 0.5

Source current, TRKOUT 0.65 2.00

Sink current, TRKOUT 12

Differential voltage from TRKIN to VO 18 V

Tracking amplifier gain bandwidth product

TRK

Tracking amplifier open loop DC gain

TRK

Undervoltage lockout threshold 1.285 1.332 1.378 V

Hysteresis current 9.0 10.0 10.8 µA

Fixed UVLO turn-on voltage at VDD pin -40°C ≤ TA< 125°C 3.850 4.150 4.425

Fixed UVLO turn-off voltage at VDD pin 3.75 4.06 4.35

UVLO hysteresis at VDD pin 85 mV

Thermal shutdown temerature

Hysteresis

=12V,RRT= 182 kΩ,RGM= 232 kΩ,R

VDD

(6)

(6)

(6)

(6)

V

TRKOS=VTRKIN-VO;VVO

V

TRKOS=VTRKIN-VO

4.5 V ≤ V

5V<V

V

VDD

V

VDD

SLUS601–MAY 2005

= 121 kΩ (unless otherwise noted)

ILIM

≤ 2V 7 25 40

;2V<VVO≤ 6 V -5 25 40

≤ 5.5 V 0 3.6

VDD

VDD

≤ 18 V

(5)

06

= 12 V 5.0 6.5 8.0

= 4.5 V 3.2 3.6

1MHz

60 dB

130 165

25

V

mA

V

°C

(5) Amplifier can track to the lesser of 6 V or (VDD× 0.95)
(6) Ensured by design. Not production tested.

DEVICE INFORMATION

MGU

MGD

SYNC

PG

VO

ISNS

24

23

22

21

20

19

RGE PACKAGE

(BOTTOM VIEW)

COMPFBTRKOUT

TRKIN

UVLO

123456

18 17 16 15 14 13

VDD

SW

BST

HDRV

5VBP

ILIM

7

8

9

10

11

12

LDRV

RT

BIAS

GND

SS

GM

PGND

5

www.ti.com

TPS40100

SLUS601–MAY 2005

DEVICE INFORMATION (continued)

TERMINAL FUNCTIONS

TERMINAL

NAME NO.

5VBP 14 O pin to PGND. Power for external circuitry may be drawn from this pin. The total gate drive

BIAS 8 O

BST 15 I connected from 5VBP (A) to BST(K). A schottky diode is recommended for this purpose. A

COMP 1 O

FB 2 I

GM 11 I Connect a resistor from this pin to GND to set the gain of the current sense amplifier.

GND 9 -

HDRV 16 O Floating gate drive for the high side N-channel MOSFET.

ILIM 6 O connected from this pin to GND. When this voltage reaches 1.48 V, an overcurrent condition

ISNS 19 I

LDRV 13 O Gate drive for the N-channel synchronous rectifier.

MGD 23 I 10 kΩ, the output voltage is decreased by 5%. The 3% margin down at the output voltage is

MGU 24 I kΩ, the output voltage is increased by 5%. The 3% margin up at the output voltage is

PG 21 O FB pin is more than 10% higher or lower than 690 mV, a UVLO condition exists, soft-start is

PGND 12 - Power ground for internal drivers

RT 7 I A resistor connected from this pin to GND sets operating frequency.

SS 10 I

SW 17 I

SYNC 22 I synchronize the oscillator frequency to an external master clock. This pin may be left floating

TRKIN 4 I tracks TRKIN voltage with a small controlled offset (typically 25 mV) when the tracking

TRKOUT 3 O the equivalent impedance at the FB node. The diode should be a low leakage type to

UVLO 5 I

VDD 18 I Supply voltage for the device.

VO 20 I

I/O DESCRIPTION

Output of an internal 5-V regulator. A 1-µF bypass capacitor should be connected from this

current and external current draw should not cause the device to exceed thermal capabilities

The bypassed supply for internal device circuitry. Connect a 0.1-µF or greater ceramic
capacitor from this pin to GND.

Gate drive voltage for the high-side N-channel MOSFET. An external diode must be

capacitor must be connected from this pin to the SW pin.

Output of the error amplifier. A feedback network is connected from this pin to the FB pin for
control loop compensation.

Inverting input to the error amplifier. In normal operation the voltage on this pin is equal to
the internal reference voltage (approximately 690 mV).

Low power or signal ground for the device. All signal level circuits should be referenced to
this pin unless otherwise noted.

Current limit pin used to set the overcurrent threshold and transient ride out time. An internal
current source that is proportional to the inductor current sets a voltage on a resistor

is declared by the device. Adding a capacitor in parallel with the resistor to GND sets a time
delay that can be used to help avoid nuisance trips.

Input from the inductor DCR sensing network. This input signal is one of the inputs to the
current sense amplifier for current feedback control and overcurrent protection

Margin down pin used for load stress test. When this pin is pulled to GND through less than

accommodated when this pin is connected to GND through a 30-kΩ resistor.

Margin up pin used for load stress test. When this pin is pulled to GND through less than 10

accommodated when this pin is connected to GND through a 30-kΩ resistor.

Open drain power good output for the device. This pin is pulled low when the voltage at the

active, tracking is active, an overcurrent condition exists or the die is over temperature.

Soft-start programming pin. A capacitor connected from this pin to ground programs the
soft-start time. This pin is also used as a time out function during an overcurrent event.

Connected to the switched node of the converter. This pin is the return line for the flying high
side driver.

Rising edge triggered synchronization input for the device. This pin can be used to

or grounded if the function is not used.

Control input allowing simultaneous startup of multiple controllers. The converter output

amplifier is used. See application secttion for more information.

Output of the tracking amplifier. If the tracking feature is used, this pin should be connected
to FB pin through a resistor in series with a diode. The resistor value can be calculated from

minimize errors due to diode reverse current. For further information on compensation of the
tracking amplifier refer to the application information

Provides for programming the undervoltage lockout level and serves as a shutdown input for
the device.

Output voltage. This is the reference input to the current sense amplifier for current mode
control and overcurrent protection.

6

TPS40100

www.ti.com

COMP

FB

MGU

MGD

ISNS

VO

GM

TPS40100

1

2

24

23

19

20

11

SS

Reference

Select

+

Current

Mirror

RT SYNC

7 22

Oscillator

+

0.725 V

0.711 V

0.690 V

0.669 V

0.655 V

+

+

FUNCTIONAL BLOCK DIAGRAM

UVLO

5

CLK

PWM

20 kΩ

+

1.48 V

THERMSD

1.5 V

CLK

OC

1.33 V

10 µA

+

OC/SS

Controller

+

OC

FAULT

CLK

OC

FAULT

UVLO

Adaptive

Drive

Prebias

Control

Reference

Gate

and

Voltages

SLUS601–MAY 2005

15 BST

16 HDRV

17 SW

14 5VBP

13 LDRV

12 PGND

21 PG

TRKOUT

3

4TRKIN

+

6

ILIM

10

SS

9

GND

Housekeeping

8

BIAS

18 VDD

UDG−04142

7

www.ti.com

TPS40100

SLUS601–MAY 2005

APPLICATION INFORMATION

Introduction

The TPS40100 is a synchronous buck controller targeted at applications that require sequencing and output
voltage margining features. This controller uses a current feedback mechanism to make loop compensation
easier for loads that can have wide capacitance variations. Current sensing (for both current feedback and
overcurrent) is true differential and can be done using the inductor DC resistance (with a R-C filter) or with a
separate sense resistor in series with the inductor. The overcurrent level is programmable independently from
the amount of current feedback providing greater application flexibility. Likewise, the overcurrent function has
user programmable integration to eliminate nuisance tripping and allow the user to tailor the response to
application requirements. The controller provides an integrated method to margin the output voltage to ± 3% and
± 5% of its nominal value by simply grounding one of two pins directly or through a resistance. Powergood and
clock synchronization functions are provided on dedicated pins. Users can program operating frequency and the
closed loop soft-start time by means of a resistor and capacitor to ground respectively. Output se­quencing/tracking can be accomplished in one of three ways: sequential (one output comes up, then a second
comes up), ratiometric (one or more outputs reach regulation at the same time – the voltages all follow a
constant ration while starting) and simultaneous (one or more outputs track together on startup and reach
regulation in order from lowest to highest).

Programming Operating Frequency

Operating frequency is set by connecting a resistor to GND from the RT pin. The relationship is:

ȡ

RT+

where

Figure 1 and Figure 2 show the relationship between the switching frequency and the RTresistor as described in
Equation 1. The scaling is different between them to allow the user a more accurate views at both high and low

frequency.

* 3.98 10

ȧ

f

Ȣ

• fSWis the switching frequency in kHz

• R

SW

is in kΩ

T

ȣ

4

2

ȧ
Ȥ

)

5.14 10

ǒ

f

SW

4

Ǔ

* 8.6 (kW)

(1)

8

TPS40100

www.ti.com

APPLICATION INFORMATION (continued)

− Timing Resistance − kΩ
R

T

225

200

175

150

125

100

75

50

250

TIMING RESISTOR TIMING RESISTOR

SWITCHING FREQUENCY SWITCHING FREQUENCY

(250 kHz to 600 kHz) (100 kHz to 350 kHz)

350300 400 500450 600550

f

− Switching Frequency − kHz

SW

vs vs

Figure 1. Figure 2.

SLUS601–MAY 2005

550

500

450

400

350

300

250

− Timing Resistance − kΩ

T

200

R

150

100

100

150 200 250 350300

f − Switching Frequency − kHz

Selecting an Inductor Value

The inductor value determines the ripple current in the output capacitors and has an effect on the achievable
transient response. A large inductance decreases ripple current and output voltage ripple, but is physically larger
than a smaller inductance at the same current rating and limits output current slew rate more that a smaller
inductance would. A lower inductance increases ripple current and output voltage ripple, but is physically smaller
than a larger inductance at the same current rating. For most applications, a good compromise is selecting an
inductance value that gives a ripple current between 20% and 30% of the full load current of the converter. The
required inductance for a given ripple current can be found from:

L +

ǒ

VIN* V

VIN fSW DI

OUT

Ǔ

V

OUT

(H)

(2)

where

• L is the inductance value (H)

• V

is the input voltage to the converter (V)

IN

• V

• f

•∆I is the peak-to-peak ripple current in the inductor (A)

is the output voltage of the converter (V)

OUT

is the switching frequency chosen for the converter (Hz)

SW

Selecting the Output Capacitance

The required value for the output capacitance depends on the output ripple voltage requirements and the ripple
current in the inductor, as well as any load transient specifications that may exist.

The output voltage ripple depends directly on the ripple current and is affected by two parameters from the
output capacitor: total capacitance and the capacitors equivalent series resistance (ESR). The output ripple
voltage (worst case) can be found from:

9

www.ti.com

TPS40100

SLUS601–MAY 2005

APPLICATION INFORMATION (continued)

DV + DI

ESR ) ǒ

ƪ

8 C

1

OUT

f

SW

Ǔ

(V)

ƫ

(3)

where

•∆V is the peak to peak output ripple voltage (V)

•∆I is the peak-to-peak ripple current in the inductor (A)

• f

is the switching frequency chosen for the converter (Hz)

SW

• C

• ESR is the equivalent series resistance of the capacitor, C

is the capacitance value of the output capacitor (F)

OUT

OUT

(Ω)

For electrolytic capacitors, the output ripple voltage is almost entirely (90% or more) due to the ESR of the
capacitor. When using ceramic output capacitors, the output ripple contribution from ESR is much smaller and
the capacitance value itself becomes more significant. Paralleling output capacitors to achieve a desired output
capacitance generally lowers the effective ESR more effectively than using a single larger capacitor. This
increases performance at the expense of board area.

If there are load transient requirements that must be met, the overshoot and undershoot of the output voltage
must be considered. If the load suddenly increases, the output voltage momentarily dips until the c urrent in the
inductor can ramp up to match the new load requirement. If the feedback loop is designed aggressively, this
undershoot can be minimized. For a given undershoot specification, the required output capacitance can be
found by:

C

O(under)

+

2 V

UNDER

L I

D

STEP

ǒVIN* V

MAX

2

(F)

Ǔ

OUT

(4)

where

• C

• L is the inductor value (H)

• I

STEP

• V

• D

• V

• V

is the output capacitance required to meet the undershoot specification (F)

O(under)

is the change in load current (A)

is the maximum allowable output voltage undershoot

UNDER

is the maximum duty cycle for the converter

MAX

is the input voltage

IN

is the output voltage

OUT

Similarly, if the load current suddenly goes from a high value to a low value, the output voltage overshoots. The
ouput voltage rises until the current in the inductor drops to the new load current. The required capacitance for a
given amount of overshoot can be found by:

C

O(over)

+

2 V

L I

OVER

STEP

V

2

OUT

(F)

(5)

where

• C

• L in the inductor value (H)

• I

• V

• V

The required value of output capacitance is the maximum of C

is the output capacitance required to meet the undershoot specification (F)

O(over)

is the change in load current (A)

STEP

is the maximum allowable output voltage overshoot

OVER

is the output voltage

OUT

O(under)

and C

O(over)

.

Knowing the inductor ripple current, the switching frequency, the required load step and the allowable output
voltage excursion allows calculation of the required output capacitance from a transient response perspective.
The actual value and type of output capacitance is the one that satisfies both the ripple and transient
specifications.

10

TPS40100

www.ti.com

SLUS601–MAY 2005

APPLICATION INFORMATION (continued)

Calculating the Current Sense Filter Network

The TPS 40100 gets current feedback information by sensing the voltage across the inductor resistance, R
order to do this, a filter must be constructed that allows the sensed voltage to be representative of the actual
current in the inductor. This filter is a series R-C network connected across the inductor as shown in Figure 3.

V

IN

To ISNS pin

R

FLT

L

R

C

LDC

FLT

To VO pin

100 Ω

V

O

C

O

UDG−04150

Figure 3. Current Sensing Filter Circuit

If the R

FLT-CFLT

voltage across R
condition (100 nF is suggested). R

R

FLT

time constant is matched to the L/R

. It is recommended to keep R

+

LDC

L

R

C

LDC

* 100 (W)

FLT

can then be calculated.

FLT

time constant, the voltage across C

LDC

10 kΩ or less. C

FLT

can be arbitrarily chosen to meet this

FLT

is equal to the

FLT

where

• R

• C

• L is the output inductance (H)

• R

When laying out the board, better performance can be accomplished by locating C

is the current sense filter resistance (Ω)

FLT

is the current sense filter capacitance (F)

FLT

is the DC resistance of the output inductor (Ω)

LDC

as close as possible to the

FLT

VO and ISNS pins. The closer the two resistors can be brought to the device the better as this reduces the
length of high impedance runs that are susceptible to noise pickup. The 100-Ω resistor from V

to the VO pin

OUT

of the device is to limit current in the event that the output voltage dips below ground when a short is applied to
the output of the converter.

LDC

.In

(6)

Compensation for Inductor Resistance Change Over Temperature

The resistance in the inductor that is sensed is the resistance of the copper winding. This value changes over
temperature and has approximately a 4000 ppm/°C temperature coefficient. The gain of current sense amplifier
in the TPS40100 has a built in temperature coefficient of approximately -2000 ppm/°C. If the circuit is physically
arranged so that there is good thermal coupling between the inductor and the device, the thermal shifts tend to
offset. If the thermal coupling is perfect, the net temperature coefficient is 2000 ppm/°C. If the coupling is not
perfect, the net temperature coefficient lies between 2000 ppm/°C and 4000 ppm/°C. For most applications this is
sufficient. If desired, the temperature drifts can be compensated for. The following compensation scheme
assumes that the temperature rise at the device is directly proportional to the temperature rise at the inductor. If
this is not the case, compensation accuracy suffers. Also, there is generally a time lag in the temperature rise at
the device vs. at the inductor that could introduce transient errors beyond those predicted by the compensation.

Also, the 100-Ω resistor in Figure 3 is not shown. However, it is required if the output voltage can dip below
ground during fault conditions. The calculations are not afffected, other than increasing the effective value of R
by 100-Ω.

F1

11

www.ti.com

TPS40100

SLUS601–MAY 2005

APPLICATION INFORMATION (continued)

The relative resistance change in the inductor is given by:

R

+ 1 ) TCL ǒTL* T

REL(L)

where

• R

• TCLis the temperature coefficient of copper, 4000 ppm/°C or 0.004

• T

• T

is the relative resistance of the inductor at TLcompared to the resistance at T

REL(L)

is the inductor copper temperature (°C)

L

is the reference temperature, typically lowest ambient (°C)

BASE

The relative gain of the current sense amplifier is given by a similar equation:

gm

+ 1 ) TCGM ǒTIC* T

(REL)

where

• gm

• TCGMis the temperature coefficient of the amplifier gain, -2000 ppm/°C or -0.002

• T

• T

is the relative gain of the amplifier at TICcompared to the gain at T

REL

is the device junction temperature (°C)

IC

is the reference temperature, typically lowest ambient (°C)

BASE

The temperature rise of the device can usually be related to the temperature rise of the inductor. The relationship
between the two temperature rises can be approximated as a linear relationship in most cases:

TIC* T

BASE

+ǒTL* T

BASE

where

• TICis the device junction temperature (°C)

• T

• T

• k

is the reference temperature, typically lowest ambient (°C)

BASE

is the inductor copper temperature (°C)

L

is the constant that relates device temperature rise to the inductor temperature rise and must be

THM

determined experimentally for any given design

BASE

Ǔ

k

Ǔ

(dimensionless)

Ǔ

BASE

THM

(dimensionless)

(7)

BASE

(8)

BASE

(9)

With these assumptions, the effective inductor resistance over temperature is:

R

REL(eff)

R

REL(eff)

+ R

REL(L)

gm

+ƪ1 ) TC

REL

ǒ

TL* T

L

is the relative effective resistance that must be compensated for when doing the compensation. The

BASE

Ǔƫ

ƪ1 ) k

TCGM ǒTL* T

THM

BASE

Ǔƫ

(dimensionless)

circuit of Figure 4 shows a method of compensating for thermal shifts in current limit. The NTC thermistor (R
must be well coupled to the inductor. C

should be located as close to the device as possible.

FLT

(10)

NTC

)

12