TEXAS INSTRUMENTS TPS40060, TPS40061 Technical data

8

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SLUS543D–DECEMBER 2002–REVISED SEPTEMBER 2004

WIDE-INPUT SYNCHRONOUS BUCK CONTROLLER

FEATURES DESCRIPTION

• Operating Input Voltage 10 V to 55 V

• Input Voltage Feed-Forward Compensation

• < 1% Internal 0.7-V Reference

• Programmable Fixed-Frequency, Up to 1-MHz

Voltage Mode Controller

• Internal Gate Drive Outputs for High-Side
P-Channel and Synchronous N-Channel
MOSFETs

• 16-Pin PowerPAD™ Package (θJC=2°C/W)

• Thermal Shutdown

• Externally Synchronizable

• Programmable High-Side Sense Short Circuit

Protection

• Programmable Closed-Loop Soft-Start

• TPS40060 Source Only/TPS40061 Source/Sink

The TPS40060 and TPS40061 are high-voltage, wide
input (10 V to 55 V) synchronous, step-down con­verters.

This family of devices offers design flexibility with a
variety of user programmable functions, including;
soft-start, UVLO, operating frequency, voltage
feed-forward, high-side current limit, and loop com­pensation. These devices are also synchronizable to
an external supply.

The TPS40060 and TPS40061 incorporate MOSFET
gate drivers for external P-channel high-side and
N-channel synchronous rectifier (SR) MOSFETs.
Gate drive logic incorporates anti-cross conduction
circuitry to prevent simultaneous high-side and
synchronous rectifier conduction.

TPS40060
TPS40061

APPLICATIONS

• Networking Equipment

• Telecom Equipment

• Base Stations

• Servers

SIMPLIFIED APPLICATION DIAGRAM

TPS40060PWP

1

KFF

2

IN

RT

3

BP5

4

SYNC

5

SGND

SS/SD

VFB

7

COMP

8

HDRV

BPN10

LDRV

PGND

ILIM

VIN

SW

BP10

16

15

14

13

12

116

10

+

V

OUT

9

-

UDG-02157

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Copyright © 2002–2004, Texas Instruments Incorporated

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TPS40060
TPS40061

SLUS543D–DECEMBER 2002–REVISED SEPTEMBER 2004

These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION

T

A

–40°Cto85°C

(1) The PWP package is alsoavailable taped and reeled. Add an R suffix to the device type (i.e.,TPS40060PWPR). See the application

section of the data sheet for PowerPADdrawing and layout information.

(2) See ApplicationInformation section.

LOAD CURRENT PACKAGE

SOURCE

SOURCE/SIN

(2)

(2)

Plastic HTSSOP (PWP) TPS40060PWP

Plastic HTSSOP (PWP) TPS40061PWP

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted

VIN 60 V

VFB, SS/SD, SYNC –0.3 V to 6 V

V

V

I

I

T

T

(1) Stresses beyond thoselisted under "absolute maximum ratings" may cause permanent damage to thedevice. These are stress ratings

Input voltage range

IN

Output voltage range COMP, RT, KFF, SS –0.3 V to 6 V

OUT

Input current KFF 5mA

IN

Output current RT 200 µA

OUT

Operating junction temperature range –40°C to 125°C

J

Storage temperature –55°C to 150°C

stg

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C

only, and functional operation of the deviceat these or any other conditions beyond those indicated under "recommendedoperating
conditions" is not implied. Exposure to absolute-maximum-ratedconditions for extended periods may affect devicereliability.

SW

SW. transient < 50 ns –2.5 V

(1)

(1)

PART NUMBER

TPS40060
TPS40061

–0.3 V to 60 V or VIN+5 V

(whichever is less)

RECOMMENDED OPERATING CONDITIONS

V

T

2

Input voltage 10 55 V

IN

Operating free-air temperature –40 85 °C

A

PAD

(1)(2)

16
15
14
13
12
11
10

ILIM
VIN
HDRV
BPN10
SW
BP10
LDRV

9

PGND

PWP PACKAGE

(TOP VIEW)

KFF

RT

BP5

SYNC

SGND

SS/SD

VFB

COMP

(1) For more information on the PWP package, refer to TI Technical Brief (SLMA002).

(2) PowerPAD™ heat slug must be connected to SGND (Pin 5), or electrically isolated from all other pins.

1
2
3
4
5
6
7
8

THERMAL

MIN NOM MAX UNIT

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ELECTRICAL CHARACTERISTICS

TA= –40°Cto85°C, VIN=24Vdc,RT= 165 kΩ,I
otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

INPUT SUPPLY

V

OPERATING CURRENT

I

5-V REFERENCE

V

OSCILLATOR/RAMP GENERATOR

f

V

V

V

I

V

V

I

SS/SD (SOFT START)

I

V

t

t

SS/SD (SHUTDOWN)

V

V

10-V REFERENCE

V

ERROR AMPLIFIER

V

G

A

I

I

I

V

V

(1) KFF current(I
(2) Ensured by design. Notproduction tested.
(3) Ensured by design. Notproduction tested.

Input voltage range, VIN 10 55 V

IN

Quiescent current Output drivers not switching 1.5 2.5 mA

DD

Input voltage 4.5 5.0 5.5 V

BP5

Frequency 270 300 330 kHz

OSC

PWM ramp voltage

RAMP

High-level input voltage, SYNC 2V

IH

Low-level input voltage, SYNC 0.8

IL

Input current, SYNC 510µA

SYNC

(2)

(1)

Pulse width, SYNC Pulse amplitude = 5 V 50 ns

RT voltage 2.32 2.50 2.68 V

RT

Maximum duty cycle VFB= 0 V, 100 kHz ≤ fSW≤ 1 MHz 85% 98%

Minumum duty cycle VFB≥ 0.75 V 0%

Feed-forward voltage 3.35 3.50 3.65 V

KFF

Feed-forward current operating range

KFF

Soft-start source current 1.8 2.3 2.9 µA

SS

Soft-start clamp voltage 3.1 3.7 4.0 V

SS

Discharge time CSS= 220 pF 1.8 2.2 2.8

DSCH

Soft-start time CSS= 220 pF, 0 V ≤ VSS≤ 1.6 V 120 155 190

SS

Shutdown threshold voltage 90 120 145 mV

SD

Device action threshold voltage 160 210 260 mV

EN

Input voltage 9.0 9.7 10.7 V

BP10

Feedback regulation voltage 0°C ≤ TA≤ 85°C 0.690 0.700 0.707 V

FB

Gain bandwidth 3 5 MHz

BW

Open loop gain 60 80 dB

VOL

High-level output source current V

OH

Low-level output sink current V

OL

Input bias current VFB= 0.7 V 100 300 nA

BIAS

High-level output voltage IOH= 0.5 mA, VFB= 0 V 3.25 3.45 3.60

OH

Low-level output voltage IOL= 0.5 mA, VFB= 1 V 0.050 0.215 0.350

OL

) increases with SYNC frequency(f

KFF

(3)

TPS40060
TPS40061

SLUS543D–DECEMBER 2002–REVISED SEPTEMBER 2004

= 113 µA, fSW= 300 kHz, all parameters at zero power dissipation (unless

KFF

2

20 1100 µA

TA=25°C 0.698 0.700 0.704

0.690 0.700 0.715

= 2.0 V, VFB=0V 1.5 4.0

COMP

= 2.0 V, VFB=1V 2.5 4.0

COMP

) and decreases with maximum dutycycle (D

SYNC

MAX

).

µs

mA

V

3

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TPS40060
TPS40061

SLUS543D–DECEMBER 2002–REVISED SEPTEMBER 2004

ELECTRICAL CHARACTERISTICS (continued)

TA= –40°Cto85°C, VIN=24Vdc,RT= 165 kΩ,I
otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

CURRENT LIMIT

I

t

t

t

V

OUTPUT DRIVER

t

t

t

t

V

V

V

V

BPN10 REGULATOR

V

0

RECTIFIER ZERO CURRENT COMPARATOR (TPS40060 ONLY)

V

SW NODE

I

THERMAL SHUTDOWN

T

UNDERVOLTAGE LOCKOUT

V

V

Current limit sink current 8.3 10.0 11.5 µA

SINK

Propagation delay to output

DELAY

Switch leading-edge blanking pulse time

ON

Off time during a fault 7 cycles

OFF

Overcurrent comparator offset voltage -200 -60 50 mV

OS

High-side driver fall time

HFALL

High-side driver rise time

HRISE

Low-side driver fall time

LFALL

Low-side driver rise time

LRISE

High-level ouput voltage, HDRV I

OH

Low-level ouput voltage, HDRV I

OL

High-level ouput voltage, LDRV I

OH

Low-level ouput voltage, LDRV I

OL

(4)

(4)

(4)

(4)

(4)

Minimum controllable pulse width 100 150 ns

BPN1

Output voltage Outputs off –7.5 –8.5 –9.5 V

Switch voltage LDRV output OFF –6 0 6 mV

SW

Leakage current

LEAK

Shutdown temperature

SD

Hysteresis

Undervoltage lockout threshold voltage, BP10 R

UVLO

(4)

(4)

(4)

Undervoltage lockout hysteresis 0.4 V

KFF programmable threshold voltage R

KFF

= 113 µA, fSW= 300 kHz, all parameters at zero power dissipation (unless

KFF

V

= 23.7 V, VSW=(V

ILIM

V

= 23.7 V, VSW=(V

ILIM

C

HDRV

C

HDRV

C

LDRV

C

LDRV

=0.1A,(VIN–V

HDRV

=0.1A,(V

HDRV

= 0.1 A, (V

LDRV

= 0.1 A 0.5

LDRV

=10kΩ 6.25 6.5 7.5

KFF

= 82.5 kΩ 91011

KFF

– 0.5 V) 330 500

ILIM

– 2 V) 275 375 ns

ILIM

100

= 2200 pF, (VIN–V

= 2200 pF, (VIN–V

)4896

BPN10

)3672

BPN10

= 2200 pF, BP10 24 48

= 2200 pF, BP10 48 96

)1.01.4

HDRV

HDRV–VBPN10

BP10–VLDRV

)0.75

)1.01.5

165

25

ns

V

1µA

°C

(4) Ensured by design. Notproduction tested.

4

TPS40060

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SLUS543D–DECEMBER 2002–REVISED SEPTEMBER 2004

Terminal Functions

TERMINAL

NAME NO.

BP5 3 O

BP10 11 O

BPN10 13 O

COMP 8 I VFB pin to compensate the overall loop. The comp pin is internally clamped above the peak of the ramp to

HDRV 14 O

ILIM 16 I voltage drop across an external resistor connected from this pin to VIN. The voltage on this pin is compared to the

KFF 1 I

LDRV 10 I

PGND 9

RT 2 I

SGND 5 Signal ground reference for the device.

SS/SD 6 I 0.85 V. The output continues to rise and reaches regulation when V

SW 12 I

SYNC 4 I

VFB 7 I

VIN 15 I Supply voltage for the device.

I/O DESCRIPTION

5-V reference. This pin should be bypassed to ground with a 0.1-µF ceramic capacitor. This pin may be used with
an external DC load of 1 mA or less.

10-V reference used for gate drive of the N-channel synchronous rectifier. This pin should be bypassed by a 1-µF
ceramic capacitor. This pin may be used with an external DC load of 1 mA or less.

Negative 8-V reference with respect to VIN. This voltage is used to provide gate drive for the high side P-channel
MOSFET. This pin should be bypassed to VIN with a 0.1-µF capacitor

Output of the error amplifier, input to the PWM comparator. A feedback network is connected from this pin to the

improve large signal transient response.

Floating gate drive for the high-side P-channel MOSFET. This pin switches from VIN (MOSFET off) to BPN10
(MOSFET on).

Current limit pin, used to set the overcurrent threshold. An internal current sink from this pin to ground sets a

voltage drop (VIN -SW) across the high side MOSFET during conduction.

A resistor is connected from this pin to VIN to program the amount of voltage feed-forward. The current fed into
this pin is internally divided and used to control the slope of the PWM ramp.

Gate drive for the N-channel synchronous rectifier. This pin switches from BP10 (MOSFET on) to ground
(MOSFET off).

Power ground reference for the device. There should be a low-impedance connection from this point to the source
of the power MOSFET.

A resistor is connected from this pin to ground to set the internal oscillator ramp charging current and switching
frequency.

Soft-start programming pin. A capacitor connected from this pin to ground programs the soft-start time. The
capacitor is charged with an internal current source of 2.3 µA. The resulting voltage ramp on the SS pin is used as
a second non-inverting input to the error amplifier. The output voltage begins to rise when V

considered shut down when V
enabled when V
switching and the output voltage (V

This pin is connected to the switched node of the converter and used for overcurrent sensing. This pin is used for
zero current sensing in the TPS40060.

Synchronization input for the device. This pin can be used to synchronize the oscillator to an external master
frequency.

Inverting input to the error amplifier. In normal operation the voltage on this pin is equal to the internal reference
voltage, 0.7 V.

is 210 mV or greater. When V

SS/SD

is 125 mV or less. All internal circuitry is inactive. The internal circuitry is

SS/SD

) decays while the internal circuitry remains active.

OUT

is less than approximately 0.85 V, the outputs cease

SS/SD

is approximately 1.55 V. The controller is

SS/SD

SS/SD

TPS40061

is approximately

5

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TPS40060
TPS40061

SLUS543D–DECEMBER 2002–REVISED SEPTEMBER 2004

SIMPLIFIED BLOCK DIAGRAM

VIN

ILIM

16

BP10

BP10

1115

RT

SYNC

KFF

BP5

COMP

VFB

SS/SD

2

4

Ramp Generator

1

BP5

3

8

7

7

6

7

Restart

Clock

Oscillator

7

07VREF

+

+

+

0.85 V

5

SGND

CLK

07VREF

7

10−V Regulator

Reference

Voltages

Fault

7

CL

7

+

7

CLK

+

07VREF

1V5REF

3V5REF

SQ

1V5REF

BP5

QR

CLK

7

7

7

7

3−bit up/down
Fault Counter

7

7

7

Restart

SW

7

Zero Current Detector

(TPS40060 Only)

7

7

Fault

7 HDRV

CL

BP10

7

SQ

QR

VIN

7

P-Channel

Driver

7

BPN10

N-Channel

Driver

7

HDRV

7

UDG−02160

13

14

12

10

9

BPN10

HDRV

SW

LDRV

PGND

6

TPS40060

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SLUS543D–DECEMBER 2002–REVISED SEPTEMBER 2004

APPLICATION INFORMATION

The TPS40060/61 family of parts allows the user to optimize the PWM controller to the specific application.

The TPS40061 is the controller of choice for synchronous buck designs which will include most applications. It
has two quadrant operation and will source or sink output current. This provides the best transient response.

The TPS40060 operates in one quadrant and sources output current only, allowing for paralleling of converters
and ensures that one converter does not sink current from another converter. This controller also emulates a
standard buck converter at light loads where the inductor current goes discontinuous. At continuous output
inductor currents the controller operates as a synchronous buck converter to optimize efficiency.

SW NODE RESISTOR

The SW node of the converter will be negative during the dead time when both the upper and lower MOSFETs
are off. The magnitude of this negative voltage is dependent on the lower MOSFET body diode and the output
current which flows during this dead time. This negative voltage could affect the operation of the controller,
especially at low input voltages.

Therefore, a 10-Ω resistor must be placed between the lower MOSFET drain and pin 12 (SW) of the controller as
shown in Figure 13 as RSW.

SETTING THE SWITCHING FREQUENCY (PROGRAMMING THE CLOCK OSCILLATOR)

The TPS40060 and TPS40061 have independent clock oscillator and ramp generator circuits. The clock
oscillator serves as the master clock to the ramp generator circuit. The switching frequency, fSWin kHz, of the
clock oscillator is set by a single resistor (RT) to ground. The clock frequency is related to RT,inkΩ by
Equation 1 and the relationship is charted in Figure 2.

TPS40061

RT+

ǒ

fSW 17.82 10

1

* 23ǓkW

*6

(1)

PROGRAMMING THE RAMP GENERATOR CIRCUIT

The ramp generator circuit provides the actual ramp used by the PWM comparator. The ramp generator provides
voltage feed-forward control by varying the P WM ramp slope with line voltage, while maintaining a constant ramp
magnitude. Varying the PWM ramp directly with line voltage provides excellent response to line variations since
the PWM does not have to wait for loop delays before changing the duty cycle. (See Figure 1).

VIN

VIN

SW

V

PEAK

COMP

RAMP

t

ON1

d +

1

t

ON

T

t

t

ON2

ON1

> t

and d1> d

ON2

T

2

2

T

Figure 1. Voltage Feed-Forward Effect on PWM Duty Cycle

SW

RAMP

COMP

V

VALLEY

UDG-02131

7

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100

0

200

300

400

500

600

400 600 800 1000

700

200

800

FEED-FORWARD IMPEDANCE

vs

SWITCHING FREQUENCY

R

KFF

- Feed-Forward Impedance - kΩ

fSW - Switching Frequency - kHz

VIN= 25 V

VIN= 15 V

VIN= 9 V

TPS40060
TPS40061

SLUS543D–DECEMBER 2002–REVISED SEPTEMBER 2004

APPLICATION INFORMATION (continued)

The PWM ramp must be faster than the master clock frequency or the PWM is prevented from starting. The
PWM ramp time is programmed via a single resistor (R
minimum input voltage, V

R

KFF

+ǒV

IN (min)

* 3.5Ǔ ǒ65.27 RT) 1502Ǔ(W)

through the following:

IN(min)

where:

• VINis the desired start-up (UVLO) input voltage

• R

is the timing resistor in kΩ

T

See the section on UVLO operation for further description.

The curve showing the feedforward impedance required for a given switching frequency, fSW, at various input
voltages is shown in Figure 3.

For low input voltage and high duty cycle applications, the voltage feed-forward may limit the duty cycle
prematurely. This does not occur for most applications. The voltage control loop controls the duty cycle and
regulates the output voltages. For more information on large duty cycle operation, refer to Application Note
(SLUA310).

) pulled up to VIN.R

KFF

is related to RT, and the

KFF

(2)

TIMING RESISTANCE

600

500

400

300

200

- Timing Resistance - kΩ

T

R

100

0

0

SWITCHING FREQUENCY

200 400 600 800 1000

fSW - Switching Frequency - kHz

Figure 2. Figure 3.

vs

UVLO OPERATION

The TPS40060 and TPS40061 use both fixed and variable (user programmable) UVLO protection. The fixed
UVLO monitors the BP10 and BP5 bypass voltages. The UVLO circuit holds the soft-start low until the BP5 and
BP10 voltage rails have exceeded their thresholds and the input voltage has exceed the user programmable
undervoltage threshold.

The TPS40060 and TPS40061 use the feed-forward pin, KFF, as a user programmable low-line UVLO detection.
This variable low-line UVLO threshold compares the PWM ramp duration to the oscillator clock period. An
undervoltage condition existis if the device receives a clock pulse before the ramp has reached 90% of its full
amplitude. The ramp duration is a function of the ramp slope, which is directly related to the current into the KFF
pin. The KFF current is a function of the input voltage and the resistance from KFF to the input voltage. The KFF
resistor can be referenced to the oscillator frequency as descibed in Equation 3:

8